rtl/verilog/or1200_ic_top.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  OR1200's Data Cache top level                               ////
   4 ////                                                              ////
   5 ////  This file is part of the OpenRISC 1200 project              ////
   6 ////  http://www.opencores.org/cores/or1k/                        ////
   7 ////                                                              ////
   8 ////  Description                                                 ////
   9 ////  Instantiation of all IC blocks.                             ////
  10 ////                                                              ////
  11 ////  To Do:                                                      ////
  12 ////   - make it smaller and faster                               ////
  13 ////                                                              ////
  14 ////  Author(s):                                                  ////
  15 ////      - Damjan Lampret, lampret@opencores.org                 ////
  16 ////                                                              ////
  17 //////////////////////////////////////////////////////////////////////
  18 ////                                                              ////
  19 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
  20 ////                                                              ////
  21 //// This source file may be used and distributed without         ////
  22 //// restriction provided that this copyright statement is not    ////
  23 //// removed from the file and that any derivative work contains  ////
  24 //// the original copyright notice and the associated disclaimer. ////
  25 ////                                                              ////
  26 //// This source file is free software; you can redistribute it   ////
  27 //// and/or modify it under the terms of the GNU Lesser General   ////
  28 //// Public License as published by the Free Software Foundation; ////
  29 //// either version 2.1 of the License, or (at your option) any   ////
  30 //// later version.                                               ////
  31 ////                                                              ////
  32 //// This source is distributed in the hope that it will be       ////
  33 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  34 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  35 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  36 //// details.                                                     ////
  37 ////                                                              ////
  38 //// You should have received a copy of the GNU Lesser General    ////
  39 //// Public License along with this source; if not, download it   ////
  40 //// from http://www.opencores.org/lgpl.shtml                     ////
  41 ////                                                              ////
  42 //////////////////////////////////////////////////////////////////////
  43 //
  44 // CVS Revision History
  45 //
  46 // $Log$
  47 // Revision 1.6  2002/03/29 15:16:55  lampret
  48 // Some of the warnings fixed.
  49 //
  50 // Revision 1.5  2002/02/11 04:33:17  lampret
  51 // Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
  52 //
  53 // Revision 1.4  2002/02/01 19:56:54  lampret
  54 // Fixed combinational loops.
  55 //
  56 // Revision 1.3  2002/01/28 01:16:00  lampret
  57 // Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
  58 //
  59 // Revision 1.2  2002/01/14 06:18:22  lampret
  60 // Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
  61 //
  62 // Revision 1.1  2002/01/03 08:16:15  lampret
  63 // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
  64 //
  65 // Revision 1.10  2001/10/21 17:57:16  lampret
  66 // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
  67 //
  68 // Revision 1.9  2001/10/14 13:12:09  lampret
  69 // MP3 version.
  70 //
  71 // Revision 1.1.1.1  2001/10/06 10:18:35  igorm
  72 // no message
  73 //
  74 // Revision 1.4  2001/08/13 03:36:20  lampret
  75 // Added cfg regs. Moved all defines into one defines.v file. More cleanup.
  76 //
  77 // Revision 1.3  2001/08/09 13:39:33  lampret
  78 // Major clean-up.
  79 //
  80 // Revision 1.2  2001/07/22 03:31:53  lampret
  81 // Fixed RAM's oen bug. Cache bypass under development.
  82 //
  83 // Revision 1.1  2001/07/20 00:46:03  lampret
  84 // Development version of RTL. Libraries are missing.
  85 //
  86 //
  87
  88 // synopsys translate_off
  89 `include "timescale.v"
  90 // synopsys translate_on
  91 `include "or1200_defines.v"
  92
  93 //
  94 // Data cache
  95 //
  96 module or1200_ic_top(
  97         // Rst, clk and clock control
  98         clk, rst,
  99
 100         // External i/f
 101         icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
 102         icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
 103
 104         // Internal i/f
 105         ic_en,
 106         icimmu_adr_i, icimmu_cycstb_i, icimmu_ci_i,
 107         icpu_sel_i, icpu_tag_i,
 108         icpu_dat_o, icpu_ack_o, icimmu_rty_o, icimmu_err_o, icimmu_tag_o,
 109
 110         // SPRs
 111         spr_cs, spr_write, spr_dat_i
 112 );
 113
 114 parameter dw = `OR1200_OPERAND_WIDTH;
 115
 116 //
 117 // I/O
 118 //
 119
 120 //
 121 // Clock and reset
 122 //
 123 input                           clk;
 124 input                           rst;
 125
 126 //
 127 // External I/F
 128 //
 129 output  [dw-1:0]                icbiu_dat_o;
 130 output  [31:0]                  icbiu_adr_o;
 131 output                          icbiu_cyc_o;
 132 output                          icbiu_stb_o;
 133 output                          icbiu_we_o;
 134 output  [3:0]                   icbiu_sel_o;
 135 output                          icbiu_cab_o;
 136 input   [dw-1:0]                icbiu_dat_i;
 137 input                           icbiu_ack_i;
 138 input                           icbiu_err_i;
 139
 140 //
 141 // Internal I/F
 142 //
 143 input                           ic_en;
 144 input   [31:0]                  icimmu_adr_i;
 145 input                           icimmu_cycstb_i;
 146 input                           icimmu_ci_i;
 147 input   [3:0]                   icpu_sel_i;
 148 input   [3:0]                   icpu_tag_i;
 149 output  [dw-1:0]                icpu_dat_o;
 150 output                          icpu_ack_o;
 151 output                          icimmu_rty_o;
 152 output                          icimmu_err_o;
 153 output  [3:0]                   icimmu_tag_o;
 154
 155 //
 156 // SPR access
 157 //
 158 input                           spr_cs;
 159 input                           spr_write;
 160 input   [31:0]                  spr_dat_i;
 161
 162 //
 163 // Internal wires and regs
 164 //
 165 wire                            tag_v;
 166 wire    [`OR1200_ICTAG_W-2:0]   tag;
 167 wire    [dw-1:0]                to_icram;
 168 wire    [dw-1:0]                from_icram;
 169 wire    [31:0]                  saved_addr;
 170 wire    [3:0]                   icram_we;
 171 wire                            ictag_we;
 172 wire    [31:0]                  ic_addr;
 173 wire                            icfsm_biu_read;
 174 reg                             tagcomp_miss;
 175 wire    [`OR1200_ICINDXH:`OR1200_ICLS]  ictag_addr;
 176 wire                            ictag_en;
 177 wire                            ictag_v;
 178 wire                            ic_inv;
 179 wire                            icfsm_first_hit_ack;
 180 wire                            icfsm_first_miss_ack;
 181 wire                            icfsm_first_miss_err;
 182 wire                            icfsm_burst;
 183 wire                            icfsm_tag_we;
 184
 185 //
 186 // Simple assignments
 187 //
 188 assign icbiu_adr_o = ic_addr;
 189 assign ic_inv = spr_cs & spr_write;
 190 assign ictag_we = icfsm_tag_we | ic_inv;
 191 assign ictag_addr = ic_inv ? spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] : ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
 192 assign ictag_en = ic_inv | ic_en;
 193 assign ictag_v = ~ic_inv;
 194
 195 //
 196 // Data to BIU is from ICRAM when IC is enabled or from LSU when
 197 // IC is disabled
 198 //
 199 assign icbiu_dat_o = 32'h00000000;
 200
 201 //
 202 // Bypases of the IC when IC is disabled
 203 //
 204 assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icimmu_cycstb_i;
 205 assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icimmu_cycstb_i;
 206 assign icbiu_we_o = 1'b0;
 207 assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icpu_sel_i;
 208 assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
 209 assign icimmu_rty_o = ~icpu_ack_o & ~icimmu_err_o;
 210 assign icimmu_tag_o = icimmu_err_o ? `OR1200_ITAG_BE : icpu_tag_i;
 211
 212 //
 213 // CPU normal and error termination
 214 //
 215 assign icpu_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
 216 assign icimmu_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
 217
 218 //
 219 // Select between claddr generated by IC FSM and addr[3:2] generated by LSU
 220 //
 221 assign ic_addr = (icfsm_biu_read) ? saved_addr : icimmu_adr_i;
 222
 223 //
 224 // Select between input data generated by LSU or by BIU
 225 //
 226 assign to_icram = icbiu_dat_i;
 227
 228 //
 229 // Select between data generated by ICRAM or passed by BIU
 230 //
 231 assign icpu_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
 232
 233 //
 234 // Tag comparison
 235 //
 236 always @(tag or saved_addr or tag_v) begin
 237         if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v)
 238                 tagcomp_miss = 1'b1;
 239         else
 240                 tagcomp_miss = 1'b0;
 241 end
 242
 243 //
 244 // Instantiation of IC Finite State Machine
 245 //
 246 or1200_ic_fsm or1200_ic_fsm(
 247         .clk(clk),
 248         .rst(rst),
 249         .ic_en(ic_en),
 250         .icimmu_cycstb_i(icimmu_cycstb_i),
 251         .icimmu_ci_i(icimmu_ci_i),
 252         .tagcomp_miss(tagcomp_miss),
 253         .biudata_valid(icbiu_ack_i),
 254         .biudata_error(icbiu_err_i),
 255         .start_addr(icimmu_adr_i),
 256         .saved_addr(saved_addr),
 257         .icram_we(icram_we),
 258         .biu_read(icfsm_biu_read),
 259         .first_hit_ack(icfsm_first_hit_ack),
 260         .first_miss_ack(icfsm_first_miss_ack),
 261         .first_miss_err(icfsm_first_miss_err),
 262         .burst(icfsm_burst),
 263         .tag_we(icfsm_tag_we)
 264 );
 265
 266 //
 267 // Instantiation of IC main memory
 268 //
 269 or1200_ic_ram or1200_ic_ram(
 270         .clk(clk),
 271         .rst(rst),
 272         .addr(ic_addr[`OR1200_ICINDXH:2]),
 273         .en(ic_en),
 274         .we(icram_we),
 275         .datain(to_icram),
 276         .dataout(from_icram)
 277 );
 278
 279 //
 280 // Instantiation of IC TAG memory
 281 //
 282 or1200_ic_tag or1200_ic_tag(
 283         .clk(clk),
 284         .rst(rst),
 285         .addr(ictag_addr),
 286         .en(ictag_en),
 287         .we(ictag_we),
 288         .datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
 289         .tag_v(tag_v),
 290         .tag(tag)
 291 );
 292
 293 endmodule