?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
history | HEAD | snapshot (tar.gz zip)
Default ASIC configuration does not sample WB inputs.
[or1200.git] / sim / 
tree11da1a2c7038558ca8adb19a690a5855a24ef22f
drwxr-xr-x   ..
-rwxr-xr-x 355 run.sh blob | blame | history | raw
32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities