drivers/video/via/hw.h

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #ifndef __HW_H__
  23 #define __HW_H__
  24
  25 #include "viamode.h"
  26 #include "global.h"
  27 #include "via_modesetting.h"
  28
  29 #define viafb_read_reg(p, i)                    via_read_reg(p, i)
  30 #define viafb_write_reg(i, p, d)                via_write_reg(p, i, d)
  31 #define viafb_write_reg_mask(i, p, d, m)        via_write_reg_mask(p, i, d, m)
  32
  33 /***************************************************
  34 * Definition IGA1 Design Method of CRTC Registers *
  35 ****************************************************/
  36 #define IGA1_HOR_TOTAL_FORMULA(x)           (((x)/8)-5)
  37 #define IGA1_HOR_ADDR_FORMULA(x)            (((x)/8)-1)
  38 #define IGA1_HOR_BLANK_START_FORMULA(x)     (((x)/8)-1)
  39 #define IGA1_HOR_BLANK_END_FORMULA(x, y)     (((x+y)/8)-1)
  40 #define IGA1_HOR_SYNC_START_FORMULA(x)      ((x)/8)
  41 #define IGA1_HOR_SYNC_END_FORMULA(x, y)      ((x+y)/8)
  42
  43 #define IGA1_VER_TOTAL_FORMULA(x)           ((x)-2)
  44 #define IGA1_VER_ADDR_FORMULA(x)            ((x)-1)
  45 #define IGA1_VER_BLANK_START_FORMULA(x)     ((x)-1)
  46 #define IGA1_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
  47 #define IGA1_VER_SYNC_START_FORMULA(x)      ((x)-1)
  48 #define IGA1_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
  49
  50 /***************************************************
  51 ** Definition IGA2 Design Method of CRTC Registers *
  52 ****************************************************/
  53 #define IGA2_HOR_TOTAL_FORMULA(x)           ((x)-1)
  54 #define IGA2_HOR_ADDR_FORMULA(x)            ((x)-1)
  55 #define IGA2_HOR_BLANK_START_FORMULA(x)     ((x)-1)
  56 #define IGA2_HOR_BLANK_END_FORMULA(x, y)     ((x+y)-1)
  57 #define IGA2_HOR_SYNC_START_FORMULA(x)      ((x)-1)
  58 #define IGA2_HOR_SYNC_END_FORMULA(x, y)      ((x+y)-1)
  59
  60 #define IGA2_VER_TOTAL_FORMULA(x)           ((x)-1)
  61 #define IGA2_VER_ADDR_FORMULA(x)            ((x)-1)
  62 #define IGA2_VER_BLANK_START_FORMULA(x)     ((x)-1)
  63 #define IGA2_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
  64 #define IGA2_VER_SYNC_START_FORMULA(x)      ((x)-1)
  65 #define IGA2_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
  66
  67 /**********************************************************/
  68 /* Definition IGA2 Design Method of CRTC Shadow Registers */
  69 /**********************************************************/
  70 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x)           ((x/8)-5)
  71 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y)     (((x+y)/8)-1)
  72 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x)           ((x)-2)
  73 #define IGA2_VER_ADDR_SHADOW_FORMULA(x)            ((x)-1)
  74 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x)     ((x)-1)
  75 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y)     ((x+y)-1)
  76 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x)      (x)
  77 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y)      (x+y)
  78
  79 /* Define Register Number for IGA1 CRTC Timing */
  80
  81 /* location: {CR00,0,7},{CR36,3,3} */
  82 #define IGA1_HOR_TOTAL_REG_NUM          2
  83 /* location: {CR01,0,7} */
  84 #define IGA1_HOR_ADDR_REG_NUM           1
  85 /* location: {CR02,0,7} */
  86 #define IGA1_HOR_BLANK_START_REG_NUM    1
  87 /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */
  88 #define IGA1_HOR_BLANK_END_REG_NUM      3
  89 /* location: {CR04,0,7},{CR33,4,4} */
  90 #define IGA1_HOR_SYNC_START_REG_NUM     2
  91 /* location: {CR05,0,4} */
  92 #define IGA1_HOR_SYNC_END_REG_NUM       1
  93 /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */
  94 #define IGA1_VER_TOTAL_REG_NUM          4
  95 /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */
  96 #define IGA1_VER_ADDR_REG_NUM           4
  97 /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */
  98 #define IGA1_VER_BLANK_START_REG_NUM    4
  99 /* location: {CR16,0,7} */
 100 #define IGA1_VER_BLANK_END_REG_NUM      1
 101 /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */
 102 #define IGA1_VER_SYNC_START_REG_NUM     4
 103 /* location: {CR11,0,3} */
 104 #define IGA1_VER_SYNC_END_REG_NUM       1
 105
 106 /* Define Register Number for IGA2 Shadow CRTC Timing */
 107
 108 /* location: {CR6D,0,7},{CR71,3,3} */
 109 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM       2
 110 /* location: {CR6E,0,7} */
 111 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM   1
 112 /* location: {CR6F,0,7},{CR71,0,2} */
 113 #define IGA2_SHADOW_VER_TOTAL_REG_NUM       2
 114 /* location: {CR70,0,7},{CR71,4,6} */
 115 #define IGA2_SHADOW_VER_ADDR_REG_NUM        2
 116 /* location: {CR72,0,7},{CR74,4,6} */
 117 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
 118 /* location: {CR73,0,7},{CR74,0,2} */
 119 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM   2
 120 /* location: {CR75,0,7},{CR76,4,6} */
 121 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM  2
 122 /* location: {CR76,0,3} */
 123 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM    1
 124
 125 /* Define Register Number for IGA2 CRTC Timing */
 126
 127 /* location: {CR50,0,7},{CR55,0,3} */
 128 #define IGA2_HOR_TOTAL_REG_NUM          2
 129 /* location: {CR51,0,7},{CR55,4,6} */
 130 #define IGA2_HOR_ADDR_REG_NUM           2
 131 /* location: {CR52,0,7},{CR54,0,2} */
 132 #define IGA2_HOR_BLANK_START_REG_NUM    2
 133 /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6]
 134 is reserved, so it may have problem to set 1600x1200 on IGA2. */
 135 /*              Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */
 136 #define IGA2_HOR_BLANK_END_REG_NUM      3
 137 /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */
 138 /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */
 139 #define IGA2_HOR_SYNC_START_REG_NUM     4
 140
 141 /* location: {CR57,0,7},{CR5C,6,6} */
 142 #define IGA2_HOR_SYNC_END_REG_NUM       2
 143 /* location: {CR58,0,7},{CR5D,0,2} */
 144 #define IGA2_VER_TOTAL_REG_NUM          2
 145 /* location: {CR59,0,7},{CR5D,3,5} */
 146 #define IGA2_VER_ADDR_REG_NUM           2
 147 /* location: {CR5A,0,7},{CR5C,0,2} */
 148 #define IGA2_VER_BLANK_START_REG_NUM    2
 149 /* location: {CR5E,0,7},{CR5C,3,5} */
 150 #define IGA2_VER_BLANK_END_REG_NUM      2
 151 /* location: {CR5E,0,7},{CR5F,5,7} */
 152 #define IGA2_VER_SYNC_START_REG_NUM     2
 153 /* location: {CR5F,0,4} */
 154 #define IGA2_VER_SYNC_END_REG_NUM       1
 155
 156 /* Define Fetch Count Register*/
 157
 158 /* location: {SR1C,0,7},{SR1D,0,1} */
 159 #define IGA1_FETCH_COUNT_REG_NUM        2
 160 /* 16 bytes alignment. */
 161 #define IGA1_FETCH_COUNT_ALIGN_BYTE     16
 162 /* x: H resolution, y: color depth */
 163 #define IGA1_FETCH_COUNT_PATCH_VALUE    4
 164 #define IGA1_FETCH_COUNT_FORMULA(x, y)   \
 165         (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
 166
 167 /* location: {CR65,0,7},{CR67,2,3} */
 168 #define IGA2_FETCH_COUNT_REG_NUM        2
 169 #define IGA2_FETCH_COUNT_ALIGN_BYTE     16
 170 #define IGA2_FETCH_COUNT_PATCH_VALUE    0
 171 #define IGA2_FETCH_COUNT_FORMULA(x, y)   \
 172         (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
 173
 174 /* Staring Address*/
 175
 176 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
 177 #define IGA1_STARTING_ADDR_REG_NUM      4
 178 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
 179 #define IGA2_STARTING_ADDR_REG_NUM      3
 180
 181 /* Define Display OFFSET*/
 182 /* These value are by HW suggested value*/
 183 /* location: {SR17,0,7} */
 184 #define K800_IGA1_FIFO_MAX_DEPTH                384
 185 /* location: {SR16,0,5},{SR16,7,7} */
 186 #define K800_IGA1_FIFO_THRESHOLD                328
 187 /* location: {SR18,0,5},{SR18,7,7} */
 188 #define K800_IGA1_FIFO_HIGH_THRESHOLD           296
 189 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
 190                                 /* because HW only 5 bits */
 191 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
 192
 193 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 194 #define K800_IGA2_FIFO_MAX_DEPTH                384
 195 /* location: {CR68,0,3},{CR95,4,6} */
 196 #define K800_IGA2_FIFO_THRESHOLD                328
 197 /* location: {CR92,0,3},{CR95,0,2} */
 198 #define K800_IGA2_FIFO_HIGH_THRESHOLD           296
 199 /* location: {CR94,0,6} */
 200 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
 201
 202 /* location: {SR17,0,7} */
 203 #define P880_IGA1_FIFO_MAX_DEPTH                192
 204 /* location: {SR16,0,5},{SR16,7,7} */
 205 #define P880_IGA1_FIFO_THRESHOLD                128
 206 /* location: {SR18,0,5},{SR18,7,7} */
 207 #define P880_IGA1_FIFO_HIGH_THRESHOLD           64
 208 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
 209                                 /* because HW only 5 bits */
 210 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
 211
 212 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 213 #define P880_IGA2_FIFO_MAX_DEPTH                96
 214 /* location: {CR68,0,3},{CR95,4,6} */
 215 #define P880_IGA2_FIFO_THRESHOLD                64
 216 /* location: {CR92,0,3},{CR95,0,2} */
 217 #define P880_IGA2_FIFO_HIGH_THRESHOLD           32
 218 /* location: {CR94,0,6} */
 219 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
 220
 221 /* VT3314 chipset*/
 222
 223 /* location: {SR17,0,7} */
 224 #define CN700_IGA1_FIFO_MAX_DEPTH               96
 225 /* location: {SR16,0,5},{SR16,7,7} */
 226 #define CN700_IGA1_FIFO_THRESHOLD               80
 227 /* location: {SR18,0,5},{SR18,7,7} */
 228 #define CN700_IGA1_FIFO_HIGH_THRESHOLD          64
 229 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
 230                                 because HW only 5 bits */
 231 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     0
 232 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 233 #define CN700_IGA2_FIFO_MAX_DEPTH               96
 234 /* location: {CR68,0,3},{CR95,4,6} */
 235 #define CN700_IGA2_FIFO_THRESHOLD               80
 236 /* location: {CR92,0,3},{CR95,0,2} */
 237 #define CN700_IGA2_FIFO_HIGH_THRESHOLD          32
 238 /* location: {CR94,0,6} */
 239 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
 240
 241 /* For VT3324, these values are suggested by HW */
 242 /* location: {SR17,0,7} */
 243 #define CX700_IGA1_FIFO_MAX_DEPTH               192
 244 /* location: {SR16,0,5},{SR16,7,7} */
 245 #define CX700_IGA1_FIFO_THRESHOLD               128
 246 /* location: {SR18,0,5},{SR18,7,7} */
 247 #define CX700_IGA1_FIFO_HIGH_THRESHOLD          128
 248 /* location: {SR22,0,4} */
 249 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
 250
 251 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 252 #define CX700_IGA2_FIFO_MAX_DEPTH               96
 253 /* location: {CR68,0,3},{CR95,4,6} */
 254 #define CX700_IGA2_FIFO_THRESHOLD               64
 255 /* location: {CR92,0,3},{CR95,0,2} */
 256 #define CX700_IGA2_FIFO_HIGH_THRESHOLD          32
 257 /* location: {CR94,0,6} */
 258 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
 259
 260 /* VT3336 chipset*/
 261 /* location: {SR17,0,7} */
 262 #define K8M890_IGA1_FIFO_MAX_DEPTH               360
 263 /* location: {SR16,0,5},{SR16,7,7} */
 264 #define K8M890_IGA1_FIFO_THRESHOLD               328
 265 /* location: {SR18,0,5},{SR18,7,7} */
 266 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD          296
 267 /* location: {SR22,0,4}. */
 268 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
 269
 270 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 271 #define K8M890_IGA2_FIFO_MAX_DEPTH               360
 272 /* location: {CR68,0,3},{CR95,4,6} */
 273 #define K8M890_IGA2_FIFO_THRESHOLD               328
 274 /* location: {CR92,0,3},{CR95,0,2} */
 275 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD          296
 276 /* location: {CR94,0,6} */
 277 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     124
 278
 279 /* VT3327 chipset*/
 280 /* location: {SR17,0,7} */
 281 #define P4M890_IGA1_FIFO_MAX_DEPTH               96
 282 /* location: {SR16,0,5},{SR16,7,7} */
 283 #define P4M890_IGA1_FIFO_THRESHOLD               76
 284 /* location: {SR18,0,5},{SR18,7,7} */
 285 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD          64
 286 /* location: {SR22,0,4}. (32/4) =8 */
 287 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
 288 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 289 #define P4M890_IGA2_FIFO_MAX_DEPTH               96
 290 /* location: {CR68,0,3},{CR95,4,6} */
 291 #define P4M890_IGA2_FIFO_THRESHOLD               76
 292 /* location: {CR92,0,3},{CR95,0,2} */
 293 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD          64
 294 /* location: {CR94,0,6} */
 295 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
 296
 297 /* VT3364 chipset*/
 298 /* location: {SR17,0,7} */
 299 #define P4M900_IGA1_FIFO_MAX_DEPTH               96
 300 /* location: {SR16,0,5},{SR16,7,7} */
 301 #define P4M900_IGA1_FIFO_THRESHOLD               76
 302 /* location: {SR18,0,5},{SR18,7,7} */
 303 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD          76
 304 /* location: {SR22,0,4}. */
 305 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
 306 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 307 #define P4M900_IGA2_FIFO_MAX_DEPTH               96
 308 /* location: {CR68,0,3},{CR95,4,6} */
 309 #define P4M900_IGA2_FIFO_THRESHOLD               76
 310 /* location: {CR92,0,3},{CR95,0,2} */
 311 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD          76
 312 /* location: {CR94,0,6} */
 313 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
 314
 315 /* For VT3353, these values are suggested by HW */
 316 /* location: {SR17,0,7} */
 317 #define VX800_IGA1_FIFO_MAX_DEPTH               192
 318 /* location: {SR16,0,5},{SR16,7,7} */
 319 #define VX800_IGA1_FIFO_THRESHOLD               152
 320 /* location: {SR18,0,5},{SR18,7,7} */
 321 #define VX800_IGA1_FIFO_HIGH_THRESHOLD          152
 322 /* location: {SR22,0,4} */
 323 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      64
 324 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 325 #define VX800_IGA2_FIFO_MAX_DEPTH               96
 326 /* location: {CR68,0,3},{CR95,4,6} */
 327 #define VX800_IGA2_FIFO_THRESHOLD               64
 328 /* location: {CR92,0,3},{CR95,0,2} */
 329 #define VX800_IGA2_FIFO_HIGH_THRESHOLD          32
 330 /* location: {CR94,0,6} */
 331 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
 332
 333 /* For VT3409 */
 334 #define VX855_IGA1_FIFO_MAX_DEPTH               400
 335 #define VX855_IGA1_FIFO_THRESHOLD               320
 336 #define VX855_IGA1_FIFO_HIGH_THRESHOLD          320
 337 #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     160
 338
 339 #define VX855_IGA2_FIFO_MAX_DEPTH               200
 340 #define VX855_IGA2_FIFO_THRESHOLD               160
 341 #define VX855_IGA2_FIFO_HIGH_THRESHOLD          160
 342 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     320
 343
 344 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM          1
 345 #define IGA1_FIFO_THRESHOLD_REG_NUM             2
 346 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM        2
 347 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
 348
 349 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM          3
 350 #define IGA2_FIFO_THRESHOLD_REG_NUM             2
 351 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM        2
 352 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
 353
 354 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)                   ((x/2)-1)
 355 #define IGA1_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
 356 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
 357 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
 358 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)                   (((x/2)/4)-1)
 359 #define IGA2_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
 360 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
 361 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
 362
 363 /************************************************************************/
 364 /*  LCD Timing                                                          */
 365 /************************************************************************/
 366
 367 /* 500 ms = 500000 us */
 368 #define LCD_POWER_SEQ_TD0               500000
 369 /* 50 ms = 50000 us */
 370 #define LCD_POWER_SEQ_TD1               50000
 371 /* 0 us */
 372 #define LCD_POWER_SEQ_TD2               0
 373 /* 210 ms = 210000 us */
 374 #define LCD_POWER_SEQ_TD3               210000
 375 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
 376 #define CLE266_POWER_SEQ_UNIT           71
 377 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
 378 #define K800_POWER_SEQ_UNIT             142
 379 /* 2^13 * (1/14.31818M) = 572.1 us */
 380 #define P880_POWER_SEQ_UNIT             572
 381
 382 #define CLE266_POWER_SEQ_FORMULA(x)     ((x)/CLE266_POWER_SEQ_UNIT)
 383 #define K800_POWER_SEQ_FORMULA(x)       ((x)/K800_POWER_SEQ_UNIT)
 384 #define P880_POWER_SEQ_FORMULA(x)       ((x)/P880_POWER_SEQ_UNIT)
 385
 386 /* location: {CR8B,0,7},{CR8F,0,3} */
 387 #define LCD_POWER_SEQ_TD0_REG_NUM       2
 388 /* location: {CR8C,0,7},{CR8F,4,7} */
 389 #define LCD_POWER_SEQ_TD1_REG_NUM       2
 390 /* location: {CR8D,0,7},{CR90,0,3} */
 391 #define LCD_POWER_SEQ_TD2_REG_NUM       2
 392 /* location: {CR8E,0,7},{CR90,4,7} */
 393 #define LCD_POWER_SEQ_TD3_REG_NUM       2
 394
 395 /* LCD Scaling factor*/
 396 /* x: indicate setting horizontal size*/
 397 /* y: indicate panel horizontal size*/
 398
 399 /* Horizontal scaling factor 10 bits (2^10) */
 400 #define CLE266_LCD_HOR_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
 401 /* Vertical scaling factor 10 bits (2^10) */
 402 #define CLE266_LCD_VER_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
 403 /* Horizontal scaling factor 10 bits (2^12) */
 404 #define K800_LCD_HOR_SCF_FORMULA(x, y)     (((x-1)*4096)/(y-1))
 405 /* Vertical scaling factor 10 bits (2^11) */
 406 #define K800_LCD_VER_SCF_FORMULA(x, y)     (((x-1)*2048)/(y-1))
 407
 408 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
 409 #define LCD_HOR_SCALING_FACTOR_REG_NUM  3
 410 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
 411 #define LCD_VER_SCALING_FACTOR_REG_NUM  3
 412 /* location: {CR77,0,7},{CR79,4,5} */
 413 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE  2
 414 /* location: {CR78,0,7},{CR79,6,7} */
 415 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE  2
 416
 417 /************************************************
 418  *****     Define IGA1 Display Timing       *****
 419  ************************************************/
 420 struct io_register {
 421         u8 io_addr;
 422         u8 start_bit;
 423         u8 end_bit;
 424 };
 425
 426 /* IGA1 Horizontal Total */
 427 struct iga1_hor_total {
 428         int reg_num;
 429         struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
 430 };
 431
 432 /* IGA1 Horizontal Addressable Video */
 433 struct iga1_hor_addr {
 434         int reg_num;
 435         struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
 436 };
 437
 438 /* IGA1 Horizontal Blank Start */
 439 struct iga1_hor_blank_start {
 440         int reg_num;
 441         struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
 442 };
 443
 444 /* IGA1 Horizontal Blank End */
 445 struct iga1_hor_blank_end {
 446         int reg_num;
 447         struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
 448 };
 449
 450 /* IGA1 Horizontal Sync Start */
 451 struct iga1_hor_sync_start {
 452         int reg_num;
 453         struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
 454 };
 455
 456 /* IGA1 Horizontal Sync End */
 457 struct iga1_hor_sync_end {
 458         int reg_num;
 459         struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
 460 };
 461
 462 /* IGA1 Vertical Total */
 463 struct iga1_ver_total {
 464         int reg_num;
 465         struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
 466 };
 467
 468 /* IGA1 Vertical Addressable Video */
 469 struct iga1_ver_addr {
 470         int reg_num;
 471         struct io_register reg[IGA1_VER_ADDR_REG_NUM];
 472 };
 473
 474 /* IGA1 Vertical Blank Start */
 475 struct iga1_ver_blank_start {
 476         int reg_num;
 477         struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
 478 };
 479
 480 /* IGA1 Vertical Blank End */
 481 struct iga1_ver_blank_end {
 482         int reg_num;
 483         struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
 484 };
 485
 486 /* IGA1 Vertical Sync Start */
 487 struct iga1_ver_sync_start {
 488         int reg_num;
 489         struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
 490 };
 491
 492 /* IGA1 Vertical Sync End */
 493 struct iga1_ver_sync_end {
 494         int reg_num;
 495         struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
 496 };
 497
 498 /*****************************************************
 499 **      Define IGA2 Shadow Display Timing         ****
 500 *****************************************************/
 501
 502 /* IGA2 Shadow Horizontal Total */
 503 struct iga2_shadow_hor_total {
 504         int reg_num;
 505         struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
 506 };
 507
 508 /* IGA2 Shadow Horizontal Blank End */
 509 struct iga2_shadow_hor_blank_end {
 510         int reg_num;
 511         struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
 512 };
 513
 514 /* IGA2 Shadow Vertical Total */
 515 struct iga2_shadow_ver_total {
 516         int reg_num;
 517         struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
 518 };
 519
 520 /* IGA2 Shadow Vertical Addressable Video */
 521 struct iga2_shadow_ver_addr {
 522         int reg_num;
 523         struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
 524 };
 525
 526 /* IGA2 Shadow Vertical Blank Start */
 527 struct iga2_shadow_ver_blank_start {
 528         int reg_num;
 529         struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
 530 };
 531
 532 /* IGA2 Shadow Vertical Blank End */
 533 struct iga2_shadow_ver_blank_end {
 534         int reg_num;
 535         struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
 536 };
 537
 538 /* IGA2 Shadow Vertical Sync Start */
 539 struct iga2_shadow_ver_sync_start {
 540         int reg_num;
 541         struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
 542 };
 543
 544 /* IGA2 Shadow Vertical Sync End */
 545 struct iga2_shadow_ver_sync_end {
 546         int reg_num;
 547         struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
 548 };
 549
 550 /*****************************************************
 551 **      Define IGA2 Display Timing                ****
 552 ******************************************************/
 553
 554 /* IGA2 Horizontal Total */
 555 struct iga2_hor_total {
 556         int reg_num;
 557         struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
 558 };
 559
 560 /* IGA2 Horizontal Addressable Video */
 561 struct iga2_hor_addr {
 562         int reg_num;
 563         struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
 564 };
 565
 566 /* IGA2 Horizontal Blank Start */
 567 struct iga2_hor_blank_start {
 568         int reg_num;
 569         struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
 570 };
 571
 572 /* IGA2 Horizontal Blank End */
 573 struct iga2_hor_blank_end {
 574         int reg_num;
 575         struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
 576 };
 577
 578 /* IGA2 Horizontal Sync Start */
 579 struct iga2_hor_sync_start {
 580         int reg_num;
 581         struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
 582 };
 583
 584 /* IGA2 Horizontal Sync End */
 585 struct iga2_hor_sync_end {
 586         int reg_num;
 587         struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
 588 };
 589
 590 /* IGA2 Vertical Total */
 591 struct iga2_ver_total {
 592         int reg_num;
 593         struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
 594 };
 595
 596 /* IGA2 Vertical Addressable Video */
 597 struct iga2_ver_addr {
 598         int reg_num;
 599         struct io_register reg[IGA2_VER_ADDR_REG_NUM];
 600 };
 601
 602 /* IGA2 Vertical Blank Start */
 603 struct iga2_ver_blank_start {
 604         int reg_num;
 605         struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
 606 };
 607
 608 /* IGA2 Vertical Blank End */
 609 struct iga2_ver_blank_end {
 610         int reg_num;
 611         struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
 612 };
 613
 614 /* IGA2 Vertical Sync Start */
 615 struct iga2_ver_sync_start {
 616         int reg_num;
 617         struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
 618 };
 619
 620 /* IGA2 Vertical Sync End */
 621 struct iga2_ver_sync_end {
 622         int reg_num;
 623         struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
 624 };
 625
 626 /* IGA1 Fetch Count Register */
 627 struct iga1_fetch_count {
 628         int reg_num;
 629         struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
 630 };
 631
 632 /* IGA2 Fetch Count Register */
 633 struct iga2_fetch_count {
 634         int reg_num;
 635         struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
 636 };
 637
 638 struct fetch_count {
 639         struct iga1_fetch_count iga1_fetch_count_reg;
 640         struct iga2_fetch_count iga2_fetch_count_reg;
 641 };
 642
 643 /* Starting Address Register */
 644 struct iga1_starting_addr {
 645         int reg_num;
 646         struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
 647 };
 648
 649 struct iga2_starting_addr {
 650         int reg_num;
 651         struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
 652 };
 653
 654 struct starting_addr {
 655         struct iga1_starting_addr iga1_starting_addr_reg;
 656         struct iga2_starting_addr iga2_starting_addr_reg;
 657 };
 658
 659 /* LCD Power Sequence Timer */
 660 struct lcd_pwd_seq_td0 {
 661         int reg_num;
 662         struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
 663 };
 664
 665 struct lcd_pwd_seq_td1 {
 666         int reg_num;
 667         struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
 668 };
 669
 670 struct lcd_pwd_seq_td2 {
 671         int reg_num;
 672         struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
 673 };
 674
 675 struct lcd_pwd_seq_td3 {
 676         int reg_num;
 677         struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
 678 };
 679
 680 struct _lcd_pwd_seq_timer {
 681         struct lcd_pwd_seq_td0 td0;
 682         struct lcd_pwd_seq_td1 td1;
 683         struct lcd_pwd_seq_td2 td2;
 684         struct lcd_pwd_seq_td3 td3;
 685 };
 686
 687 /* LCD Scaling Factor */
 688 struct _lcd_hor_scaling_factor {
 689         int reg_num;
 690         struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
 691 };
 692
 693 struct _lcd_ver_scaling_factor {
 694         int reg_num;
 695         struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
 696 };
 697
 698 struct _lcd_scaling_factor {
 699         struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
 700         struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
 701 };
 702
 703 struct pll_map {
 704         u32 clk;
 705         u32 cle266_pll;
 706         u32 k800_pll;
 707         u32 cx700_pll;
 708         u32 vx855_pll;
 709 };
 710
 711 struct rgbLUT {
 712         u8 red;
 713         u8 green;
 714         u8 blue;
 715 };
 716
 717 struct lcd_pwd_seq_timer {
 718         u16 td0;
 719         u16 td1;
 720         u16 td2;
 721         u16 td3;
 722 };
 723
 724 /* Display FIFO Relation Registers*/
 725 struct iga1_fifo_depth_select {
 726         int reg_num;
 727         struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
 728 };
 729
 730 struct iga1_fifo_threshold_select {
 731         int reg_num;
 732         struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
 733 };
 734
 735 struct iga1_fifo_high_threshold_select {
 736         int reg_num;
 737         struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
 738 };
 739
 740 struct iga1_display_queue_expire_num {
 741         int reg_num;
 742         struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
 743 };
 744
 745 struct iga2_fifo_depth_select {
 746         int reg_num;
 747         struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
 748 };
 749
 750 struct iga2_fifo_threshold_select {
 751         int reg_num;
 752         struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
 753 };
 754
 755 struct iga2_fifo_high_threshold_select {
 756         int reg_num;
 757         struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
 758 };
 759
 760 struct iga2_display_queue_expire_num {
 761         int reg_num;
 762         struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
 763 };
 764
 765 struct fifo_depth_select {
 766         struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
 767         struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
 768 };
 769
 770 struct fifo_threshold_select {
 771         struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
 772         struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
 773 };
 774
 775 struct fifo_high_threshold_select {
 776         struct iga1_fifo_high_threshold_select
 777          iga1_fifo_high_threshold_select_reg;
 778         struct iga2_fifo_high_threshold_select
 779          iga2_fifo_high_threshold_select_reg;
 780 };
 781
 782 struct display_queue_expire_num {
 783         struct iga1_display_queue_expire_num
 784          iga1_display_queue_expire_num_reg;
 785         struct iga2_display_queue_expire_num
 786          iga2_display_queue_expire_num_reg;
 787 };
 788
 789 struct iga1_crtc_timing {
 790         struct iga1_hor_total hor_total;
 791         struct iga1_hor_addr hor_addr;
 792         struct iga1_hor_blank_start hor_blank_start;
 793         struct iga1_hor_blank_end hor_blank_end;
 794         struct iga1_hor_sync_start hor_sync_start;
 795         struct iga1_hor_sync_end hor_sync_end;
 796         struct iga1_ver_total ver_total;
 797         struct iga1_ver_addr ver_addr;
 798         struct iga1_ver_blank_start ver_blank_start;
 799         struct iga1_ver_blank_end ver_blank_end;
 800         struct iga1_ver_sync_start ver_sync_start;
 801         struct iga1_ver_sync_end ver_sync_end;
 802 };
 803
 804 struct iga2_shadow_crtc_timing {
 805         struct iga2_shadow_hor_total hor_total_shadow;
 806         struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
 807         struct iga2_shadow_ver_total ver_total_shadow;
 808         struct iga2_shadow_ver_addr ver_addr_shadow;
 809         struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
 810         struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
 811         struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
 812         struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
 813 };
 814
 815 struct iga2_crtc_timing {
 816         struct iga2_hor_total hor_total;
 817         struct iga2_hor_addr hor_addr;
 818         struct iga2_hor_blank_start hor_blank_start;
 819         struct iga2_hor_blank_end hor_blank_end;
 820         struct iga2_hor_sync_start hor_sync_start;
 821         struct iga2_hor_sync_end hor_sync_end;
 822         struct iga2_ver_total ver_total;
 823         struct iga2_ver_addr ver_addr;
 824         struct iga2_ver_blank_start ver_blank_start;
 825         struct iga2_ver_blank_end ver_blank_end;
 826         struct iga2_ver_sync_start ver_sync_start;
 827         struct iga2_ver_sync_end ver_sync_end;
 828 };
 829
 830 /* device ID */
 831 #define CLE266_FUNCTION3    0x3123
 832 #define KM400_FUNCTION3     0x3205
 833 #define CN400_FUNCTION2     0x2259
 834 #define CN400_FUNCTION3     0x3259
 835 /* support VT3314 chipset */
 836 #define CN700_FUNCTION2     0x2314
 837 #define CN700_FUNCTION3     0x3208
 838 /* VT3324 chipset */
 839 #define CX700_FUNCTION2     0x2324
 840 #define CX700_FUNCTION3     0x3324
 841 /* VT3204 chipset*/
 842 #define KM800_FUNCTION3      0x3204
 843 /* VT3336 chipset*/
 844 #define KM890_FUNCTION3      0x3336
 845 /* VT3327 chipset*/
 846 #define P4M890_FUNCTION3     0x3327
 847 /* VT3293 chipset*/
 848 #define CN750_FUNCTION3     0x3208
 849 /* VT3364 chipset*/
 850 #define P4M900_FUNCTION3    0x3364
 851 /* VT3353 chipset*/
 852 #define VX800_FUNCTION3     0x3353
 853 /* VT3409 chipset*/
 854 #define VX855_FUNCTION3     0x3409
 855
 856 #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
 857
 858 struct IODATA {
 859         u8 Index;
 860         u8 Mask;
 861         u8 Data;
 862 };
 863
 864 struct pci_device_id_info {
 865         u32 vendor;
 866         u32 device;
 867         u32 chip_index;
 868 };
 869
 870 extern unsigned int viafb_second_virtual_xres;
 871 extern int viafb_SAMM_ON;
 872 extern int viafb_dual_fb;
 873 extern int viafb_LCD2_ON;
 874 extern int viafb_LCD_ON;
 875 extern int viafb_DVI_ON;
 876 extern int viafb_hotplug;
 877
 878 void viafb_set_output_path(int device, int set_iga,
 879         int output_interface);
 880
 881 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
 882         struct VideoModeTable *video_mode, int bpp_byte, int set_iga);
 883
 884 void viafb_set_vclock(u32 CLK, int set_iga);
 885 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
 886         struct io_register *reg,
 887               int io_type);
 888 void viafb_crt_disable(void);
 889 void viafb_crt_enable(void);
 890 void init_ad9389(void);
 891 /* Access I/O Function */
 892 void viafb_lock_crt(void);
 893 void viafb_unlock_crt(void);
 894 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
 895 void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
 896 u32 viafb_get_clk_value(int clk);
 897 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
 898 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
 899                                         *p_gfx_dpa_setting);
 900
 901 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
 902         struct VideoModeTable *vmode_tbl1, int video_bpp1);
 903 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
 904         struct VideoModeTable *vmode_tbl);
 905 void viafb_init_chip_info(int chip_type);
 906 void viafb_init_dac(int set_iga);
 907 int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
 908 int viafb_get_refresh(int hres, int vres, u32 float_refresh);
 909 void viafb_update_device_setting(int hres, int vres, int bpp,
 910                            int vmode_refresh, int flag);
 911
 912 void viafb_set_iga_path(void);
 913 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
 914 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
 915 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
 916
 917 #endif /* __HW_H__ */