source/soc-codec/Kinets/kinets-adc-dac.h

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  * <liu090@sina.com>
   6  */
   7
   8 #ifndef _KINETS_K60DAC_H_
   9 #define _KINETS_K60DAC_H_
  10
  11 /* soc relation head file */
  12 //#include "dma/edma.h"
  13
  14 struct soc_dma_data {
  15         int priority;
  16         unsigned short fifo_aligned_bits;       /* fifo aligned bits in bit */
  17         unsigned short fifo_align_type;
  18       /*
  19         DAC_MemMapPtr dac0_base;
  20         DAC_MemMapPtr dac1_base;
  21       ADC_MemMapPtr adc0_base;
  22       ADC_MemMapPtr adc1_base;
  23       */
  24       volatile void * dev0_base;
  25       volatile void * dev1_base;
  26 };
  27
  28 typedef struct{
  29     uint32_t SADDR;                                  /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
  30     uint16_t SOFF;                                   /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
  31     uint16_t ATTR;                                   /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
  32     union {                                          /* offset: 0x1008, array step: 0x20 */
  33       uint32_t NBYTES_MLNO;                            /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
  34       uint32_t NBYTES_MLOFFNO;                         /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
  35       uint32_t NBYTES_MLOFFYES;                        /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
  36     };
  37     uint32_t SLAST;                                  /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
  38     uint32_t DADDR;                                  /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
  39     uint16_t DOFF;                                   /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
  40     union {                                          /* offset: 0x1016, array step: 0x20 */
  41       uint16_t CITER_ELINKYES;                         /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
  42       uint16_t CITER_ELINKNO;                          /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
  43     };
  44     uint32_t DLAST_SGA;                              /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
  45     uint16_t CSR;                                    /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
  46     union {                                          /* offset: 0x101E, array step: 0x20 */
  47       uint16_t BITER_ELINKNO;                          /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
  48       uint16_t BITER_ELINKYES;                         /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
  49     };
  50 } DMA_TCD_t, *DMA_TCD_p;
  51
  52 #define MAX_TCD_LISTS                            4   /* must match the number of periods  ! */
  53 #define FIFO_ALIGNMENT_TYPE_RIGHT       0x00
  54 #define FIFO_ALIGNMENT_TYPE_LEFT        0x01
  55
  56 #define FIFO_BITS_ALIGNED               16
  57 #define FIFO_BITS_ENDTYPES              FIFO_ALIGNMENT_TYPE_LEFT
  58
  59 /* Enable global DACx Interrup bit*/
  60 #define VECTOR_DAC0_INT_MASK    2
  61 #define VECTOR_DAC1_INT_MASK    4
  62
  63 /* DAXx registers reset values*/
  64 #define DACx_DAT_RESET                  0
  65 #define DACx_SR_RESET                   2
  66 #define DACx_C0_RESET                   0
  67 #define DACx_C1_RESET                   0
  68 #define DACx_C2_RESET                   15 //0x0f
  69
  70 /* DACx_C0 bits definition*/
  71
  72 #define DAC_DISABLE                             0x00
  73 #define DAC_ENABLE                              DAC_C0_DACEN_MASK
  74
  75 #define DAC_SEL_VREFO                   0x00
  76 #define DAC_SEL_VDDA                    DAC_C0_DACRFS_MASK
  77
  78 #define DAC_SEL_PDB_HW_TRIG     0x00
  79 #define DAC_SEL_SW_TRIG         DAC_C0_DACTRGSEL_MASK
  80
  81 #define DAC_SW_TRIG_STOP                0x00
  82 #define DAC_SW_TRIG_NEXT                DAC_C0_DACSWTRG_MASK
  83
  84 #define DAC_HP_MODE                     0x00
  85 #define DAC_LP_MODE                     DAC_C0_LPEN_MASK
  86
  87 #define DAC_BFWM_INT_DISABLE    0x00
  88 #define DAC_BFWM_INT_ENABLE     DAC_C0_DACBWIEN_MASK
  89
  90 #define DAC_BFT_PTR_INT_DISABLE 0x00
  91 #define DAC_BFT_PTR_INT_ENABLE          DAC_C0_DACBTIEN_MASK
  92
  93 #define DAC_BFB_PTR_INT_DISABLE 0x00
  94 #define DAC_BFB_PTR_INT_ENABLE  DAC_C0_DACBBIEN_MASK
  95
  96 /* DACx_C1 bits definition*/
  97 #define DAC_DMA_DISABLE         0x00
  98 #define DAC_DMA_ENABLE                  DAC_C1_DMAEN_MASK
  99
 100 #define DAC_BFWM_1WORD          DAC_C1_DACBFWM(0)
 101 #define DAC_BFWM_2WORDS         DAC_C1_DACBFWM(1)
 102 #define DAC_BFWM_3WORDS         DAC_C1_DACBFWM(2)
 103 #define DAC_BFWM_4WORDS         DAC_C1_DACBFWM(3)
 104
 105 #define DAC_BF_NORMAL_MODE      DAC_C1_DACBFMD(0)
 106 #define DAC_BF_SWING_MODE               DAC_C1_DACBFMD(1)
 107 #define DAC_BF_ONE_TIME_MODE    DAC_C1_DACBFMD(2)
 108
 109 #define DAC_BF_DISABLE                  0x00
 110 #define DAC_BF_ENABLE                   DAC_C1_DACBFEN_MASK
 111
 112 /* DACx_C2 bits definition*/
 113 #define DAC_SET_PTR_AT_BF(x)    DAC_C2_DACBFRP(x)
 114 #define DAC_SET_PTR_UP_LIMIT(x) DAC_C2_DACBFUP(x)
 115
 116
 117 #define Watermark_One_Word              0
 118 #define Watermark_Two_Words     1
 119 #define Watermark_Three_Words   2
 120 #define Watermark_Four_Words    3
 121
 122 #define Clear_DACBFWMF                  0x03
 123 #define Clear_DACBFRPTF                 0x05
 124 #define Clear_DACBFRPBF                 0x06
 125
 126 #define PDB_DACINTC0_TOE_MASK   0x1u
 127 ///////////////////////////////////////////
 128 #define DEFAULT_AUDIO_SAMPLERATE        44100
 129
 130 #define  DAM16WORD_TWICE
 131
 132 /* simulate */
 133 #define DMA_CHANNEL_DAC0                        0
 134
 135 #define DMA_CHANNEL_ADC1                        1
 136
 137 #ifdef DAM16WORD_TWICE
 138 #define DAC_BUFFER_SIZE                 (0x10)
 139 #else
 140 #define DAC_BUFFER_SIZE                 (0x10 * 2)
 141 #endif
 142 #define AUDIO_DMA_BUFFER_SIZE           0x200
 143 #define DMA_CH0_ISR_NUM                 0
 144 #define DMA_ERROR_ISR_NUM                       16
 145 #define DMA_REQUEST_DAC0                        45
 146 //#define DMA_REQUEST_DAC1                      46
 147 #define DMA_REQUEST_ADC1       /*MQX_EDMA_HARD_REQ_ADC1*/41
 148
 149 #define SAMPLE_RATE_44100HZ             44100
 150 #define SAMPLE_RATE_1KHZ                        1000
 151
 152 //#define DAC_TWO_CHANNEL
 153
 154
 155 // adc
 156 #define ADC_CFG2_ADLSTS_20             ADC_CFG2_ADLSTS(0)
 157 #define ADC_CFG2_ADLSTS_12             ADC_CFG2_ADLSTS(1)
 158 #define ADC_CFG2_ADLSTS_6              ADC_CFG2_ADLSTS(2)
 159 #define ADC_CFG2_ADLSTS_2              ADC_CFG2_ADLSTS(3)
 160 #define ADC_CFG2_ADLSTS_DEFAULT       (ADC_CFG2_ADLSTS_20)
 161
 162 #define ADC_SC3_AVGS_4                 ADC_SC3_AVGS(0x00)
 163 #define ADC_SC3_AVGS_8                 ADC_SC3_AVGS(0x01)
 164 #define ADC_SC3_AVGS_16                ADC_SC3_AVGS(0x02)
 165 #define ADC_SC3_AVGS_32                ADC_SC3_AVGS(0x03)
 166 #define ADC_SC3_AVGE                   ADC_SC3_AVGE_MASK
 167 #define ADC_SC3_ADCO                   ADC_SC3_ADCO_MASK
 168 #define ADC_SC3_CALF                   ADC_SC3_CALF_MASK
 169 #define ADC_SC3_CAL                    ADC_SC3_CAL_MASK
 170
 171 #define ADC_SC2_REFSEL_VREF            ADC_SC2_REFSEL(0x00)
 172 #define ADC_SC2_REFSEL_VALT            ADC_SC2_REFSEL(0x01)
 173 #define ADC_SC2_REFSEL_VBG             ADC_SC2_REFSEL(0x02)
 174
 175 #define ADC_SC1_ADCH_DISABLED          ADC_SC1_ADCH(0x1F)
 176
 177 #define ADC_CFG1_ADIV_1                ADC_CFG1_ADIV(0x00)
 178 #define ADC_CFG1_ADIV_2                ADC_CFG1_ADIV(0x01)
 179 #define ADC_CFG1_ADIV_4                ADC_CFG1_ADIV(0x02)
 180 #define ADC_CFG1_ADIV_8                ADC_CFG1_ADIV(0x03)
 181
 182 #define ADC_CFG1_ADICLK_BUSCLK         ADC_CFG1_ADICLK(0x00)
 183 #define ADC_CFG1_ADICLK_BUSCLK2        ADC_CFG1_ADICLK(0x01)
 184 #define ADC_CFG1_ADICLK_ALTCLK         ADC_CFG1_ADICLK(0x02)
 185 #define ADC_CFG1_ADICLK_ADACK          ADC_CFG1_ADICLK(0x03)
 186
 187
 188 //// ADCSC1 (register)
 189
 190 // Conversion Complete (COCO) mask
 191 #define COCO_COMPLETE     ADC_SC1_COCO_MASK
 192 #define COCO_NOT          0x00
 193
 194 // ADC interrupts: enabled, or disabled.
 195 #define AIEN_ON           ADC_SC1_AIEN_MASK
 196 #define AIEN_OFF          0x00
 197
 198 // Differential or Single ended ADC input
 199 #define DIFF_SINGLE       0x00
 200 #define DIFF_DIFFERENTIAL ADC_SC1_DIFF_MASK
 201
 202 //// ADCCFG1
 203 // Power setting of ADC
 204 #define ADLPC_LOW         ADC_CFG1_ADLPC_MASK
 205 #define ADLPC_NORMAL      0x00
 206
 207 // Clock divisor
 208 #define ADIV_1            0x00
 209 #define ADIV_2            0x01
 210 #define ADIV_4            0x02
 211 #define ADIV_8            0x03
 212
 213 // Long samle time, or Short sample time
 214 #define ADLSMP_LONG       ADC_CFG1_ADLSMP_MASK
 215 #define ADLSMP_SHORT      0x00
 216
 217 // How many bits for the conversion?  8, 12, 10, or 16 (single ended).
 218 #define MODE_8            0x00
 219 #define MODE_12           0x01
 220 #define MODE_10           0x02
 221 #define MODE_16           0x03
 222
 223 // ADC Input Clock Source choice? Bus clock, Bus clock/2, "altclk", or the
 224 //                                ADC's own asynchronous clock for less noise
 225 #define ADICLK_BUS        0x00
 226 #define ADICLK_BUS_2      0x01
 227 #define ADICLK_ALTCLK     0x02
 228 #define ADICLK_ADACK      0x03
 229
 230 //// ADCCFG2
 231
 232 // Select between B or A channels
 233 #define MUXSEL_ADCB       ADC_CFG2_MUXSEL_MASK
 234 #define MUXSEL_ADCA       0x00
 235
 236 // Ansync clock output enable: enable, or disable the output of it
 237 #define ADACKEN_ENABLED   ADC_CFG2_ADACKEN_MASK
 238 #define ADACKEN_DISABLED  0x00
 239
 240 // High speed or low speed conversion mode
 241 #define ADHSC_HISPEED     ADC_CFG2_ADHSC_MASK
 242 #define ADHSC_NORMAL      0x00
 243
 244 // Long Sample Time selector: 20, 12, 6, or 2 extra clocks for a longer sample time
 245 #define ADLSTS_20          0x00
 246 #define ADLSTS_12          0x01
 247 #define ADLSTS_6           0x02
 248 #define ADLSTS_2           0x03
 249
 250 ////ADCSC2
 251
 252 // Read-only status bit indicating conversion status
 253 #define ADACT_ACTIVE       ADC_SC2_ADACT_MASK
 254 #define ADACT_INACTIVE     0x00
 255
 256 // Trigger for starting conversion: Hardware trigger, or software trigger.
 257 // For using PDB, the Hardware trigger option is selected.
 258 #define ADTRG_HW           ADC_SC2_ADTRG_MASK
 259 #define ADTRG_SW           0x00
 260
 261 // ADC Compare Function Enable: Disabled, or Enabled.
 262 #define ACFE_DISABLED      0x00
 263 #define ACFE_ENABLED       ADC_SC2_ACFE_MASK
 264
 265 // Compare Function Greater Than Enable: Greater, or Less.
 266 #define ACFGT_GREATER      ADC_SC2_ACFGT_MASK
 267 #define ACFGT_LESS         0x00
 268
 269 // Compare Function Range Enable: Enabled or Disabled.
 270 #define ACREN_ENABLED      ADC_SC2_ACREN_MASK
 271 #define ACREN_DISABLED     0x00
 272
 273 // DMA enable: enabled or disabled.
 274 #define DMAEN_ENABLED      ADC_SC2_DMAEN_MASK
 275 #define DMAEN_DISABLED     0x00
 276
 277 // Voltage Reference selection for the ADC conversions
 278 // (***not*** the PGA which uses VREFO only).
 279 // VREFH and VREFL (0) , or VREFO (1).
 280
 281 #define REFSEL_EXT         0x00
 282 #define REFSEL_ALT         0x01
 283 #define REFSEL_RES         0x02     /* reserved */
 284 #define REFSEL_RES_EXT     0x03     /* reserved but defaults to Vref */
 285
 286 ////ADCSC3
 287
 288 // Calibration begin or off
 289 #define CAL_BEGIN          ADC_SC3_CAL_MASK
 290 #define CAL_OFF            0x00
 291
 292 // Status indicating Calibration failed, or normal success
 293 #define CALF_FAIL          ADC_SC3_CALF_MASK
 294 #define CALF_NORMAL        0x00
 295
 296 // ADC to continously convert, or do a sinle conversion
 297 #define ADCO_CONTINUOUS    ADC_SC3_ADCO_MASK
 298 #define ADCO_SINGLE        0x00
 299
 300 // Averaging enabled in the ADC, or not.
 301 #define AVGE_ENABLED       ADC_SC3_AVGE_MASK
 302 #define AVGE_DISABLED      0x00
 303
 304 // How many to average prior to "interrupting" the MCU?  4, 8, 16, or 32
 305 #define AVGS_4             0x00
 306 #define AVGS_8             0x01
 307 #define AVGS_16            0x02
 308 #define AVGS_32            0x03
 309
 310 ////PGA
 311
 312 // PGA enabled or not?
 313 #define PGAEN_ENABLED      ADC_PGA_PGAEN_MASK
 314 #define PGAEN_DISABLED     0x00
 315
 316 // Chopper stabilization of the amplifier, or not.
 317 #define PGACHP_CHOP        ADC_PGA_PGACHP_MASK
 318 #define PGACHP_NOCHOP      0x00
 319
 320 // PGA in low power mode, or normal mode.
 321 #define PGALP_LOW          ADC_PGA_PGALP_MASK
 322 #define PGALP_NORMAL       0x00
 323
 324 // Gain of PGA.  Selectable from 1 to 64.
 325 #define PGAG_1             0x00
 326 #define PGAG_2             0x01
 327 #define PGAG_4             0x02
 328 #define PGAG_8             0x03
 329 #define PGAG_16            0x04
 330 #define PGAG_32            0x05
 331 #define PGAG_64            0x06
 332
 333 #define ADC_SIG_PORTA   (0x01 << 5)
 334 #define ADC_SIG_PORTB   (0x02 << 5)
 335 #define ADC_SIG_PORTC   (0x03 << 5)
 336 #define ADC_SIG_PORTD   (0x04 << 5)
 337 #define ADC_SIG_PORTE   (0x05 << 5)
 338
 339 #if 0
 340 #define PDB_CH_EN(adc_num)\
 341         * (uint_8 *) (&PDB0_BASE_PTR->CH[adc_num].C1)
 342 #else
 343 #define PIT_MCR_MDIS      (1<<1)
 344 #define PIT_MCR_FRZ       (1<<0)
 345
 346 #define PIT_TCTRL_TIE     (1<<1)
 347 #define PIT_TCTRL_TEN     (1<<0)
 348
 349 #define PIT_TFLG_TIF      (1<<0)
 350 #endif
 351
 352 #endif /* _KINETS_K60DAC_H_ */