source/soc-codec/Kinets/kinets-k60dac.h

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  * <liu090@sina.com>
   6  */
   7
   8 #ifndef _KINETS_K60DAC_H_
   9 #define _KINETS_K60DAC_H_
  10
  11 /* soc relation head file */
  12 //#include "dma/edma.h"
  13
  14 struct soc_dma_data {
  15         int priority;
  16         unsigned short fifo_aligned_bits;       /* fifo aligned bits in bit */
  17         unsigned short fifo_align_type;
  18         DAC_MemMapPtr dac0_base;
  19         DAC_MemMapPtr dac1_base;
  20 };
  21
  22 typedef struct{
  23     uint32_t SADDR;                                  /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
  24     uint16_t SOFF;                                   /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
  25     uint16_t ATTR;                                   /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
  26     union {                                          /* offset: 0x1008, array step: 0x20 */
  27       uint32_t NBYTES_MLNO;                            /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
  28       uint32_t NBYTES_MLOFFNO;                         /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
  29       uint32_t NBYTES_MLOFFYES;                        /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
  30     };
  31     uint32_t SLAST;                                  /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
  32     uint32_t DADDR;                                  /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
  33     uint16_t DOFF;                                   /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
  34     union {                                          /* offset: 0x1016, array step: 0x20 */
  35       uint16_t CITER_ELINKYES;                         /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
  36       uint16_t CITER_ELINKNO;                          /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
  37     };
  38     uint32_t DLAST_SGA;                              /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
  39     uint16_t CSR;                                    /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
  40     union {                                          /* offset: 0x101E, array step: 0x20 */
  41       uint16_t BITER_ELINKNO;                          /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
  42       uint16_t BITER_ELINKYES;                         /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
  43     };
  44 } DMA_TCD_t, *DMA_TCD_p;
  45
  46 #define MAX_TCD_LISTS                            4   /* must match the number of periods  ! */
  47 #define FIFO_ALIGNMENT_TYPE_RIGHT       0x00
  48 #define FIFO_ALIGNMENT_TYPE_LEFT        0x01
  49
  50 #define FIFO_BITS_ALIGNED               16
  51 #define FIFO_BITS_ENDTYPES              FIFO_ALIGNMENT_TYPE_LEFT
  52
  53 /* Enable global DACx Interrup bit*/
  54 #define VECTOR_DAC0_INT_MASK    2
  55 #define VECTOR_DAC1_INT_MASK    4
  56
  57 /* DAXx registers reset values*/
  58 #define DACx_DAT_RESET                  0
  59 #define DACx_SR_RESET                   2
  60 #define DACx_C0_RESET                   0
  61 #define DACx_C1_RESET                   0
  62 #define DACx_C2_RESET                   15 //0x0f
  63
  64 /* DACx_C0 bits definition*/
  65
  66 #define DAC_DISABLE                             0x00
  67 #define DAC_ENABLE                              DAC_C0_DACEN_MASK
  68
  69 #define DAC_SEL_VREFO                   0x00
  70 #define DAC_SEL_VDDA                    DAC_C0_DACRFS_MASK
  71
  72 #define DAC_SEL_PDB_HW_TRIG     0x00
  73 #define DAC_SEL_SW_TRIG         DAC_C0_DACTRGSEL_MASK
  74
  75 #define DAC_SW_TRIG_STOP                0x00
  76 #define DAC_SW_TRIG_NEXT                DAC_C0_DACSWTRG_MASK
  77
  78 #define DAC_HP_MODE                     0x00
  79 #define DAC_LP_MODE                     DAC_C0_LPEN_MASK
  80
  81 #define DAC_BFWM_INT_DISABLE    0x00
  82 #define DAC_BFWM_INT_ENABLE     DAC_C0_DACBWIEN_MASK
  83
  84 #define DAC_BFT_PTR_INT_DISABLE 0x00
  85 #define DAC_BFT_PTR_INT_ENABLE          DAC_C0_DACBTIEN_MASK
  86
  87 #define DAC_BFB_PTR_INT_DISABLE 0x00
  88 #define DAC_BFB_PTR_INT_ENABLE  DAC_C0_DACBBIEN_MASK
  89
  90 /* DACx_C1 bits definition*/
  91 #define DAC_DMA_DISABLE         0x00
  92 #define DAC_DMA_ENABLE                  DAC_C1_DMAEN_MASK
  93
  94 #define DAC_BFWM_1WORD          DAC_C1_DACBFWM(0)
  95 #define DAC_BFWM_2WORDS         DAC_C1_DACBFWM(1)
  96 #define DAC_BFWM_3WORDS         DAC_C1_DACBFWM(2)
  97 #define DAC_BFWM_4WORDS         DAC_C1_DACBFWM(3)
  98
  99 #define DAC_BF_NORMAL_MODE      DAC_C1_DACBFMD(0)
 100 #define DAC_BF_SWING_MODE               DAC_C1_DACBFMD(1)
 101 #define DAC_BF_ONE_TIME_MODE    DAC_C1_DACBFMD(2)
 102
 103 #define DAC_BF_DISABLE                  0x00
 104 #define DAC_BF_ENABLE                   DAC_C1_DACBFEN_MASK
 105
 106 /* DACx_C2 bits definition*/
 107 #define DAC_SET_PTR_AT_BF(x)    DAC_C2_DACBFRP(x)
 108 #define DAC_SET_PTR_UP_LIMIT(x) DAC_C2_DACBFUP(x)
 109
 110
 111 #define Watermark_One_Word              0
 112 #define Watermark_Two_Words     1
 113 #define Watermark_Three_Words   2
 114 #define Watermark_Four_Words    3
 115
 116 #define Clear_DACBFWMF                  0x03
 117 #define Clear_DACBFRPTF                 0x05
 118 #define Clear_DACBFRPBF                 0x06
 119
 120 #define PDB_DACINTC0_TOE_MASK   0x1u
 121 ///////////////////////////////////////////
 122 #define DEFAULT_AUDIO_SAMPLERATE        44100
 123
 124 #define  DAM16WORD_TWICE
 125
 126 /* simulate */
 127 #define DMA_CHANNEL_DAC0                        0
 128 #define DMA_CHANNEL_DAC1                        1
 129
 130 #ifdef DAM16WORD_TWICE
 131 #define DAC_BUFFER_SIZE                 (0x10)
 132 #else
 133 #define DAC_BUFFER_SIZE                 (0x10 * 2)
 134 #endif
 135 #define AUDIO_DMA_BUFFER_SIZE           0x200
 136 #define DMA_CH0_ISR_NUM                 0
 137 #define DMA_ERROR_ISR_NUM                       16
 138 #define DMA_REQUEST_DAC0                        45
 139 #define DMA_REQUEST_DAC1                        46
 140 #define SAMPLE_RATE_44100HZ             44100
 141 #define SAMPLE_RATE_1KHZ                        1000
 142
 143 #define DAC_TWO_CHANNEL
 144
 145
 146 #endif /* _KINETS_K60DAC_H_ */