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cpufreq/amd-pstate: Fix per-policy boost flag incorrect when fail
[pf-kernel.git] / drivers / crypto / amcc / crypto4xx_core.c
blobec3ccfa60445fcb9dbbe3f0de60bec4ab35f9574
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AMCC SoC PPC4xx Crypto Driver
4 *
5 * Copyright (c) 2008 Applied Micro Circuits Corporation.
6 * All rights reserved. James Hsiao <jhsiao@amcc.com>
7 *
8 * This file implements AMCC crypto offload Linux device driver for use with
9 * Linux CryptoAPI.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/spinlock_types.h>
15 #include <linux/random.h>
16 #include <linux/scatterlist.h>
17 #include <linux/crypto.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/platform_device.h>
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_platform.h>
25 #include <linux/slab.h>
26 #include <asm/dcr.h>
27 #include <asm/dcr-regs.h>
28 #include <asm/cacheflush.h>
29 #include <crypto/aead.h>
30 #include <crypto/aes.h>
31 #include <crypto/ctr.h>
32 #include <crypto/gcm.h>
33 #include <crypto/sha1.h>
34 #include <crypto/rng.h>
35 #include <crypto/scatterwalk.h>
36 #include <crypto/skcipher.h>
37 #include <crypto/internal/aead.h>
38 #include <crypto/internal/rng.h>
39 #include <crypto/internal/skcipher.h>
40 #include "crypto4xx_reg_def.h"
41 #include "crypto4xx_core.h"
42 #include "crypto4xx_sa.h"
43 #include "crypto4xx_trng.h"
44
45 #define PPC4XX_SEC_VERSION_STR "0.5"
46
47 /*
48 * PPC4xx Crypto Engine Initialization Routine
49 */
50 static void crypto4xx_hw_init(struct crypto4xx_device *dev)
51 {
52 union ce_ring_size ring_size;
53 union ce_ring_control ring_ctrl;
54 union ce_part_ring_size part_ring_size;
55 union ce_io_threshold io_threshold;
56 u32 rand_num;
57 union ce_pe_dma_cfg pe_dma_cfg;
58 u32 device_ctrl;
59
60 writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
61 /* setup pe dma, include reset sg, pdr and pe, then release reset */
62 pe_dma_cfg.w = 0;
63 pe_dma_cfg.bf.bo_sgpd_en = 1;
64 pe_dma_cfg.bf.bo_data_en = 0;
65 pe_dma_cfg.bf.bo_sa_en = 1;
66 pe_dma_cfg.bf.bo_pd_en = 1;
67 pe_dma_cfg.bf.dynamic_sa_en = 1;
68 pe_dma_cfg.bf.reset_sg = 1;
69 pe_dma_cfg.bf.reset_pdr = 1;
70 pe_dma_cfg.bf.reset_pe = 1;
71 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
72 /* un reset pe,sg and pdr */
73 pe_dma_cfg.bf.pe_mode = 0;
74 pe_dma_cfg.bf.reset_sg = 0;
75 pe_dma_cfg.bf.reset_pdr = 0;
76 pe_dma_cfg.bf.reset_pe = 0;
77 pe_dma_cfg.bf.bo_td_en = 0;
78 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
79 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE);
80 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE);
81 writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL);
82 get_random_bytes(&rand_num, sizeof(rand_num));
83 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L);
84 get_random_bytes(&rand_num, sizeof(rand_num));
85 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H);
86 ring_size.w = 0;
87 ring_size.bf.ring_offset = PPC4XX_PD_SIZE;
88 ring_size.bf.ring_size = PPC4XX_NUM_PD;
89 writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
90 ring_ctrl.w = 0;
91 writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
92 device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
93 device_ctrl |= PPC4XX_DC_3DES_EN;
94 writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
95 writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
96 writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
97 part_ring_size.w = 0;
98 part_ring_size.bf.sdr_size = PPC4XX_SDR_SIZE;
99 part_ring_size.bf.gdr_size = PPC4XX_GDR_SIZE;
100 writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE);
101 writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG);
102 io_threshold.w = 0;
103 io_threshold.bf.output_threshold = PPC4XX_OUTPUT_THRESHOLD;
104 io_threshold.bf.input_threshold = PPC4XX_INPUT_THRESHOLD;
105 writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD);
106 writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR);
107 writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR);
108 writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR);
109 writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR);
110 writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR);
111 writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR);
112 writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR);
113 /* un reset pe,sg and pdr */
114 pe_dma_cfg.bf.pe_mode = 1;
115 pe_dma_cfg.bf.reset_sg = 0;
116 pe_dma_cfg.bf.reset_pdr = 0;
117 pe_dma_cfg.bf.reset_pe = 0;
118 pe_dma_cfg.bf.bo_td_en = 0;
119 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
120 /*clear all pending interrupt*/
121 writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR);
122 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
123 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
124 writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG);
125 if (dev->is_revb) {
126 writel(PPC4XX_INT_TIMEOUT_CNT_REVB << 10,
127 dev->ce_base + CRYPTO4XX_INT_TIMEOUT_CNT);
128 writel(PPC4XX_PD_DONE_INT | PPC4XX_TMO_ERR_INT,
129 dev->ce_base + CRYPTO4XX_INT_EN);
130 } else {
131 writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
132 }
133 }
134
135 int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size)
136 {
137 ctx->sa_in = kcalloc(size, 4, GFP_ATOMIC);
138 if (ctx->sa_in == NULL)
139 return -ENOMEM;
140
141 ctx->sa_out = kcalloc(size, 4, GFP_ATOMIC);
142 if (ctx->sa_out == NULL) {
143 kfree(ctx->sa_in);
144 ctx->sa_in = NULL;
145 return -ENOMEM;
146 }
147
148 ctx->sa_len = size;
149
150 return 0;
151 }
152
153 void crypto4xx_free_sa(struct crypto4xx_ctx *ctx)
154 {
155 kfree(ctx->sa_in);
156 ctx->sa_in = NULL;
157 kfree(ctx->sa_out);
158 ctx->sa_out = NULL;
159 ctx->sa_len = 0;
160 }
161
162 /*
163 * alloc memory for the gather ring
164 * no need to alloc buf for the ring
165 * gdr_tail, gdr_head and gdr_count are initialized by this function
166 */
167 static u32 crypto4xx_build_pdr(struct crypto4xx_device *dev)
168 {
169 int i;
170 dev->pdr = dma_alloc_coherent(dev->core_dev->device,
171 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
172 &dev->pdr_pa, GFP_KERNEL);
173 if (!dev->pdr)
174 return -ENOMEM;
175
176 dev->pdr_uinfo = kcalloc(PPC4XX_NUM_PD, sizeof(struct pd_uinfo),
177 GFP_KERNEL);
178 if (!dev->pdr_uinfo) {
179 dma_free_coherent(dev->core_dev->device,
180 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
181 dev->pdr,
182 dev->pdr_pa);
183 return -ENOMEM;
184 }
185 dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device,
186 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD,
187 &dev->shadow_sa_pool_pa,
188 GFP_KERNEL);
189 if (!dev->shadow_sa_pool)
190 return -ENOMEM;
191
192 dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device,
193 sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
194 &dev->shadow_sr_pool_pa, GFP_KERNEL);
195 if (!dev->shadow_sr_pool)
196 return -ENOMEM;
197 for (i = 0; i < PPC4XX_NUM_PD; i++) {
198 struct ce_pd *pd = &dev->pdr[i];
199 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[i];
200
201 pd->sa = dev->shadow_sa_pool_pa +
202 sizeof(union shadow_sa_buf) * i;
203
204 /* alloc 256 bytes which is enough for any kind of dynamic sa */
205 pd_uinfo->sa_va = &dev->shadow_sa_pool[i].sa;
206
207 /* alloc state record */
208 pd_uinfo->sr_va = &dev->shadow_sr_pool[i];
209 pd_uinfo->sr_pa = dev->shadow_sr_pool_pa +
210 sizeof(struct sa_state_record) * i;
211 }
212
213 return 0;
214 }
215
216 static void crypto4xx_destroy_pdr(struct crypto4xx_device *dev)
217 {
218 if (dev->pdr)
219 dma_free_coherent(dev->core_dev->device,
220 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
221 dev->pdr, dev->pdr_pa);
222
223 if (dev->shadow_sa_pool)
224 dma_free_coherent(dev->core_dev->device,
225 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD,
226 dev->shadow_sa_pool, dev->shadow_sa_pool_pa);
227
228 if (dev->shadow_sr_pool)
229 dma_free_coherent(dev->core_dev->device,
230 sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
231 dev->shadow_sr_pool, dev->shadow_sr_pool_pa);
232
233 kfree(dev->pdr_uinfo);
234 }
235
236 static u32 crypto4xx_get_pd_from_pdr_nolock(struct crypto4xx_device *dev)
237 {
238 u32 retval;
239 u32 tmp;
240
241 retval = dev->pdr_head;
242 tmp = (dev->pdr_head + 1) % PPC4XX_NUM_PD;
243
244 if (tmp == dev->pdr_tail)
245 return ERING_WAS_FULL;
246
247 dev->pdr_head = tmp;
248
249 return retval;
250 }
251
252 static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx)
253 {
254 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx];
255 u32 tail;
256 unsigned long flags;
257
258 spin_lock_irqsave(&dev->core_dev->lock, flags);
259 pd_uinfo->state = PD_ENTRY_FREE;
260
261 if (dev->pdr_tail != PPC4XX_LAST_PD)
262 dev->pdr_tail++;
263 else
264 dev->pdr_tail = 0;
265 tail = dev->pdr_tail;
266 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
267
268 return tail;
269 }
270
271 /*
272 * alloc memory for the gather ring
273 * no need to alloc buf for the ring
274 * gdr_tail, gdr_head and gdr_count are initialized by this function
275 */
276 static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev)
277 {
278 dev->gdr = dma_alloc_coherent(dev->core_dev->device,
279 sizeof(struct ce_gd) * PPC4XX_NUM_GD,
280 &dev->gdr_pa, GFP_KERNEL);
281 if (!dev->gdr)
282 return -ENOMEM;
283
284 return 0;
285 }
286
287 static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev)
288 {
289 if (dev->gdr)
290 dma_free_coherent(dev->core_dev->device,
291 sizeof(struct ce_gd) * PPC4XX_NUM_GD,
292 dev->gdr, dev->gdr_pa);
293 }
294
295 /*
296 * when this function is called.
297 * preemption or interrupt must be disabled
298 */
299 static u32 crypto4xx_get_n_gd(struct crypto4xx_device *dev, int n)
300 {
301 u32 retval;
302 u32 tmp;
303
304 if (n >= PPC4XX_NUM_GD)
305 return ERING_WAS_FULL;
306
307 retval = dev->gdr_head;
308 tmp = (dev->gdr_head + n) % PPC4XX_NUM_GD;
309 if (dev->gdr_head > dev->gdr_tail) {
310 if (tmp < dev->gdr_head && tmp >= dev->gdr_tail)
311 return ERING_WAS_FULL;
312 } else if (dev->gdr_head < dev->gdr_tail) {
313 if (tmp < dev->gdr_head || tmp >= dev->gdr_tail)
314 return ERING_WAS_FULL;
315 }
316 dev->gdr_head = tmp;
317
318 return retval;
319 }
320
321 static u32 crypto4xx_put_gd_to_gdr(struct crypto4xx_device *dev)
322 {
323 unsigned long flags;
324
325 spin_lock_irqsave(&dev->core_dev->lock, flags);
326 if (dev->gdr_tail == dev->gdr_head) {
327 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
328 return 0;
329 }
330
331 if (dev->gdr_tail != PPC4XX_LAST_GD)
332 dev->gdr_tail++;
333 else
334 dev->gdr_tail = 0;
335
336 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
337
338 return 0;
339 }
340
341 static inline struct ce_gd *crypto4xx_get_gdp(struct crypto4xx_device *dev,
342 dma_addr_t *gd_dma, u32 idx)
343 {
344 *gd_dma = dev->gdr_pa + sizeof(struct ce_gd) * idx;
345
346 return &dev->gdr[idx];
347 }
348
349 /*
350 * alloc memory for the scatter ring
351 * need to alloc buf for the ring
352 * sdr_tail, sdr_head and sdr_count are initialized by this function
353 */
354 static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev)
355 {
356 int i;
357
358 dev->scatter_buffer_va =
359 dma_alloc_coherent(dev->core_dev->device,
360 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD,
361 &dev->scatter_buffer_pa, GFP_KERNEL);
362 if (!dev->scatter_buffer_va)
363 return -ENOMEM;
364
365 /* alloc memory for scatter descriptor ring */
366 dev->sdr = dma_alloc_coherent(dev->core_dev->device,
367 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
368 &dev->sdr_pa, GFP_KERNEL);
369 if (!dev->sdr)
370 return -ENOMEM;
371
372 for (i = 0; i < PPC4XX_NUM_SD; i++) {
373 dev->sdr[i].ptr = dev->scatter_buffer_pa +
374 PPC4XX_SD_BUFFER_SIZE * i;
375 }
376
377 return 0;
378 }
379
380 static void crypto4xx_destroy_sdr(struct crypto4xx_device *dev)
381 {
382 if (dev->sdr)
383 dma_free_coherent(dev->core_dev->device,
384 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
385 dev->sdr, dev->sdr_pa);
386
387 if (dev->scatter_buffer_va)
388 dma_free_coherent(dev->core_dev->device,
389 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD,
390 dev->scatter_buffer_va,
391 dev->scatter_buffer_pa);
392 }
393
394 /*
395 * when this function is called.
396 * preemption or interrupt must be disabled
397 */
398 static u32 crypto4xx_get_n_sd(struct crypto4xx_device *dev, int n)
399 {
400 u32 retval;
401 u32 tmp;
402
403 if (n >= PPC4XX_NUM_SD)
404 return ERING_WAS_FULL;
405
406 retval = dev->sdr_head;
407 tmp = (dev->sdr_head + n) % PPC4XX_NUM_SD;
408 if (dev->sdr_head > dev->gdr_tail) {
409 if (tmp < dev->sdr_head && tmp >= dev->sdr_tail)
410 return ERING_WAS_FULL;
411 } else if (dev->sdr_head < dev->sdr_tail) {
412 if (tmp < dev->sdr_head || tmp >= dev->sdr_tail)
413 return ERING_WAS_FULL;
414 } /* the head = tail, or empty case is already take cared */
415 dev->sdr_head = tmp;
416
417 return retval;
418 }
419
420 static u32 crypto4xx_put_sd_to_sdr(struct crypto4xx_device *dev)
421 {
422 unsigned long flags;
423
424 spin_lock_irqsave(&dev->core_dev->lock, flags);
425 if (dev->sdr_tail == dev->sdr_head) {
426 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
427 return 0;
428 }
429 if (dev->sdr_tail != PPC4XX_LAST_SD)
430 dev->sdr_tail++;
431 else
432 dev->sdr_tail = 0;
433 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
434
435 return 0;
436 }
437
438 static inline struct ce_sd *crypto4xx_get_sdp(struct crypto4xx_device *dev,
439 dma_addr_t *sd_dma, u32 idx)
440 {
441 *sd_dma = dev->sdr_pa + sizeof(struct ce_sd) * idx;
442
443 return &dev->sdr[idx];
444 }
445
446 static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev,
447 struct ce_pd *pd,
448 struct pd_uinfo *pd_uinfo,
449 u32 nbytes,
450 struct scatterlist *dst)
451 {
452 unsigned int first_sd = pd_uinfo->first_sd;
453 unsigned int last_sd;
454 unsigned int overflow = 0;
455 unsigned int to_copy;
456 unsigned int dst_start = 0;
457
458 /*
459 * Because the scatter buffers are all neatly organized in one
460 * big continuous ringbuffer; scatterwalk_map_and_copy() can
461 * be instructed to copy a range of buffers in one go.
462 */
463
464 last_sd = (first_sd + pd_uinfo->num_sd);
465 if (last_sd > PPC4XX_LAST_SD) {
466 last_sd = PPC4XX_LAST_SD;
467 overflow = last_sd % PPC4XX_NUM_SD;
468 }
469
470 while (nbytes) {
471 void *buf = dev->scatter_buffer_va +
472 first_sd * PPC4XX_SD_BUFFER_SIZE;
473
474 to_copy = min(nbytes, PPC4XX_SD_BUFFER_SIZE *
475 (1 + last_sd - first_sd));
476 scatterwalk_map_and_copy(buf, dst, dst_start, to_copy, 1);
477 nbytes -= to_copy;
478
479 if (overflow) {
480 first_sd = 0;
481 last_sd = overflow;
482 dst_start += to_copy;
483 overflow = 0;
484 }
485 }
486 }
487
488 static void crypto4xx_copy_digest_to_dst(void *dst,
489 struct pd_uinfo *pd_uinfo,
490 struct crypto4xx_ctx *ctx)
491 {
492 struct dynamic_sa_ctl *sa = (struct dynamic_sa_ctl *) ctx->sa_in;
493
494 if (sa->sa_command_0.bf.hash_alg == SA_HASH_ALG_SHA1) {
495 memcpy(dst, pd_uinfo->sr_va->save_digest,
496 SA_HASH_ALG_SHA1_DIGEST_SIZE);
497 }
498 }
499
500 static void crypto4xx_ret_sg_desc(struct crypto4xx_device *dev,
501 struct pd_uinfo *pd_uinfo)
502 {
503 int i;
504 if (pd_uinfo->num_gd) {
505 for (i = 0; i < pd_uinfo->num_gd; i++)
506 crypto4xx_put_gd_to_gdr(dev);
507 pd_uinfo->first_gd = 0xffffffff;
508 pd_uinfo->num_gd = 0;
509 }
510 if (pd_uinfo->num_sd) {
511 for (i = 0; i < pd_uinfo->num_sd; i++)
512 crypto4xx_put_sd_to_sdr(dev);
513
514 pd_uinfo->first_sd = 0xffffffff;
515 pd_uinfo->num_sd = 0;
516 }
517 }
518
519 static void crypto4xx_cipher_done(struct crypto4xx_device *dev,
520 struct pd_uinfo *pd_uinfo,
521 struct ce_pd *pd)
522 {
523 struct skcipher_request *req;
524 struct scatterlist *dst;
525
526 req = skcipher_request_cast(pd_uinfo->async_req);
527
528 if (pd_uinfo->sa_va->sa_command_0.bf.scatter) {
529 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
530 req->cryptlen, req->dst);
531 } else {
532 dst = pd_uinfo->dest_va;
533 dma_unmap_page(dev->core_dev->device, pd->dest, dst->length,
534 DMA_FROM_DEVICE);
535 }
536
537 if (pd_uinfo->sa_va->sa_command_0.bf.save_iv == SA_SAVE_IV) {
538 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
539
540 crypto4xx_memcpy_from_le32((u32 *)req->iv,
541 pd_uinfo->sr_va->save_iv,
542 crypto_skcipher_ivsize(skcipher));
543 }
544
545 crypto4xx_ret_sg_desc(dev, pd_uinfo);
546
547 if (pd_uinfo->state & PD_ENTRY_BUSY)
548 skcipher_request_complete(req, -EINPROGRESS);
549 skcipher_request_complete(req, 0);
550 }
551
552 static void crypto4xx_ahash_done(struct crypto4xx_device *dev,
553 struct pd_uinfo *pd_uinfo)
554 {
555 struct crypto4xx_ctx *ctx;
556 struct ahash_request *ahash_req;
557
558 ahash_req = ahash_request_cast(pd_uinfo->async_req);
559 ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(ahash_req));
560
561 crypto4xx_copy_digest_to_dst(ahash_req->result, pd_uinfo, ctx);
562 crypto4xx_ret_sg_desc(dev, pd_uinfo);
563
564 if (pd_uinfo->state & PD_ENTRY_BUSY)
565 ahash_request_complete(ahash_req, -EINPROGRESS);
566 ahash_request_complete(ahash_req, 0);
567 }
568
569 static void crypto4xx_aead_done(struct crypto4xx_device *dev,
570 struct pd_uinfo *pd_uinfo,
571 struct ce_pd *pd)
572 {
573 struct aead_request *aead_req = container_of(pd_uinfo->async_req,
574 struct aead_request, base);
575 struct scatterlist *dst = pd_uinfo->dest_va;
576 size_t cp_len = crypto_aead_authsize(
577 crypto_aead_reqtfm(aead_req));
578 u32 icv[AES_BLOCK_SIZE];
579 int err = 0;
580
581 if (pd_uinfo->sa_va->sa_command_0.bf.scatter) {
582 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
583 pd->pd_ctl_len.bf.pkt_len,
584 dst);
585 } else {
586 dma_unmap_page(dev->core_dev->device, pd->dest, dst->length,
587 DMA_FROM_DEVICE);
588 }
589
590 if (pd_uinfo->sa_va->sa_command_0.bf.dir == DIR_OUTBOUND) {
591 /* append icv at the end */
592 crypto4xx_memcpy_from_le32(icv, pd_uinfo->sr_va->save_digest,
593 sizeof(icv));
594
595 scatterwalk_map_and_copy(icv, dst, aead_req->cryptlen,
596 cp_len, 1);
597 } else {
598 /* check icv at the end */
599 scatterwalk_map_and_copy(icv, aead_req->src,
600 aead_req->assoclen + aead_req->cryptlen -
601 cp_len, cp_len, 0);
602
603 crypto4xx_memcpy_from_le32(icv, icv, sizeof(icv));
604
605 if (crypto_memneq(icv, pd_uinfo->sr_va->save_digest, cp_len))
606 err = -EBADMSG;
607 }
608
609 crypto4xx_ret_sg_desc(dev, pd_uinfo);
610
611 if (pd->pd_ctl.bf.status & 0xff) {
612 if (!__ratelimit(&dev->aead_ratelimit)) {
613 if (pd->pd_ctl.bf.status & 2)
614 pr_err("pad fail error\n");
615 if (pd->pd_ctl.bf.status & 4)
616 pr_err("seqnum fail\n");
617 if (pd->pd_ctl.bf.status & 8)
618 pr_err("error _notify\n");
619 pr_err("aead return err status = 0x%02x\n",
620 pd->pd_ctl.bf.status & 0xff);
621 pr_err("pd pad_ctl = 0x%08x\n",
622 pd->pd_ctl.bf.pd_pad_ctl);
623 }
624 err = -EINVAL;
625 }
626
627 if (pd_uinfo->state & PD_ENTRY_BUSY)
628 aead_request_complete(aead_req, -EINPROGRESS);
629
630 aead_request_complete(aead_req, err);
631 }
632
633 static void crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
634 {
635 struct ce_pd *pd = &dev->pdr[idx];
636 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx];
637
638 switch (crypto_tfm_alg_type(pd_uinfo->async_req->tfm)) {
639 case CRYPTO_ALG_TYPE_SKCIPHER:
640 crypto4xx_cipher_done(dev, pd_uinfo, pd);
641 break;
642 case CRYPTO_ALG_TYPE_AEAD:
643 crypto4xx_aead_done(dev, pd_uinfo, pd);
644 break;
645 case CRYPTO_ALG_TYPE_AHASH:
646 crypto4xx_ahash_done(dev, pd_uinfo);
647 break;
648 }
649 }
650
651 static void crypto4xx_stop_all(struct crypto4xx_core_device *core_dev)
652 {
653 crypto4xx_destroy_pdr(core_dev->dev);
654 crypto4xx_destroy_gdr(core_dev->dev);
655 crypto4xx_destroy_sdr(core_dev->dev);
656 }
657
658 static u32 get_next_gd(u32 current)
659 {
660 if (current != PPC4XX_LAST_GD)
661 return current + 1;
662 else
663 return 0;
664 }
665
666 static u32 get_next_sd(u32 current)
667 {
668 if (current != PPC4XX_LAST_SD)
669 return current + 1;
670 else
671 return 0;
672 }
673
674 int crypto4xx_build_pd(struct crypto_async_request *req,
675 struct crypto4xx_ctx *ctx,
676 struct scatterlist *src,
677 struct scatterlist *dst,
678 const unsigned int datalen,
679 const __le32 *iv, const u32 iv_len,
680 const struct dynamic_sa_ctl *req_sa,
681 const unsigned int sa_len,
682 const unsigned int assoclen,
683 struct scatterlist *_dst)
684 {
685 struct crypto4xx_device *dev = ctx->dev;
686 struct dynamic_sa_ctl *sa;
687 struct ce_gd *gd;
688 struct ce_pd *pd;
689 u32 num_gd, num_sd;
690 u32 fst_gd = 0xffffffff;
691 u32 fst_sd = 0xffffffff;
692 u32 pd_entry;
693 unsigned long flags;
694 struct pd_uinfo *pd_uinfo;
695 unsigned int nbytes = datalen;
696 size_t offset_to_sr_ptr;
697 u32 gd_idx = 0;
698 int tmp;
699 bool is_busy, force_sd;
700
701 /*
702 * There's a very subtile/disguised "bug" in the hardware that
703 * gets indirectly mentioned in 18.1.3.5 Encryption/Decryption
704 * of the hardware spec:
705 * *drum roll* the AES/(T)DES OFB and CFB modes are listed as
706 * operation modes for >>> "Block ciphers" <<<.
707 *
708 * To workaround this issue and stop the hardware from causing
709 * "overran dst buffer" on crypttexts that are not a multiple
710 * of 16 (AES_BLOCK_SIZE), we force the driver to use the
711 * scatter buffers.
712 */
713 force_sd = (req_sa->sa_command_1.bf.crypto_mode9_8 == CRYPTO_MODE_CFB
714 || req_sa->sa_command_1.bf.crypto_mode9_8 == CRYPTO_MODE_OFB)
715 && (datalen % AES_BLOCK_SIZE);
716
717 /* figure how many gd are needed */
718 tmp = sg_nents_for_len(src, assoclen + datalen);
719 if (tmp < 0) {
720 dev_err(dev->core_dev->device, "Invalid number of src SG.\n");
721 return tmp;
722 }
723 if (tmp == 1)
724 tmp = 0;
725 num_gd = tmp;
726
727 if (assoclen) {
728 nbytes += assoclen;
729 dst = scatterwalk_ffwd(_dst, dst, assoclen);
730 }
731
732 /* figure how many sd are needed */
733 if (sg_is_last(dst) && force_sd == false) {
734 num_sd = 0;
735 } else {
736 if (datalen > PPC4XX_SD_BUFFER_SIZE) {
737 num_sd = datalen / PPC4XX_SD_BUFFER_SIZE;
738 if (datalen % PPC4XX_SD_BUFFER_SIZE)
739 num_sd++;
740 } else {
741 num_sd = 1;
742 }
743 }
744
745 /*
746 * The follow section of code needs to be protected
747 * The gather ring and scatter ring needs to be consecutive
748 * In case of run out of any kind of descriptor, the descriptor
749 * already got must be return the original place.
750 */
751 spin_lock_irqsave(&dev->core_dev->lock, flags);
752 /*
753 * Let the caller know to slow down, once more than 13/16ths = 81%
754 * of the available data contexts are being used simultaneously.
755 *
756 * With PPC4XX_NUM_PD = 256, this will leave a "backlog queue" for
757 * 31 more contexts. Before new requests have to be rejected.
758 */
759 if (req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG) {
760 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >=
761 ((PPC4XX_NUM_PD * 13) / 16);
762 } else {
763 /*
764 * To fix contention issues between ipsec (no blacklog) and
765 * dm-crypto (backlog) reserve 32 entries for "no backlog"
766 * data contexts.
767 */
768 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >=
769 ((PPC4XX_NUM_PD * 15) / 16);
770
771 if (is_busy) {
772 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
773 return -EBUSY;
774 }
775 }
776
777 if (num_gd) {
778 fst_gd = crypto4xx_get_n_gd(dev, num_gd);
779 if (fst_gd == ERING_WAS_FULL) {
780 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
781 return -EAGAIN;
782 }
783 }
784 if (num_sd) {
785 fst_sd = crypto4xx_get_n_sd(dev, num_sd);
786 if (fst_sd == ERING_WAS_FULL) {
787 if (num_gd)
788 dev->gdr_head = fst_gd;
789 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
790 return -EAGAIN;
791 }
792 }
793 pd_entry = crypto4xx_get_pd_from_pdr_nolock(dev);
794 if (pd_entry == ERING_WAS_FULL) {
795 if (num_gd)
796 dev->gdr_head = fst_gd;
797 if (num_sd)
798 dev->sdr_head = fst_sd;
799 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
800 return -EAGAIN;
801 }
802 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
803
804 pd = &dev->pdr[pd_entry];
805 pd->sa_len = sa_len;
806
807 pd_uinfo = &dev->pdr_uinfo[pd_entry];
808 pd_uinfo->num_gd = num_gd;
809 pd_uinfo->num_sd = num_sd;
810 pd_uinfo->dest_va = dst;
811 pd_uinfo->async_req = req;
812
813 if (iv_len)
814 memcpy(pd_uinfo->sr_va->save_iv, iv, iv_len);
815
816 sa = pd_uinfo->sa_va;
817 memcpy(sa, req_sa, sa_len * 4);
818
819 sa->sa_command_1.bf.hash_crypto_offset = (assoclen >> 2);
820 offset_to_sr_ptr = get_dynamic_sa_offset_state_ptr_field(sa);
821 *(u32 *)((unsigned long)sa + offset_to_sr_ptr) = pd_uinfo->sr_pa;
822
823 if (num_gd) {
824 dma_addr_t gd_dma;
825 struct scatterlist *sg;
826
827 /* get first gd we are going to use */
828 gd_idx = fst_gd;
829 pd_uinfo->first_gd = fst_gd;
830 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
831 pd->src = gd_dma;
832 /* enable gather */
833 sa->sa_command_0.bf.gather = 1;
834 /* walk the sg, and setup gather array */
835
836 sg = src;
837 while (nbytes) {
838 size_t len;
839
840 len = min(sg->length, nbytes);
841 gd->ptr = dma_map_page(dev->core_dev->device,
842 sg_page(sg), sg->offset, len, DMA_TO_DEVICE);
843 gd->ctl_len.len = len;
844 gd->ctl_len.done = 0;
845 gd->ctl_len.ready = 1;
846 if (len >= nbytes)
847 break;
848
849 nbytes -= sg->length;
850 gd_idx = get_next_gd(gd_idx);
851 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
852 sg = sg_next(sg);
853 }
854 } else {
855 pd->src = (u32)dma_map_page(dev->core_dev->device, sg_page(src),
856 src->offset, min(nbytes, src->length),
857 DMA_TO_DEVICE);
858 /*
859 * Disable gather in sa command
860 */
861 sa->sa_command_0.bf.gather = 0;
862 /*
863 * Indicate gather array is not used
864 */
865 pd_uinfo->first_gd = 0xffffffff;
866 }
867 if (!num_sd) {
868 /*
869 * we know application give us dst a whole piece of memory
870 * no need to use scatter ring.
871 */
872 pd_uinfo->first_sd = 0xffffffff;
873 sa->sa_command_0.bf.scatter = 0;
874 pd->dest = (u32)dma_map_page(dev->core_dev->device,
875 sg_page(dst), dst->offset,
876 min(datalen, dst->length),
877 DMA_TO_DEVICE);
878 } else {
879 dma_addr_t sd_dma;
880 struct ce_sd *sd = NULL;
881
882 u32 sd_idx = fst_sd;
883 nbytes = datalen;
884 sa->sa_command_0.bf.scatter = 1;
885 pd_uinfo->first_sd = fst_sd;
886 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
887 pd->dest = sd_dma;
888 /* setup scatter descriptor */
889 sd->ctl.done = 0;
890 sd->ctl.rdy = 1;
891 /* sd->ptr should be setup by sd_init routine*/
892 if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
893 nbytes -= PPC4XX_SD_BUFFER_SIZE;
894 else
895 nbytes = 0;
896 while (nbytes) {
897 sd_idx = get_next_sd(sd_idx);
898 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
899 /* setup scatter descriptor */
900 sd->ctl.done = 0;
901 sd->ctl.rdy = 1;
902 if (nbytes >= PPC4XX_SD_BUFFER_SIZE) {
903 nbytes -= PPC4XX_SD_BUFFER_SIZE;
904 } else {
905 /*
906 * SD entry can hold PPC4XX_SD_BUFFER_SIZE,
907 * which is more than nbytes, so done.
908 */
909 nbytes = 0;
910 }
911 }
912 }
913
914 pd->pd_ctl.w = PD_CTL_HOST_READY |
915 ((crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AHASH) ||
916 (crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AEAD) ?
917 PD_CTL_HASH_FINAL : 0);
918 pd->pd_ctl_len.w = 0x00400000 | (assoclen + datalen);
919 pd_uinfo->state = PD_ENTRY_INUSE | (is_busy ? PD_ENTRY_BUSY : 0);
920
921 wmb();
922 /* write any value to push engine to read a pd */
923 writel(0, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
924 writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
925 return is_busy ? -EBUSY : -EINPROGRESS;
926 }
927
928 /*
929 * Algorithm Registration Functions
930 */
931 static void crypto4xx_ctx_init(struct crypto4xx_alg *amcc_alg,
932 struct crypto4xx_ctx *ctx)
933 {
934 ctx->dev = amcc_alg->dev;
935 ctx->sa_in = NULL;
936 ctx->sa_out = NULL;
937 ctx->sa_len = 0;
938 }
939
940 static int crypto4xx_sk_init(struct crypto_skcipher *sk)
941 {
942 struct skcipher_alg *alg = crypto_skcipher_alg(sk);
943 struct crypto4xx_alg *amcc_alg;
944 struct crypto4xx_ctx *ctx = crypto_skcipher_ctx(sk);
945
946 if (alg->base.cra_flags & CRYPTO_ALG_NEED_FALLBACK) {
947 ctx->sw_cipher.cipher =
948 crypto_alloc_sync_skcipher(alg->base.cra_name, 0,
949 CRYPTO_ALG_NEED_FALLBACK);
950 if (IS_ERR(ctx->sw_cipher.cipher))
951 return PTR_ERR(ctx->sw_cipher.cipher);
952 }
953
954 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.cipher);
955 crypto4xx_ctx_init(amcc_alg, ctx);
956 return 0;
957 }
958
959 static void crypto4xx_common_exit(struct crypto4xx_ctx *ctx)
960 {
961 crypto4xx_free_sa(ctx);
962 }
963
964 static void crypto4xx_sk_exit(struct crypto_skcipher *sk)
965 {
966 struct crypto4xx_ctx *ctx = crypto_skcipher_ctx(sk);
967
968 crypto4xx_common_exit(ctx);
969 if (ctx->sw_cipher.cipher)
970 crypto_free_sync_skcipher(ctx->sw_cipher.cipher);
971 }
972
973 static int crypto4xx_aead_init(struct crypto_aead *tfm)
974 {
975 struct aead_alg *alg = crypto_aead_alg(tfm);
976 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm);
977 struct crypto4xx_alg *amcc_alg;
978
979 ctx->sw_cipher.aead = crypto_alloc_aead(alg->base.cra_name, 0,
980 CRYPTO_ALG_NEED_FALLBACK |
981 CRYPTO_ALG_ASYNC);
982 if (IS_ERR(ctx->sw_cipher.aead))
983 return PTR_ERR(ctx->sw_cipher.aead);
984
985 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.aead);
986 crypto4xx_ctx_init(amcc_alg, ctx);
987 crypto_aead_set_reqsize(tfm, max(sizeof(struct aead_request) + 32 +
988 crypto_aead_reqsize(ctx->sw_cipher.aead),
989 sizeof(struct crypto4xx_aead_reqctx)));
990 return 0;
991 }
992
993 static void crypto4xx_aead_exit(struct crypto_aead *tfm)
994 {
995 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm);
996
997 crypto4xx_common_exit(ctx);
998 crypto_free_aead(ctx->sw_cipher.aead);
999 }
1000
1001 static int crypto4xx_register_alg(struct crypto4xx_device *sec_dev,
1002 struct crypto4xx_alg_common *crypto_alg,
1003 int array_size)
1004 {
1005 struct crypto4xx_alg *alg;
1006 int i;
1007 int rc = 0;
1008
1009 for (i = 0; i < array_size; i++) {
1010 alg = kzalloc(sizeof(struct crypto4xx_alg), GFP_KERNEL);
1011 if (!alg)
1012 return -ENOMEM;
1013
1014 alg->alg = crypto_alg[i];
1015 alg->dev = sec_dev;
1016
1017 switch (alg->alg.type) {
1018 case CRYPTO_ALG_TYPE_AEAD:
1019 rc = crypto_register_aead(&alg->alg.u.aead);
1020 break;
1021
1022 case CRYPTO_ALG_TYPE_AHASH:
1023 rc = crypto_register_ahash(&alg->alg.u.hash);
1024 break;
1025
1026 case CRYPTO_ALG_TYPE_RNG:
1027 rc = crypto_register_rng(&alg->alg.u.rng);
1028 break;
1029
1030 default:
1031 rc = crypto_register_skcipher(&alg->alg.u.cipher);
1032 break;
1033 }
1034
1035 if (rc)
1036 kfree(alg);
1037 else
1038 list_add_tail(&alg->entry, &sec_dev->alg_list);
1039 }
1040
1041 return 0;
1042 }
1043
1044 static void crypto4xx_unregister_alg(struct crypto4xx_device *sec_dev)
1045 {
1046 struct crypto4xx_alg *alg, *tmp;
1047
1048 list_for_each_entry_safe(alg, tmp, &sec_dev->alg_list, entry) {
1049 list_del(&alg->entry);
1050 switch (alg->alg.type) {
1051 case CRYPTO_ALG_TYPE_AHASH:
1052 crypto_unregister_ahash(&alg->alg.u.hash);
1053 break;
1054
1055 case CRYPTO_ALG_TYPE_AEAD:
1056 crypto_unregister_aead(&alg->alg.u.aead);
1057 break;
1058
1059 case CRYPTO_ALG_TYPE_RNG:
1060 crypto_unregister_rng(&alg->alg.u.rng);
1061 break;
1062
1063 default:
1064 crypto_unregister_skcipher(&alg->alg.u.cipher);
1065 }
1066 kfree(alg);
1067 }
1068 }
1069
1070 static void crypto4xx_bh_tasklet_cb(unsigned long data)
1071 {
1072 struct device *dev = (struct device *)data;
1073 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1074 struct pd_uinfo *pd_uinfo;
1075 struct ce_pd *pd;
1076 u32 tail = core_dev->dev->pdr_tail;
1077 u32 head = core_dev->dev->pdr_head;
1078
1079 do {
1080 pd_uinfo = &core_dev->dev->pdr_uinfo[tail];
1081 pd = &core_dev->dev->pdr[tail];
1082 if ((pd_uinfo->state & PD_ENTRY_INUSE) &&
1083 ((READ_ONCE(pd->pd_ctl.w) &
1084 (PD_CTL_PE_DONE | PD_CTL_HOST_READY)) ==
1085 PD_CTL_PE_DONE)) {
1086 crypto4xx_pd_done(core_dev->dev, tail);
1087 tail = crypto4xx_put_pd_to_pdr(core_dev->dev, tail);
1088 } else {
1089 /* if tail not done, break */
1090 break;
1091 }
1092 } while (head != tail);
1093 }
1094
1095 /*
1096 * Top Half of isr.
1097 */
1098 static inline irqreturn_t crypto4xx_interrupt_handler(int irq, void *data,
1099 u32 clr_val)
1100 {
1101 struct device *dev = data;
1102 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1103
1104 writel(clr_val, core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
1105 tasklet_schedule(&core_dev->tasklet);
1106
1107 return IRQ_HANDLED;
1108 }
1109
1110 static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data)
1111 {
1112 return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR);
1113 }
1114
1115 static irqreturn_t crypto4xx_ce_interrupt_handler_revb(int irq, void *data)
1116 {
1117 return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR |
1118 PPC4XX_TMO_ERR_INT);
1119 }
1120
1121 static int ppc4xx_prng_data_read(struct crypto4xx_device *dev,
1122 u8 *data, unsigned int max)
1123 {
1124 unsigned int i, curr = 0;
1125 u32 val[2];
1126
1127 do {
1128 /* trigger PRN generation */
1129 writel(PPC4XX_PRNG_CTRL_AUTO_EN,
1130 dev->ce_base + CRYPTO4XX_PRNG_CTRL);
1131
1132 for (i = 0; i < 1024; i++) {
1133 /* usually 19 iterations are enough */
1134 if ((readl(dev->ce_base + CRYPTO4XX_PRNG_STAT) &
1135 CRYPTO4XX_PRNG_STAT_BUSY))
1136 continue;
1137
1138 val[0] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_0);
1139 val[1] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_1);
1140 break;
1141 }
1142 if (i == 1024)
1143 return -ETIMEDOUT;
1144
1145 if ((max - curr) >= 8) {
1146 memcpy(data, &val, 8);
1147 data += 8;
1148 curr += 8;
1149 } else {
1150 /* copy only remaining bytes */
1151 memcpy(data, &val, max - curr);
1152 break;
1153 }
1154 } while (curr < max);
1155
1156 return curr;
1157 }
1158
1159 static int crypto4xx_prng_generate(struct crypto_rng *tfm,
1160 const u8 *src, unsigned int slen,
1161 u8 *dstn, unsigned int dlen)
1162 {
1163 struct rng_alg *alg = crypto_rng_alg(tfm);
1164 struct crypto4xx_alg *amcc_alg;
1165 struct crypto4xx_device *dev;
1166 int ret;
1167
1168 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.rng);
1169 dev = amcc_alg->dev;
1170
1171 mutex_lock(&dev->core_dev->rng_lock);
1172 ret = ppc4xx_prng_data_read(dev, dstn, dlen);
1173 mutex_unlock(&dev->core_dev->rng_lock);
1174 return ret;
1175 }
1176
1177
1178 static int crypto4xx_prng_seed(struct crypto_rng *tfm, const u8 *seed,
1179 unsigned int slen)
1180 {
1181 return 0;
1182 }
1183
1184 /*
1185 * Supported Crypto Algorithms
1186 */
1187 static struct crypto4xx_alg_common crypto4xx_alg[] = {
1188 /* Crypto AES modes */
1189 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1190 .base = {
1191 .cra_name = "cbc(aes)",
1192 .cra_driver_name = "cbc-aes-ppc4xx",
1193 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1194 .cra_flags = CRYPTO_ALG_ASYNC |
1195 CRYPTO_ALG_KERN_DRIVER_ONLY,
1196 .cra_blocksize = AES_BLOCK_SIZE,
1197 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1198 .cra_module = THIS_MODULE,
1199 },
1200 .min_keysize = AES_MIN_KEY_SIZE,
1201 .max_keysize = AES_MAX_KEY_SIZE,
1202 .ivsize = AES_IV_SIZE,
1203 .setkey = crypto4xx_setkey_aes_cbc,
1204 .encrypt = crypto4xx_encrypt_iv_block,
1205 .decrypt = crypto4xx_decrypt_iv_block,
1206 .init = crypto4xx_sk_init,
1207 .exit = crypto4xx_sk_exit,
1208 } },
1209 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1210 .base = {
1211 .cra_name = "ctr(aes)",
1212 .cra_driver_name = "ctr-aes-ppc4xx",
1213 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1214 .cra_flags = CRYPTO_ALG_NEED_FALLBACK |
1215 CRYPTO_ALG_ASYNC |
1216 CRYPTO_ALG_KERN_DRIVER_ONLY,
1217 .cra_blocksize = 1,
1218 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1219 .cra_module = THIS_MODULE,
1220 },
1221 .min_keysize = AES_MIN_KEY_SIZE,
1222 .max_keysize = AES_MAX_KEY_SIZE,
1223 .ivsize = AES_IV_SIZE,
1224 .setkey = crypto4xx_setkey_aes_ctr,
1225 .encrypt = crypto4xx_encrypt_ctr,
1226 .decrypt = crypto4xx_decrypt_ctr,
1227 .init = crypto4xx_sk_init,
1228 .exit = crypto4xx_sk_exit,
1229 } },
1230 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1231 .base = {
1232 .cra_name = "rfc3686(ctr(aes))",
1233 .cra_driver_name = "rfc3686-ctr-aes-ppc4xx",
1234 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1235 .cra_flags = CRYPTO_ALG_ASYNC |
1236 CRYPTO_ALG_KERN_DRIVER_ONLY,
1237 .cra_blocksize = 1,
1238 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1239 .cra_module = THIS_MODULE,
1240 },
1241 .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
1242 .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
1243 .ivsize = CTR_RFC3686_IV_SIZE,
1244 .setkey = crypto4xx_setkey_rfc3686,
1245 .encrypt = crypto4xx_rfc3686_encrypt,
1246 .decrypt = crypto4xx_rfc3686_decrypt,
1247 .init = crypto4xx_sk_init,
1248 .exit = crypto4xx_sk_exit,
1249 } },
1250 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1251 .base = {
1252 .cra_name = "ecb(aes)",
1253 .cra_driver_name = "ecb-aes-ppc4xx",
1254 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1255 .cra_flags = CRYPTO_ALG_ASYNC |
1256 CRYPTO_ALG_KERN_DRIVER_ONLY,
1257 .cra_blocksize = AES_BLOCK_SIZE,
1258 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1259 .cra_module = THIS_MODULE,
1260 },
1261 .min_keysize = AES_MIN_KEY_SIZE,
1262 .max_keysize = AES_MAX_KEY_SIZE,
1263 .setkey = crypto4xx_setkey_aes_ecb,
1264 .encrypt = crypto4xx_encrypt_noiv_block,
1265 .decrypt = crypto4xx_decrypt_noiv_block,
1266 .init = crypto4xx_sk_init,
1267 .exit = crypto4xx_sk_exit,
1268 } },
1269
1270 /* AEAD */
1271 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = {
1272 .setkey = crypto4xx_setkey_aes_ccm,
1273 .setauthsize = crypto4xx_setauthsize_aead,
1274 .encrypt = crypto4xx_encrypt_aes_ccm,
1275 .decrypt = crypto4xx_decrypt_aes_ccm,
1276 .init = crypto4xx_aead_init,
1277 .exit = crypto4xx_aead_exit,
1278 .ivsize = AES_BLOCK_SIZE,
1279 .maxauthsize = 16,
1280 .base = {
1281 .cra_name = "ccm(aes)",
1282 .cra_driver_name = "ccm-aes-ppc4xx",
1283 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1284 .cra_flags = CRYPTO_ALG_ASYNC |
1285 CRYPTO_ALG_NEED_FALLBACK |
1286 CRYPTO_ALG_KERN_DRIVER_ONLY,
1287 .cra_blocksize = 1,
1288 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1289 .cra_module = THIS_MODULE,
1290 },
1291 } },
1292 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = {
1293 .setkey = crypto4xx_setkey_aes_gcm,
1294 .setauthsize = crypto4xx_setauthsize_aead,
1295 .encrypt = crypto4xx_encrypt_aes_gcm,
1296 .decrypt = crypto4xx_decrypt_aes_gcm,
1297 .init = crypto4xx_aead_init,
1298 .exit = crypto4xx_aead_exit,
1299 .ivsize = GCM_AES_IV_SIZE,
1300 .maxauthsize = 16,
1301 .base = {
1302 .cra_name = "gcm(aes)",
1303 .cra_driver_name = "gcm-aes-ppc4xx",
1304 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1305 .cra_flags = CRYPTO_ALG_ASYNC |
1306 CRYPTO_ALG_NEED_FALLBACK |
1307 CRYPTO_ALG_KERN_DRIVER_ONLY,
1308 .cra_blocksize = 1,
1309 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1310 .cra_module = THIS_MODULE,
1311 },
1312 } },
1313 { .type = CRYPTO_ALG_TYPE_RNG, .u.rng = {
1314 .base = {
1315 .cra_name = "stdrng",
1316 .cra_driver_name = "crypto4xx_rng",
1317 .cra_priority = 300,
1318 .cra_ctxsize = 0,
1319 .cra_module = THIS_MODULE,
1320 },
1321 .generate = crypto4xx_prng_generate,
1322 .seed = crypto4xx_prng_seed,
1323 .seedsize = 0,
1324 } },
1325 };
1326
1327 /*
1328 * Module Initialization Routine
1329 */
1330 static int crypto4xx_probe(struct platform_device *ofdev)
1331 {
1332 int rc;
1333 struct device *dev = &ofdev->dev;
1334 struct crypto4xx_core_device *core_dev;
1335 struct device_node *np;
1336 u32 pvr;
1337 bool is_revb = true;
1338
1339 np = of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto");
1340 if (np) {
1341 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1342 mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET);
1343 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1344 mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET);
1345 } else {
1346 np = of_find_compatible_node(NULL, NULL, "amcc,ppc405ex-crypto");
1347 if (np) {
1348 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1349 mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET);
1350 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1351 mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET);
1352 is_revb = false;
1353 } else {
1354 np = of_find_compatible_node(NULL, NULL, "amcc,ppc460sx-crypto");
1355 if (np) {
1356 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1357 mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET);
1358 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1359 mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET);
1360 } else {
1361 printk(KERN_ERR "Crypto Function Not supported!\n");
1362 return -EINVAL;
1363 }
1364 }
1365 }
1366
1367 of_node_put(np);
1368
1369 core_dev = devm_kzalloc(
1370 &ofdev->dev, sizeof(struct crypto4xx_core_device), GFP_KERNEL);
1371 if (!core_dev)
1372 return -ENOMEM;
1373
1374 dev_set_drvdata(dev, core_dev);
1375 core_dev->ofdev = ofdev;
1376 core_dev->dev = devm_kzalloc(
1377 &ofdev->dev, sizeof(struct crypto4xx_device), GFP_KERNEL);
1378 if (!core_dev->dev)
1379 return -ENOMEM;
1380
1381 /*
1382 * Older version of 460EX/GT have a hardware bug.
1383 * Hence they do not support H/W based security intr coalescing
1384 */
1385 pvr = mfspr(SPRN_PVR);
1386 if (is_revb && ((pvr >> 4) == 0x130218A)) {
1387 u32 min = PVR_MIN(pvr);
1388
1389 if (min < 4) {
1390 dev_info(dev, "RevA detected - disable interrupt coalescing\n");
1391 is_revb = false;
1392 }
1393 }
1394
1395 core_dev->dev->core_dev = core_dev;
1396 core_dev->dev->is_revb = is_revb;
1397 core_dev->device = dev;
1398 rc = devm_mutex_init(&ofdev->dev, &core_dev->rng_lock);
1399 if (rc)
1400 return rc;
1401 spin_lock_init(&core_dev->lock);
1402 INIT_LIST_HEAD(&core_dev->dev->alg_list);
1403 ratelimit_default_init(&core_dev->dev->aead_ratelimit);
1404 rc = crypto4xx_build_sdr(core_dev->dev);
1405 if (rc)
1406 goto err_build_sdr;
1407 rc = crypto4xx_build_pdr(core_dev->dev);
1408 if (rc)
1409 goto err_build_sdr;
1410
1411 rc = crypto4xx_build_gdr(core_dev->dev);
1412 if (rc)
1413 goto err_build_sdr;
1414
1415 /* Init tasklet for bottom half processing */
1416 tasklet_init(&core_dev->tasklet, crypto4xx_bh_tasklet_cb,
1417 (unsigned long) dev);
1418
1419 core_dev->dev->ce_base = devm_platform_ioremap_resource(ofdev, 0);
1420 if (IS_ERR(core_dev->dev->ce_base)) {
1421 dev_err(&ofdev->dev, "failed to ioremap resource");
1422 rc = PTR_ERR(core_dev->dev->ce_base);
1423 goto err_build_sdr;
1424 }
1425
1426 /* Register for Crypto isr, Crypto Engine IRQ */
1427 core_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1428 rc = devm_request_irq(&ofdev->dev, core_dev->irq,
1429 is_revb ? crypto4xx_ce_interrupt_handler_revb :
1430 crypto4xx_ce_interrupt_handler,
1431 0, KBUILD_MODNAME, dev);
1432 if (rc)
1433 goto err_iomap;
1434
1435 /* need to setup pdr, rdr, gdr and sdr before this */
1436 crypto4xx_hw_init(core_dev->dev);
1437
1438 /* Register security algorithms with Linux CryptoAPI */
1439 rc = crypto4xx_register_alg(core_dev->dev, crypto4xx_alg,
1440 ARRAY_SIZE(crypto4xx_alg));
1441 if (rc)
1442 goto err_iomap;
1443
1444 ppc4xx_trng_probe(core_dev);
1445 return 0;
1446
1447 err_iomap:
1448 tasklet_kill(&core_dev->tasklet);
1449 err_build_sdr:
1450 crypto4xx_destroy_sdr(core_dev->dev);
1451 crypto4xx_destroy_gdr(core_dev->dev);
1452 crypto4xx_destroy_pdr(core_dev->dev);
1453 return rc;
1454 }
1455
1456 static void crypto4xx_remove(struct platform_device *ofdev)
1457 {
1458 struct device *dev = &ofdev->dev;
1459 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1460
1461 ppc4xx_trng_remove(core_dev);
1462
1463 tasklet_kill(&core_dev->tasklet);
1464 /* Un-register with Linux CryptoAPI */
1465 crypto4xx_unregister_alg(core_dev->dev);
1466 /* Free all allocated memory */
1467 crypto4xx_stop_all(core_dev);
1468 }
1469
1470 static const struct of_device_id crypto4xx_match[] = {
1471 { .compatible = "amcc,ppc4xx-crypto",},
1472 { },
1473 };
1474 MODULE_DEVICE_TABLE(of, crypto4xx_match);
1475
1476 static struct platform_driver crypto4xx_driver = {
1477 .driver = {
1478 .name = KBUILD_MODNAME,
1479 .of_match_table = crypto4xx_match,
1480 },
1481 .probe = crypto4xx_probe,
1482 .remove = crypto4xx_remove,
1483 };
1484
1485 module_platform_driver(crypto4xx_driver);
1486
1487 MODULE_LICENSE("GPL");
1488 MODULE_AUTHOR("James Hsiao <jhsiao@amcc.com>");
1489 MODULE_DESCRIPTION("Driver for AMCC PPC4xx crypto accelerator");
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