drivers/net/ipa/reg/gsi_reg-v4.5.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /* Copyright (C) 2023-2024 Linaro Ltd. */
   4
   5 #include <linux/array_size.h>
   6 #include <linux/bits.h>
   7 #include <linux/types.h>
   8
   9 #include "../gsi_reg.h"
  10 #include "../ipa_version.h"
  11 #include "../reg.h"
  12
  13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
  14     0x0000c020 + 0x1000 * GSI_EE_AP);
  15
  16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
  17     0x0000c024 + 0x1000 * GSI_EE_AP);
  18
  19 static const u32 reg_ch_c_cntxt_0_fmask[] = {
  20         [CHTYPE_PROTOCOL]                               = GENMASK(2, 0),
  21         [CHTYPE_DIR]                                    = BIT(3),
  22         [CH_EE]                                         = GENMASK(7, 4),
  23         [CHID]                                          = GENMASK(12, 8),
  24         [CHTYPE_PROTOCOL_MSB]                           = BIT(13),
  25         [ERINDEX]                                       = GENMASK(18, 14),
  26                                                 /* Bit 19 reserved */
  27         [CHSTATE]                                       = GENMASK(23, 20),
  28         [ELEMENT_SIZE]                                  = GENMASK(31, 24),
  29 };
  30
  31 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
  32                   0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
  33
  34 static const u32 reg_ch_c_cntxt_1_fmask[] = {
  35         [CH_R_LENGTH]                                   = GENMASK(15, 0),
  36                                                 /* Bits 16-31 reserved */
  37 };
  38
  39 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
  40                   0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
  41
  42 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
  43
  44 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
  45
  46 static const u32 reg_ch_c_qos_fmask[] = {
  47         [WRR_WEIGHT]                                    = GENMASK(3, 0),
  48                                                 /* Bits 4-7 reserved */
  49         [MAX_PREFETCH]                                  = BIT(8),
  50         [USE_DB_ENG]                                    = BIT(9),
  51         [PREFETCH_MODE]                                 = GENMASK(13, 10),
  52                                                 /* Bits 14-15 reserved */
  53         [EMPTY_LVL_THRSHOLD]                            = GENMASK(23, 16),
  54                                                 /* Bits 24-31 reserved */
  55 };
  56
  57 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
  58
  59 static const u32 reg_error_log_fmask[] = {
  60         [ERR_ARG3]                                      = GENMASK(3, 0),
  61         [ERR_ARG2]                                      = GENMASK(7, 4),
  62         [ERR_ARG1]                                      = GENMASK(11, 8),
  63         [ERR_CODE]                                      = GENMASK(15, 12),
  64                                                 /* Bits 16-18 reserved */
  65         [ERR_VIRT_IDX]                                  = GENMASK(23, 19),
  66         [ERR_TYPE]                                      = GENMASK(27, 24),
  67         [ERR_EE]                                        = GENMASK(31, 28),
  68 };
  69
  70 REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
  71            0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
  72
  73 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
  74            0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
  75
  76 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
  77            0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
  78
  79 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
  80            0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
  81
  82 static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
  83         [EV_CHTYPE]                                     = GENMASK(3, 0),
  84         [EV_EE]                                         = GENMASK(7, 4),
  85         [EV_EVCHID]                                     = GENMASK(15, 8),
  86         [EV_INTYPE]                                     = BIT(16),
  87                                                 /* Bits 17-19 reserved */
  88         [EV_CHSTATE]                                    = GENMASK(23, 20),
  89         [EV_ELEMENT_SIZE]                               = GENMASK(31, 24),
  90 };
  91
  92 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
  93                   0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
  94
  95 static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
  96         [R_LENGTH]                                      = GENMASK(15, 0),
  97 };
  98
  99 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
 100                   0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
 101
 102 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
 103            0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
 104
 105 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
 106            0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
 107
 108 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
 109            0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
 110
 111 static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
 112         [EV_MODT]                                       = GENMASK(15, 0),
 113         [EV_MODC]                                       = GENMASK(23, 16),
 114         [EV_MOD_CNT]                                    = GENMASK(31, 24),
 115 };
 116
 117 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
 118                   0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
 119
 120 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
 121            0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
 122
 123 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
 124            0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
 125
 126 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
 127            0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
 128
 129 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
 130            0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
 131
 132 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
 133            0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
 134
 135 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
 136            0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
 137
 138 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
 139            0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
 140
 141 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
 142            0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
 143
 144 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
 145            0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
 146
 147 static const u32 reg_gsi_status_fmask[] = {
 148         [ENABLED]                                       = BIT(0),
 149                                                 /* Bits 1-31 reserved */
 150 };
 151
 152 REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
 153
 154 static const u32 reg_ch_cmd_fmask[] = {
 155         [CH_CHID]                                       = GENMASK(7, 0),
 156                                                 /* Bits 8-23 reserved */
 157         [CH_OPCODE]                                     = GENMASK(31, 24),
 158 };
 159
 160 REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
 161
 162 static const u32 reg_ev_ch_cmd_fmask[] = {
 163         [EV_CHID]                                       = GENMASK(7, 0),
 164                                                 /* Bits 8-23 reserved */
 165         [EV_OPCODE]                                     = GENMASK(31, 24),
 166 };
 167
 168 REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
 169
 170 static const u32 reg_generic_cmd_fmask[] = {
 171         [GENERIC_OPCODE]                                = GENMASK(4, 0),
 172         [GENERIC_CHID]                                  = GENMASK(9, 5),
 173         [GENERIC_EE]                                    = GENMASK(13, 10),
 174                                                 /* Bits 14-31 reserved */
 175 };
 176
 177 REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
 178
 179 static const u32 reg_hw_param_2_fmask[] = {
 180         [IRAM_SIZE]                                     = GENMASK(2, 0),
 181         [NUM_CH_PER_EE]                                 = GENMASK(7, 3),
 182         [NUM_EV_PER_EE]                                 = GENMASK(12, 8),
 183         [GSI_CH_PEND_TRANSLATE]                         = BIT(13),
 184         [GSI_CH_FULL_LOGIC]                             = BIT(14),
 185         [GSI_USE_SDMA]                                  = BIT(15),
 186         [GSI_SDMA_N_INT]                                = GENMASK(18, 16),
 187         [GSI_SDMA_MAX_BURST]                            = GENMASK(26, 19),
 188         [GSI_SDMA_N_IOVEC]                              = GENMASK(29, 27),
 189         [GSI_USE_RD_WR_ENG]                             = BIT(30),
 190         [GSI_USE_INTER_EE]                              = BIT(31),
 191 };
 192
 193 REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
 194
 195 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
 196
 197 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
 198
 199 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
 200
 201 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
 202
 203 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
 204     0x00012098 + 0x4000 * GSI_EE_AP);
 205
 206 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
 207     0x0001209c + 0x4000 * GSI_EE_AP);
 208
 209 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
 210     0x000120a0 + 0x4000 * GSI_EE_AP);
 211
 212 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
 213     0x000120a4 + 0x4000 * GSI_EE_AP);
 214
 215 REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
 216
 217 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
 218     0x000120b8 + 0x4000 * GSI_EE_AP);
 219
 220 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
 221     0x000120c0 + 0x4000 * GSI_EE_AP);
 222
 223 REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
 224
 225 REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
 226
 227 REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
 228
 229 REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
 230
 231 REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
 232
 233 REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
 234
 235 static const u32 reg_cntxt_intset_fmask[] = {
 236         [INTYPE]                                        = BIT(0)
 237                                                 /* Bits 1-31 reserved */
 238 };
 239
 240 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
 241
 242 REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
 243
 244 REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
 245
 246 static const u32 reg_cntxt_scratch_0_fmask[] = {
 247         [INTER_EE_RESULT]                               = GENMASK(2, 0),
 248                                                 /* Bits 3-4 reserved */
 249         [GENERIC_EE_RESULT]                             = GENMASK(7, 5),
 250                                                 /* Bits 8-31 reserved */
 251 };
 252
 253 REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
 254
 255 static const struct reg *reg_array[] = {
 256         [INTER_EE_SRC_CH_IRQ_MSK]       = &reg_inter_ee_src_ch_irq_msk,
 257         [INTER_EE_SRC_EV_CH_IRQ_MSK]    = &reg_inter_ee_src_ev_ch_irq_msk,
 258         [CH_C_CNTXT_0]                  = &reg_ch_c_cntxt_0,
 259         [CH_C_CNTXT_1]                  = &reg_ch_c_cntxt_1,
 260         [CH_C_CNTXT_2]                  = &reg_ch_c_cntxt_2,
 261         [CH_C_CNTXT_3]                  = &reg_ch_c_cntxt_3,
 262         [CH_C_QOS]                      = &reg_ch_c_qos,
 263         [CH_C_SCRATCH_0]                = &reg_ch_c_scratch_0,
 264         [CH_C_SCRATCH_1]                = &reg_ch_c_scratch_1,
 265         [CH_C_SCRATCH_2]                = &reg_ch_c_scratch_2,
 266         [CH_C_SCRATCH_3]                = &reg_ch_c_scratch_3,
 267         [EV_CH_E_CNTXT_0]               = &reg_ev_ch_e_cntxt_0,
 268         [EV_CH_E_CNTXT_1]               = &reg_ev_ch_e_cntxt_1,
 269         [EV_CH_E_CNTXT_2]               = &reg_ev_ch_e_cntxt_2,
 270         [EV_CH_E_CNTXT_3]               = &reg_ev_ch_e_cntxt_3,
 271         [EV_CH_E_CNTXT_4]               = &reg_ev_ch_e_cntxt_4,
 272         [EV_CH_E_CNTXT_8]               = &reg_ev_ch_e_cntxt_8,
 273         [EV_CH_E_CNTXT_9]               = &reg_ev_ch_e_cntxt_9,
 274         [EV_CH_E_CNTXT_10]              = &reg_ev_ch_e_cntxt_10,
 275         [EV_CH_E_CNTXT_11]              = &reg_ev_ch_e_cntxt_11,
 276         [EV_CH_E_CNTXT_12]              = &reg_ev_ch_e_cntxt_12,
 277         [EV_CH_E_CNTXT_13]              = &reg_ev_ch_e_cntxt_13,
 278         [EV_CH_E_SCRATCH_0]             = &reg_ev_ch_e_scratch_0,
 279         [EV_CH_E_SCRATCH_1]             = &reg_ev_ch_e_scratch_1,
 280         [CH_C_DOORBELL_0]               = &reg_ch_c_doorbell_0,
 281         [EV_CH_E_DOORBELL_0]            = &reg_ev_ch_e_doorbell_0,
 282         [GSI_STATUS]                    = &reg_gsi_status,
 283         [CH_CMD]                        = &reg_ch_cmd,
 284         [EV_CH_CMD]                     = &reg_ev_ch_cmd,
 285         [GENERIC_CMD]                   = &reg_generic_cmd,
 286         [HW_PARAM_2]                    = &reg_hw_param_2,
 287         [CNTXT_TYPE_IRQ]                = &reg_cntxt_type_irq,
 288         [CNTXT_TYPE_IRQ_MSK]            = &reg_cntxt_type_irq_msk,
 289         [CNTXT_SRC_CH_IRQ]              = &reg_cntxt_src_ch_irq,
 290         [CNTXT_SRC_EV_CH_IRQ]           = &reg_cntxt_src_ev_ch_irq,
 291         [CNTXT_SRC_CH_IRQ_MSK]          = &reg_cntxt_src_ch_irq_msk,
 292         [CNTXT_SRC_EV_CH_IRQ_MSK]       = &reg_cntxt_src_ev_ch_irq_msk,
 293         [CNTXT_SRC_CH_IRQ_CLR]          = &reg_cntxt_src_ch_irq_clr,
 294         [CNTXT_SRC_EV_CH_IRQ_CLR]       = &reg_cntxt_src_ev_ch_irq_clr,
 295         [CNTXT_SRC_IEOB_IRQ]            = &reg_cntxt_src_ieob_irq,
 296         [CNTXT_SRC_IEOB_IRQ_MSK]        = &reg_cntxt_src_ieob_irq_msk,
 297         [CNTXT_SRC_IEOB_IRQ_CLR]        = &reg_cntxt_src_ieob_irq_clr,
 298         [CNTXT_GLOB_IRQ_STTS]           = &reg_cntxt_glob_irq_stts,
 299         [CNTXT_GLOB_IRQ_EN]             = &reg_cntxt_glob_irq_en,
 300         [CNTXT_GLOB_IRQ_CLR]            = &reg_cntxt_glob_irq_clr,
 301         [CNTXT_GSI_IRQ_STTS]            = &reg_cntxt_gsi_irq_stts,
 302         [CNTXT_GSI_IRQ_EN]              = &reg_cntxt_gsi_irq_en,
 303         [CNTXT_GSI_IRQ_CLR]             = &reg_cntxt_gsi_irq_clr,
 304         [CNTXT_INTSET]                  = &reg_cntxt_intset,
 305         [ERROR_LOG]                     = &reg_error_log,
 306         [ERROR_LOG_CLR]                 = &reg_error_log_clr,
 307         [CNTXT_SCRATCH_0]               = &reg_cntxt_scratch_0,
 308 };
 309
 310 const struct regs gsi_regs_v4_5 = {
 311         .reg_count      = ARRAY_SIZE(reg_array),
 312         .reg            = reg_array,
 313 };