drivers/pinctrl/pinctrl-mcp23s08.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* MCP23S08 SPI/I2C GPIO driver */
   3
   4 #include <linux/bitops.h>
   5 #include <linux/kernel.h>
   6 #include <linux/device.h>
   7 #include <linux/mutex.h>
   8 #include <linux/mod_devicetable.h>
   9 #include <linux/module.h>
  10 #include <linux/export.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/slab.h>
  15 #include <asm/byteorder.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/regmap.h>
  18 #include <linux/pinctrl/pinctrl.h>
  19 #include <linux/pinctrl/pinconf.h>
  20 #include <linux/pinctrl/pinconf-generic.h>
  21
  22 #include "pinctrl-mcp23s08.h"
  23
  24 /* Registers are all 8 bits wide.
  25  *
  26  * The mcp23s17 has twice as many bits, and can be configured to work
  27  * with either 16 bit registers or with two adjacent 8 bit banks.
  28  */
  29 #define MCP_IODIR       0x00            /* init/reset:  all ones */
  30 #define MCP_IPOL        0x01
  31 #define MCP_GPINTEN     0x02
  32 #define MCP_DEFVAL      0x03
  33 #define MCP_INTCON      0x04
  34 #define MCP_IOCON       0x05
  35 #       define IOCON_MIRROR     (1 << 6)
  36 #       define IOCON_SEQOP      (1 << 5)
  37 #       define IOCON_HAEN       (1 << 3)
  38 #       define IOCON_ODR        (1 << 2)
  39 #       define IOCON_INTPOL     (1 << 1)
  40 #       define IOCON_INTCC      (1)
  41 #define MCP_GPPU        0x06
  42 #define MCP_INTF        0x07
  43 #define MCP_INTCAP      0x08
  44 #define MCP_GPIO        0x09
  45 #define MCP_OLAT        0x0a
  46
  47 static const struct reg_default mcp23x08_defaults[] = {
  48         {.reg = MCP_IODIR,              .def = 0xff},
  49         {.reg = MCP_IPOL,               .def = 0x00},
  50         {.reg = MCP_GPINTEN,            .def = 0x00},
  51         {.reg = MCP_DEFVAL,             .def = 0x00},
  52         {.reg = MCP_INTCON,             .def = 0x00},
  53         {.reg = MCP_IOCON,              .def = 0x00},
  54         {.reg = MCP_GPPU,               .def = 0x00},
  55         {.reg = MCP_OLAT,               .def = 0x00},
  56 };
  57
  58 static const struct regmap_range mcp23x08_volatile_range = {
  59         .range_min = MCP_INTF,
  60         .range_max = MCP_GPIO,
  61 };
  62
  63 static const struct regmap_access_table mcp23x08_volatile_table = {
  64         .yes_ranges = &mcp23x08_volatile_range,
  65         .n_yes_ranges = 1,
  66 };
  67
  68 static const struct regmap_range mcp23x08_precious_range = {
  69         .range_min = MCP_GPIO,
  70         .range_max = MCP_GPIO,
  71 };
  72
  73 static const struct regmap_access_table mcp23x08_precious_table = {
  74         .yes_ranges = &mcp23x08_precious_range,
  75         .n_yes_ranges = 1,
  76 };
  77
  78 const struct regmap_config mcp23x08_regmap = {
  79         .reg_bits = 8,
  80         .val_bits = 8,
  81
  82         .reg_stride = 1,
  83         .volatile_table = &mcp23x08_volatile_table,
  84         .precious_table = &mcp23x08_precious_table,
  85         .reg_defaults = mcp23x08_defaults,
  86         .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
  87         .cache_type = REGCACHE_FLAT,
  88         .max_register = MCP_OLAT,
  89         .disable_locking = true, /* mcp->lock protects the regmap */
  90 };
  91 EXPORT_SYMBOL_GPL(mcp23x08_regmap);
  92
  93 static const struct reg_default mcp23x17_defaults[] = {
  94         {.reg = MCP_IODIR << 1,         .def = 0xffff},
  95         {.reg = MCP_IPOL << 1,          .def = 0x0000},
  96         {.reg = MCP_GPINTEN << 1,       .def = 0x0000},
  97         {.reg = MCP_DEFVAL << 1,        .def = 0x0000},
  98         {.reg = MCP_INTCON << 1,        .def = 0x0000},
  99         {.reg = MCP_IOCON << 1,         .def = 0x0000},
 100         {.reg = MCP_GPPU << 1,          .def = 0x0000},
 101         {.reg = MCP_OLAT << 1,          .def = 0x0000},
 102 };
 103
 104 static const struct regmap_range mcp23x17_volatile_range = {
 105         .range_min = MCP_INTF << 1,
 106         .range_max = MCP_GPIO << 1,
 107 };
 108
 109 static const struct regmap_access_table mcp23x17_volatile_table = {
 110         .yes_ranges = &mcp23x17_volatile_range,
 111         .n_yes_ranges = 1,
 112 };
 113
 114 static const struct regmap_range mcp23x17_precious_range = {
 115         .range_min = MCP_INTCAP << 1,
 116         .range_max = MCP_GPIO << 1,
 117 };
 118
 119 static const struct regmap_access_table mcp23x17_precious_table = {
 120         .yes_ranges = &mcp23x17_precious_range,
 121         .n_yes_ranges = 1,
 122 };
 123
 124 const struct regmap_config mcp23x17_regmap = {
 125         .reg_bits = 8,
 126         .val_bits = 16,
 127
 128         .reg_stride = 2,
 129         .max_register = MCP_OLAT << 1,
 130         .volatile_table = &mcp23x17_volatile_table,
 131         .precious_table = &mcp23x17_precious_table,
 132         .reg_defaults = mcp23x17_defaults,
 133         .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
 134         .cache_type = REGCACHE_FLAT,
 135         .val_format_endian = REGMAP_ENDIAN_LITTLE,
 136         .disable_locking = true, /* mcp->lock protects the regmap */
 137 };
 138 EXPORT_SYMBOL_GPL(mcp23x17_regmap);
 139
 140 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
 141 {
 142         return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
 143 }
 144
 145 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
 146 {
 147         return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
 148 }
 149
 150 static int mcp_update_bits(struct mcp23s08 *mcp, unsigned int reg,
 151                            unsigned int mask, unsigned int val)
 152 {
 153         return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
 154                                   mask, val);
 155 }
 156
 157 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
 158                        unsigned int pin, bool enabled)
 159 {
 160         u16 mask = BIT(pin);
 161         return mcp_update_bits(mcp, reg, mask, enabled ? mask : 0);
 162 }
 163
 164 static const struct pinctrl_pin_desc mcp23x08_pins[] = {
 165         PINCTRL_PIN(0, "gpio0"),
 166         PINCTRL_PIN(1, "gpio1"),
 167         PINCTRL_PIN(2, "gpio2"),
 168         PINCTRL_PIN(3, "gpio3"),
 169         PINCTRL_PIN(4, "gpio4"),
 170         PINCTRL_PIN(5, "gpio5"),
 171         PINCTRL_PIN(6, "gpio6"),
 172         PINCTRL_PIN(7, "gpio7"),
 173 };
 174
 175 static const struct pinctrl_pin_desc mcp23x17_pins[] = {
 176         PINCTRL_PIN(0, "gpio0"),
 177         PINCTRL_PIN(1, "gpio1"),
 178         PINCTRL_PIN(2, "gpio2"),
 179         PINCTRL_PIN(3, "gpio3"),
 180         PINCTRL_PIN(4, "gpio4"),
 181         PINCTRL_PIN(5, "gpio5"),
 182         PINCTRL_PIN(6, "gpio6"),
 183         PINCTRL_PIN(7, "gpio7"),
 184         PINCTRL_PIN(8, "gpio8"),
 185         PINCTRL_PIN(9, "gpio9"),
 186         PINCTRL_PIN(10, "gpio10"),
 187         PINCTRL_PIN(11, "gpio11"),
 188         PINCTRL_PIN(12, "gpio12"),
 189         PINCTRL_PIN(13, "gpio13"),
 190         PINCTRL_PIN(14, "gpio14"),
 191         PINCTRL_PIN(15, "gpio15"),
 192 };
 193
 194 static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 195 {
 196         return 0;
 197 }
 198
 199 static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 200                                                 unsigned int group)
 201 {
 202         return NULL;
 203 }
 204
 205 static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 206                                         unsigned int group,
 207                                         const unsigned int **pins,
 208                                         unsigned int *num_pins)
 209 {
 210         return -ENOTSUPP;
 211 }
 212
 213 static const struct pinctrl_ops mcp_pinctrl_ops = {
 214         .get_groups_count = mcp_pinctrl_get_groups_count,
 215         .get_group_name = mcp_pinctrl_get_group_name,
 216         .get_group_pins = mcp_pinctrl_get_group_pins,
 217 #ifdef CONFIG_OF
 218         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 219         .dt_free_map = pinconf_generic_dt_free_map,
 220 #endif
 221 };
 222
 223 static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 224                               unsigned long *config)
 225 {
 226         struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
 227         enum pin_config_param param = pinconf_to_config_param(*config);
 228         unsigned int data, status;
 229         int ret;
 230
 231         switch (param) {
 232         case PIN_CONFIG_BIAS_PULL_UP:
 233                 mutex_lock(&mcp->lock);
 234                 ret = mcp_read(mcp, MCP_GPPU, &data);
 235                 mutex_unlock(&mcp->lock);
 236                 if (ret < 0)
 237                         return ret;
 238                 status = (data & BIT(pin)) ? 1 : 0;
 239                 break;
 240         default:
 241                 return -ENOTSUPP;
 242         }
 243
 244         *config = 0;
 245
 246         return status ? 0 : -EINVAL;
 247 }
 248
 249 static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 250                               unsigned long *configs, unsigned int num_configs)
 251 {
 252         struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
 253         enum pin_config_param param;
 254         u32 arg;
 255         int ret = 0;
 256         int i;
 257
 258         for (i = 0; i < num_configs; i++) {
 259                 param = pinconf_to_config_param(configs[i]);
 260                 arg = pinconf_to_config_argument(configs[i]);
 261
 262                 switch (param) {
 263                 case PIN_CONFIG_BIAS_PULL_UP:
 264                         mutex_lock(&mcp->lock);
 265                         ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
 266                         mutex_unlock(&mcp->lock);
 267                         break;
 268                 default:
 269                         dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
 270                         return -ENOTSUPP;
 271                 }
 272         }
 273
 274         return ret;
 275 }
 276
 277 static const struct pinconf_ops mcp_pinconf_ops = {
 278         .pin_config_get = mcp_pinconf_get,
 279         .pin_config_set = mcp_pinconf_set,
 280         .is_generic = true,
 281 };
 282
 283 /*----------------------------------------------------------------------*/
 284
 285 static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
 286 {
 287         struct mcp23s08 *mcp = gpiochip_get_data(chip);
 288         int status;
 289
 290         mutex_lock(&mcp->lock);
 291         status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
 292         mutex_unlock(&mcp->lock);
 293
 294         return status;
 295 }
 296
 297 static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
 298 {
 299         struct mcp23s08 *mcp = gpiochip_get_data(chip);
 300         int status, ret;
 301
 302         mutex_lock(&mcp->lock);
 303
 304         /* REVISIT reading this clears any IRQ ... */
 305         ret = mcp_read(mcp, MCP_GPIO, &status);
 306         if (ret < 0)
 307                 status = 0;
 308         else {
 309                 mcp->cached_gpio = status;
 310                 status = !!(status & (1 << offset));
 311         }
 312
 313         mutex_unlock(&mcp->lock);
 314         return status;
 315 }
 316
 317 static int mcp23s08_get_multiple(struct gpio_chip *chip,
 318                                  unsigned long *mask, unsigned long *bits)
 319 {
 320         struct mcp23s08 *mcp = gpiochip_get_data(chip);
 321         unsigned int status;
 322         int ret;
 323
 324         mutex_lock(&mcp->lock);
 325
 326         /* REVISIT reading this clears any IRQ ... */
 327         ret = mcp_read(mcp, MCP_GPIO, &status);
 328         if (ret < 0)
 329                 status = 0;
 330         else {
 331                 mcp->cached_gpio = status;
 332                 *bits = status;
 333         }
 334
 335         mutex_unlock(&mcp->lock);
 336         return ret;
 337 }
 338
 339 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
 340 {
 341         return mcp_update_bits(mcp, MCP_OLAT, mask, value ? mask : 0);
 342 }
 343
 344 static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
 345 {
 346         struct mcp23s08 *mcp = gpiochip_get_data(chip);
 347         unsigned mask = BIT(offset);
 348
 349         mutex_lock(&mcp->lock);
 350         __mcp23s08_set(mcp, mask, !!value);
 351         mutex_unlock(&mcp->lock);
 352 }
 353
 354 static void mcp23s08_set_multiple(struct gpio_chip *chip,
 355                                   unsigned long *mask, unsigned long *bits)
 356 {
 357         struct mcp23s08 *mcp = gpiochip_get_data(chip);
 358
 359         mutex_lock(&mcp->lock);
 360         mcp_update_bits(mcp, MCP_OLAT, *mask, *bits);
 361         mutex_unlock(&mcp->lock);
 362 }
 363
 364 static int
 365 mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 366 {
 367         struct mcp23s08 *mcp = gpiochip_get_data(chip);
 368         unsigned mask = BIT(offset);
 369         int status;
 370
 371         mutex_lock(&mcp->lock);
 372         status = __mcp23s08_set(mcp, mask, value);
 373         if (status == 0) {
 374                 status = mcp_update_bits(mcp, MCP_IODIR, mask, 0);
 375         }
 376         mutex_unlock(&mcp->lock);
 377         return status;
 378 }
 379
 380 /*----------------------------------------------------------------------*/
 381 static irqreturn_t mcp23s08_irq(int irq, void *data)
 382 {
 383         struct mcp23s08 *mcp = data;
 384         int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval, gpinten;
 385         unsigned long int enabled_interrupts;
 386         unsigned int child_irq;
 387         bool intf_set, intcap_changed, gpio_bit_changed,
 388                 defval_changed, gpio_set;
 389
 390         mutex_lock(&mcp->lock);
 391         if (mcp_read(mcp, MCP_INTF, &intf))
 392                 goto unlock;
 393
 394         if (intf == 0) {
 395                 /* There is no interrupt pending */
 396                 goto unlock;
 397         }
 398
 399         if (mcp_read(mcp, MCP_INTCAP, &intcap))
 400                 goto unlock;
 401
 402         if (mcp_read(mcp, MCP_INTCON, &intcon))
 403                 goto unlock;
 404
 405         if (mcp_read(mcp, MCP_GPINTEN, &gpinten))
 406                 goto unlock;
 407
 408         if (mcp_read(mcp, MCP_DEFVAL, &defval))
 409                 goto unlock;
 410
 411         /* This clears the interrupt(configurable on S18) */
 412         if (mcp_read(mcp, MCP_GPIO, &gpio))
 413                 goto unlock;
 414
 415         gpio_orig = mcp->cached_gpio;
 416         mcp->cached_gpio = gpio;
 417         mutex_unlock(&mcp->lock);
 418
 419         dev_dbg(mcp->chip.parent,
 420                 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
 421                 intcap, intf, gpio_orig, gpio);
 422
 423         enabled_interrupts = gpinten;
 424         for_each_set_bit(i, &enabled_interrupts, mcp->chip.ngpio) {
 425                 /*
 426                  * We must check all of the inputs with enabled interrupts
 427                  * on the chip, otherwise we may not notice a change
 428                  * on more than one pin.
 429                  *
 430                  * On at least the mcp23s17, INTCAP is only updated
 431                  * one byte at a time(INTCAPA and INTCAPB are
 432                  * not written to at the same time - only on a per-bank
 433                  * basis).
 434                  *
 435                  * INTF only contains the single bit that caused the
 436                  * interrupt per-bank.  On the mcp23s17, there is
 437                  * INTFA and INTFB.  If two pins are changed on the A
 438                  * side at the same time, INTF will only have one bit
 439                  * set.  If one pin on the A side and one pin on the B
 440                  * side are changed at the same time, INTF will have
 441                  * two bits set.  Thus, INTF can't be the only check
 442                  * to see if the input has changed.
 443                  */
 444
 445                 intf_set = intf & BIT(i);
 446                 if (i < 8 && intf_set)
 447                         intcap_mask = 0x00FF;
 448                 else if (i >= 8 && intf_set)
 449                         intcap_mask = 0xFF00;
 450                 else
 451                         intcap_mask = 0x00;
 452
 453                 intcap_changed = (intcap_mask &
 454                         (intcap & BIT(i))) !=
 455                         (intcap_mask & (BIT(i) & gpio_orig));
 456                 gpio_set = BIT(i) & gpio;
 457                 gpio_bit_changed = (BIT(i) & gpio_orig) !=
 458                         (BIT(i) & gpio);
 459                 defval_changed = (BIT(i) & intcon) &&
 460                         ((BIT(i) & gpio) !=
 461                         (BIT(i) & defval));
 462
 463                 if (((gpio_bit_changed || intcap_changed) &&
 464                         (BIT(i) & mcp->irq_rise) && gpio_set) ||
 465                     ((gpio_bit_changed || intcap_changed) &&
 466                         (BIT(i) & mcp->irq_fall) && !gpio_set) ||
 467                     defval_changed) {
 468                         child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
 469                         handle_nested_irq(child_irq);
 470                 }
 471         }
 472
 473         return IRQ_HANDLED;
 474
 475 unlock:
 476         mutex_unlock(&mcp->lock);
 477         return IRQ_HANDLED;
 478 }
 479
 480 static void mcp23s08_irq_mask(struct irq_data *data)
 481 {
 482         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 483         struct mcp23s08 *mcp = gpiochip_get_data(gc);
 484         unsigned int pos = irqd_to_hwirq(data);
 485
 486         mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
 487         gpiochip_disable_irq(gc, pos);
 488 }
 489
 490 static void mcp23s08_irq_unmask(struct irq_data *data)
 491 {
 492         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 493         struct mcp23s08 *mcp = gpiochip_get_data(gc);
 494         unsigned int pos = irqd_to_hwirq(data);
 495
 496         gpiochip_enable_irq(gc, pos);
 497         mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
 498 }
 499
 500 static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
 501 {
 502         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 503         struct mcp23s08 *mcp = gpiochip_get_data(gc);
 504         unsigned int pos = irqd_to_hwirq(data);
 505
 506         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 507                 mcp_set_bit(mcp, MCP_INTCON, pos, false);
 508                 mcp->irq_rise |= BIT(pos);
 509                 mcp->irq_fall |= BIT(pos);
 510         } else if (type & IRQ_TYPE_EDGE_RISING) {
 511                 mcp_set_bit(mcp, MCP_INTCON, pos, false);
 512                 mcp->irq_rise |= BIT(pos);
 513                 mcp->irq_fall &= ~BIT(pos);
 514         } else if (type & IRQ_TYPE_EDGE_FALLING) {
 515                 mcp_set_bit(mcp, MCP_INTCON, pos, false);
 516                 mcp->irq_rise &= ~BIT(pos);
 517                 mcp->irq_fall |= BIT(pos);
 518         } else if (type & IRQ_TYPE_LEVEL_HIGH) {
 519                 mcp_set_bit(mcp, MCP_INTCON, pos, true);
 520                 mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
 521         } else if (type & IRQ_TYPE_LEVEL_LOW) {
 522                 mcp_set_bit(mcp, MCP_INTCON, pos, true);
 523                 mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
 524         } else
 525                 return -EINVAL;
 526
 527         return 0;
 528 }
 529
 530 static void mcp23s08_irq_bus_lock(struct irq_data *data)
 531 {
 532         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 533         struct mcp23s08 *mcp = gpiochip_get_data(gc);
 534
 535         mutex_lock(&mcp->lock);
 536         regcache_cache_only(mcp->regmap, true);
 537 }
 538
 539 static void mcp23s08_irq_bus_unlock(struct irq_data *data)
 540 {
 541         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 542         struct mcp23s08 *mcp = gpiochip_get_data(gc);
 543
 544         regcache_cache_only(mcp->regmap, false);
 545         regcache_sync(mcp->regmap);
 546
 547         mutex_unlock(&mcp->lock);
 548 }
 549
 550 static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
 551 {
 552         struct gpio_chip *chip = &mcp->chip;
 553         int err;
 554         unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
 555
 556         if (mcp->irq_active_high)
 557                 irqflags |= IRQF_TRIGGER_HIGH;
 558         else
 559                 irqflags |= IRQF_TRIGGER_LOW;
 560
 561         err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
 562                                         mcp23s08_irq,
 563                                         irqflags, dev_name(chip->parent), mcp);
 564         if (err != 0) {
 565                 dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
 566                         mcp->irq, err);
 567                 return err;
 568         }
 569
 570         return 0;
 571 }
 572
 573 static void mcp23s08_irq_print_chip(struct irq_data *d, struct seq_file *p)
 574 {
 575         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 576         struct mcp23s08 *mcp = gpiochip_get_data(gc);
 577
 578         seq_puts(p, dev_name(mcp->dev));
 579 }
 580
 581 static const struct irq_chip mcp23s08_irq_chip = {
 582         .irq_mask = mcp23s08_irq_mask,
 583         .irq_unmask = mcp23s08_irq_unmask,
 584         .irq_set_type = mcp23s08_irq_set_type,
 585         .irq_bus_lock = mcp23s08_irq_bus_lock,
 586         .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
 587         .irq_print_chip = mcp23s08_irq_print_chip,
 588         .flags = IRQCHIP_IMMUTABLE,
 589         GPIOCHIP_IRQ_RESOURCE_HELPERS,
 590 };
 591
 592 /*----------------------------------------------------------------------*/
 593
 594 int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
 595                        unsigned int addr, unsigned int type, unsigned int base)
 596 {
 597         int status, ret;
 598         bool mirror = false;
 599         bool open_drain = false;
 600
 601         mutex_init(&mcp->lock);
 602
 603         mcp->dev = dev;
 604         mcp->addr = addr;
 605
 606         mcp->irq_active_high = false;
 607
 608         mcp->chip.direction_input = mcp23s08_direction_input;
 609         mcp->chip.get = mcp23s08_get;
 610         mcp->chip.get_multiple = mcp23s08_get_multiple;
 611         mcp->chip.direction_output = mcp23s08_direction_output;
 612         mcp->chip.set = mcp23s08_set;
 613         mcp->chip.set_multiple = mcp23s08_set_multiple;
 614
 615         mcp->chip.base = base;
 616         mcp->chip.can_sleep = true;
 617         mcp->chip.parent = dev;
 618         mcp->chip.owner = THIS_MODULE;
 619
 620         mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
 621
 622         /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
 623          * and MCP_IOCON.HAEN = 1, so we work with all chips.
 624          */
 625
 626         ret = mcp_read(mcp, MCP_IOCON, &status);
 627         if (ret < 0)
 628                 return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
 629
 630         mcp->irq_controller =
 631                 device_property_read_bool(dev, "interrupt-controller");
 632         if (mcp->irq && mcp->irq_controller) {
 633                 mcp->irq_active_high =
 634                         device_property_read_bool(dev,
 635                                               "microchip,irq-active-high");
 636
 637                 mirror = device_property_read_bool(dev, "microchip,irq-mirror");
 638                 open_drain = device_property_read_bool(dev, "drive-open-drain");
 639         }
 640
 641         if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
 642              mcp->irq_active_high || open_drain) {
 643                 /* mcp23s17 has IOCON twice, make sure they are in sync */
 644                 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
 645                 status |= IOCON_HAEN | (IOCON_HAEN << 8);
 646                 if (mcp->irq_active_high)
 647                         status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
 648                 else
 649                         status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
 650
 651                 if (mirror)
 652                         status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
 653
 654                 if (open_drain)
 655                         status |= IOCON_ODR | (IOCON_ODR << 8);
 656
 657                 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
 658                         status |= IOCON_INTCC | (IOCON_INTCC << 8);
 659
 660                 ret = mcp_write(mcp, MCP_IOCON, status);
 661                 if (ret < 0)
 662                         return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
 663         }
 664
 665         if (mcp->irq && mcp->irq_controller) {
 666                 struct gpio_irq_chip *girq = &mcp->chip.irq;
 667
 668                 gpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip);
 669                 /* This will let us handle the parent IRQ in the driver */
 670                 girq->parent_handler = NULL;
 671                 girq->num_parents = 0;
 672                 girq->parents = NULL;
 673                 girq->default_type = IRQ_TYPE_NONE;
 674                 girq->handler = handle_simple_irq;
 675                 girq->threaded = true;
 676         }
 677
 678         ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
 679         if (ret < 0)
 680                 return dev_err_probe(dev, ret, "can't add GPIO chip\n");
 681
 682         mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
 683         mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
 684         mcp->pinctrl_desc.npins = mcp->chip.ngpio;
 685         if (mcp->pinctrl_desc.npins == 8)
 686                 mcp->pinctrl_desc.pins = mcp23x08_pins;
 687         else if (mcp->pinctrl_desc.npins == 16)
 688                 mcp->pinctrl_desc.pins = mcp23x17_pins;
 689         mcp->pinctrl_desc.owner = THIS_MODULE;
 690
 691         mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
 692         if (IS_ERR(mcp->pctldev))
 693                 return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
 694
 695         if (mcp->irq) {
 696                 ret = mcp23s08_irq_setup(mcp);
 697                 if (ret)
 698                         return dev_err_probe(dev, ret, "can't setup IRQ\n");
 699         }
 700
 701         return 0;
 702 }
 703 EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
 704
 705 MODULE_DESCRIPTION("MCP23S08 SPI/I2C GPIO driver");
 706 MODULE_LICENSE("GPL");