cpufreq/amd-pstate: Stop caching EPP
[pf-kernel.git] / drivers / soc / litex / litex_soc_ctrl.c
blobd08bfc8ef7be7a82c4639346e0e7867c2b120dee
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * LiteX SoC Controller Driver
5 * Copyright (C) 2020 Antmicro <www.antmicro.com>
7 */
9 #include <linux/litex.h>
10 #include <linux/device.h>
11 #include <linux/errno.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/printk.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/reboot.h>
19 /* reset register located at the base address */
20 #define RESET_REG_OFF 0x00
21 #define RESET_REG_VALUE 0x00000001
23 #define SCRATCH_REG_OFF 0x04
24 #define SCRATCH_REG_VALUE 0x12345678
25 #define SCRATCH_TEST_VALUE 0xdeadbeef
28 * Check LiteX CSR read/write access
30 * This function reads and writes a scratch register in order to verify if CSR
31 * access works.
33 * In case any problems are detected, the driver should panic.
35 * Access to the LiteX CSR is, by design, done in CPU native endianness.
36 * The driver should not dynamically configure access functions when
37 * the endianness mismatch is detected. Such situation indicates problems in
38 * the soft SoC design and should be solved at the LiteX generator level,
39 * not in the software.
41 static int litex_check_csr_access(void __iomem *reg_addr)
43 unsigned long reg;
45 reg = litex_read32(reg_addr + SCRATCH_REG_OFF);
47 if (reg != SCRATCH_REG_VALUE) {
48 panic("Scratch register read error - the system is probably broken! Expected: 0x%x but got: 0x%lx",
49 SCRATCH_REG_VALUE, reg);
50 return -EINVAL;
53 litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_TEST_VALUE);
54 reg = litex_read32(reg_addr + SCRATCH_REG_OFF);
56 if (reg != SCRATCH_TEST_VALUE) {
57 panic("Scratch register write error - the system is probably broken! Expected: 0x%x but got: 0x%lx",
58 SCRATCH_TEST_VALUE, reg);
59 return -EINVAL;
62 /* restore original value of the SCRATCH register */
63 litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_VALUE);
65 pr_info("LiteX SoC Controller driver initialized");
67 return 0;
70 struct litex_soc_ctrl_device {
71 void __iomem *base;
72 struct notifier_block reset_nb;
75 static int litex_reset_handler(struct notifier_block *this, unsigned long mode,
76 void *cmd)
78 struct litex_soc_ctrl_device *soc_ctrl_dev =
79 container_of(this, struct litex_soc_ctrl_device, reset_nb);
81 litex_write32(soc_ctrl_dev->base + RESET_REG_OFF, RESET_REG_VALUE);
82 return NOTIFY_DONE;
85 static const struct of_device_id litex_soc_ctrl_of_match[] = {
86 {.compatible = "litex,soc-controller"},
87 {},
89 MODULE_DEVICE_TABLE(of, litex_soc_ctrl_of_match);
91 static int litex_soc_ctrl_probe(struct platform_device *pdev)
93 struct litex_soc_ctrl_device *soc_ctrl_dev;
94 int error;
96 soc_ctrl_dev = devm_kzalloc(&pdev->dev, sizeof(*soc_ctrl_dev), GFP_KERNEL);
97 if (!soc_ctrl_dev)
98 return -ENOMEM;
100 soc_ctrl_dev->base = devm_platform_ioremap_resource(pdev, 0);
101 if (IS_ERR(soc_ctrl_dev->base))
102 return PTR_ERR(soc_ctrl_dev->base);
104 error = litex_check_csr_access(soc_ctrl_dev->base);
105 if (error)
106 return error;
108 platform_set_drvdata(pdev, soc_ctrl_dev);
110 soc_ctrl_dev->reset_nb.notifier_call = litex_reset_handler;
111 soc_ctrl_dev->reset_nb.priority = 128;
112 error = register_restart_handler(&soc_ctrl_dev->reset_nb);
113 if (error) {
114 dev_warn(&pdev->dev, "cannot register restart handler: %d\n",
115 error);
118 return 0;
121 static void litex_soc_ctrl_remove(struct platform_device *pdev)
123 struct litex_soc_ctrl_device *soc_ctrl_dev = platform_get_drvdata(pdev);
125 unregister_restart_handler(&soc_ctrl_dev->reset_nb);
128 static struct platform_driver litex_soc_ctrl_driver = {
129 .driver = {
130 .name = "litex-soc-controller",
131 .of_match_table = litex_soc_ctrl_of_match,
133 .probe = litex_soc_ctrl_probe,
134 .remove = litex_soc_ctrl_remove,
137 module_platform_driver(litex_soc_ctrl_driver);
138 MODULE_DESCRIPTION("LiteX SoC Controller driver");
139 MODULE_AUTHOR("Antmicro <www.antmicro.com>");
140 MODULE_LICENSE("GPL v2");