drivers/staging/fbtft/fb_ili9320.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * FB driver for the ILI9320 LCD Controller
   4  *
   5  * Copyright (C) 2013 Noralf Tronnes
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/init.h>
  11 #include <linux/spi/spi.h>
  12 #include <linux/delay.h>
  13
  14 #include "fbtft.h"
  15
  16 #define DRVNAME         "fb_ili9320"
  17 #define WIDTH           240
  18 #define HEIGHT          320
  19 #define DEFAULT_GAMMA   "07 07 6 0 0 0 5 5 4 0\n" \
  20                         "07 08 4 7 5 1 2 0 7 7"
  21
  22 static unsigned int read_devicecode(struct fbtft_par *par)
  23 {
  24         u8 rxbuf[8] = {0, };
  25
  26         write_reg(par, 0x0000);
  27         par->fbtftops.read(par, rxbuf, 4);
  28         return (rxbuf[2] << 8) | rxbuf[3];
  29 }
  30
  31 static int init_display(struct fbtft_par *par)
  32 {
  33         unsigned int devcode;
  34
  35         par->fbtftops.reset(par);
  36
  37         devcode = read_devicecode(par);
  38         if ((devcode != 0x0000) && (devcode != 0x9320))
  39                 dev_warn(par->info->device,
  40                          "Unrecognized Device code: 0x%04X (expected 0x9320)\n",
  41                         devcode);
  42
  43         /* Initialization sequence from ILI9320 Application Notes */
  44
  45         /* *********** Start Initial Sequence ********* */
  46         /* Set the Vcore voltage and this setting is must. */
  47         write_reg(par, 0x00E5, 0x8000);
  48
  49         /* Start internal OSC. */
  50         write_reg(par, 0x0000, 0x0001);
  51
  52         /* set SS and SM bit */
  53         write_reg(par, 0x0001, 0x0100);
  54
  55         /* set 1 line inversion */
  56         write_reg(par, 0x0002, 0x0700);
  57
  58         /* Resize register */
  59         write_reg(par, 0x0004, 0x0000);
  60
  61         /* set the back and front porch */
  62         write_reg(par, 0x0008, 0x0202);
  63
  64         /* set non-display area refresh cycle */
  65         write_reg(par, 0x0009, 0x0000);
  66
  67         /* FMARK function */
  68         write_reg(par, 0x000A, 0x0000);
  69
  70         /* RGB interface setting */
  71         write_reg(par, 0x000C, 0x0000);
  72
  73         /* Frame marker Position */
  74         write_reg(par, 0x000D, 0x0000);
  75
  76         /* RGB interface polarity */
  77         write_reg(par, 0x000F, 0x0000);
  78
  79         /* ***********Power On sequence *************** */
  80         /* SAP, BT[3:0], AP, DSTB, SLP, STB */
  81         write_reg(par, 0x0010, 0x0000);
  82
  83         /* DC1[2:0], DC0[2:0], VC[2:0] */
  84         write_reg(par, 0x0011, 0x0007);
  85
  86         /* VREG1OUT voltage */
  87         write_reg(par, 0x0012, 0x0000);
  88
  89         /* VDV[4:0] for VCOM amplitude */
  90         write_reg(par, 0x0013, 0x0000);
  91
  92         /* Dis-charge capacitor power voltage */
  93         mdelay(200);
  94
  95         /* SAP, BT[3:0], AP, DSTB, SLP, STB */
  96         write_reg(par, 0x0010, 0x17B0);
  97
  98         /* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */
  99         write_reg(par, 0x0011, 0x0031);
 100         mdelay(50);
 101
 102         /* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */
 103         write_reg(par, 0x0012, 0x0138);
 104         mdelay(50);
 105
 106         /* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */
 107         write_reg(par, 0x0013, 0x1800);
 108
 109         /* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */
 110         write_reg(par, 0x0029, 0x0008);
 111         mdelay(50);
 112
 113         /* GRAM horizontal Address */
 114         write_reg(par, 0x0020, 0x0000);
 115
 116         /* GRAM Vertical Address */
 117         write_reg(par, 0x0021, 0x0000);
 118
 119         /* ------------------ Set GRAM area --------------- */
 120         /* Horizontal GRAM Start Address */
 121         write_reg(par, 0x0050, 0x0000);
 122
 123         /* Horizontal GRAM End Address */
 124         write_reg(par, 0x0051, 0x00EF);
 125
 126         /* Vertical GRAM Start Address */
 127         write_reg(par, 0x0052, 0x0000);
 128
 129         /* Vertical GRAM End Address */
 130         write_reg(par, 0x0053, 0x013F);
 131
 132         /* Gate Scan Line */
 133         write_reg(par, 0x0060, 0x2700);
 134
 135         /* NDL,VLE, REV */
 136         write_reg(par, 0x0061, 0x0001);
 137
 138         /* set scrolling line */
 139         write_reg(par, 0x006A, 0x0000);
 140
 141         /* -------------- Partial Display Control --------- */
 142         write_reg(par, 0x0080, 0x0000);
 143         write_reg(par, 0x0081, 0x0000);
 144         write_reg(par, 0x0082, 0x0000);
 145         write_reg(par, 0x0083, 0x0000);
 146         write_reg(par, 0x0084, 0x0000);
 147         write_reg(par, 0x0085, 0x0000);
 148
 149         /* -------------- Panel Control ------------------- */
 150         write_reg(par, 0x0090, 0x0010);
 151         write_reg(par, 0x0092, 0x0000);
 152         write_reg(par, 0x0093, 0x0003);
 153         write_reg(par, 0x0095, 0x0110);
 154         write_reg(par, 0x0097, 0x0000);
 155         write_reg(par, 0x0098, 0x0000);
 156         write_reg(par, 0x0007, 0x0173); /* 262K color and display ON */
 157
 158         return 0;
 159 }
 160
 161 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
 162 {
 163         switch (par->info->var.rotate) {
 164         /* R20h = Horizontal GRAM Start Address */
 165         /* R21h = Vertical GRAM Start Address */
 166         case 0:
 167                 write_reg(par, 0x0020, xs);
 168                 write_reg(par, 0x0021, ys);
 169                 break;
 170         case 180:
 171                 write_reg(par, 0x0020, WIDTH - 1 - xs);
 172                 write_reg(par, 0x0021, HEIGHT - 1 - ys);
 173                 break;
 174         case 270:
 175                 write_reg(par, 0x0020, WIDTH - 1 - ys);
 176                 write_reg(par, 0x0021, xs);
 177                 break;
 178         case 90:
 179                 write_reg(par, 0x0020, ys);
 180                 write_reg(par, 0x0021, HEIGHT - 1 - xs);
 181                 break;
 182         }
 183         write_reg(par, 0x0022); /* Write Data to GRAM */
 184 }
 185
 186 static int set_var(struct fbtft_par *par)
 187 {
 188         switch (par->info->var.rotate) {
 189         case 0:
 190                 write_reg(par, 0x3, (par->bgr << 12) | 0x30);
 191                 break;
 192         case 270:
 193                 write_reg(par, 0x3, (par->bgr << 12) | 0x28);
 194                 break;
 195         case 180:
 196                 write_reg(par, 0x3, (par->bgr << 12) | 0x00);
 197                 break;
 198         case 90:
 199                 write_reg(par, 0x3, (par->bgr << 12) | 0x18);
 200                 break;
 201         }
 202         return 0;
 203 }
 204
 205 /*
 206  * Gamma string format:
 207  *  VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5
 208  *  VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5
 209  */
 210 #define CURVE(num, idx)  curves[(num) * par->gamma.num_values + (idx)]
 211 static int set_gamma(struct fbtft_par *par, u32 *curves)
 212 {
 213         static const unsigned long mask[] = {
 214                 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
 215                 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
 216         };
 217         int i, j;
 218
 219         /* apply mask */
 220         for (i = 0; i < 2; i++)
 221                 for (j = 0; j < 10; j++)
 222                         CURVE(i, j) &= mask[i * par->gamma.num_values + j];
 223
 224         write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
 225         write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
 226         write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
 227         write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2));
 228         write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0));
 229
 230         write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4));
 231         write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6));
 232         write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8));
 233         write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2));
 234         write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0));
 235
 236         return 0;
 237 }
 238
 239 #undef CURVE
 240
 241 static struct fbtft_display display = {
 242         .regwidth = 16,
 243         .width = WIDTH,
 244         .height = HEIGHT,
 245         .gamma_num = 2,
 246         .gamma_len = 10,
 247         .gamma = DEFAULT_GAMMA,
 248         .fbtftops = {
 249                 .init_display = init_display,
 250                 .set_addr_win = set_addr_win,
 251                 .set_var = set_var,
 252                 .set_gamma = set_gamma,
 253         },
 254 };
 255
 256 FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display);
 257
 258 MODULE_ALIAS("spi:" DRVNAME);
 259 MODULE_ALIAS("platform:" DRVNAME);
 260 MODULE_ALIAS("spi:ili9320");
 261 MODULE_ALIAS("platform:ili9320");
 262
 263 MODULE_DESCRIPTION("FB driver for the ILI9320 LCD Controller");
 264 MODULE_AUTHOR("Noralf Tronnes");
 265 MODULE_LICENSE("GPL");