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1 /*
2 Copyright (c) 2003, Keir Fraser All rights reserved.
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5 modification, are permitted provided that the following conditions are
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14 * nor the names of its contributors may be used to endorse or
15 * promote products derived from this software without specific
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31 #ifndef __PPC_DEFNS_H__
32 #define __PPC_DEFNS_H__
34 #ifndef PPC
35 #define PPC
36 #endif
38 #include <stdlib.h>
39 #include <sys/types.h>
40 #include <sched.h>
42 #define CACHE_LINE_SIZE 64
44 #include <pthread.h>
48 * I. Compare-and-swap.
51 static int FAS32(void *, int);
52 static long FAS64(void *, long);
53 static int CAS32(void *, int, int);
54 static long CAS64(void *, long, long);
56 #pragma mc_func FAS32 { \
57 "7c001828" /* 1: lwarx r0,0,r3 */ \
58 "7c80192d" /* stwcx r4,0,r3 */ \
59 "4082fff8" /* bne 1 */ \
60 "60030000" /* ori r3,0,r0 */ \
63 #pragma mc_func FAS64 { \
64 "7c0018a8" /* 1: ldarx r0,0,r3 */ \
65 "7c8019ad" /* stdcx r4,0,r3 */ \
66 "4082fff8" /* bne 1 */ \
67 "60030000" /* ori r3,0,r0 */ \
70 #pragma mc_func CAS32 { \
71 "7c001828" /* 1: lwarx r0,0,r3 */ \
72 "7c002000" /* cmpw r0,r4 */ \
73 "4082000c" /* bne 2 */ \
74 "7ca0192d" /* stwcx r5,0,r3 */ \
75 "4082fff0" /* bne 1 */ \
76 "60030000" /* 2: ori r3,0,r0 */ \
79 #pragma mc_func CAS64 { \
80 "7c0018a8" /* 1: ldarx r0,0,r3 */ \
81 "7c202000" /* cmpd r0,r4 */ \
82 "4082000c" /* bne 2 */ \
83 "7ca019ad" /* stdcx r5,0,r3 */ \
84 "4082fff0" /* bne 1 */ \
85 "60030000" /* 2: ori r3,0,r0 */ \
88 #define CASIO(_a,_o,_n) ((int)CAS32((int*)(_a),(int)(_o),(int)(_n)))
89 #define FASIO(_a,_n) ((int)FAS32((int*)(_a),(int)(_n)))
90 #define CASPO(_a,_o,_n) ((void *)(CAS64((long*)(_a),(long)(_o),(long)(_n))))
91 #define FASPO(_a,_n) ((void *)(FAS64((long*)(_a),(long)(_n))))
92 #define CAS32O(_a,_o,_n) ((_u32)(CAS32((_u32*)(_a),(_u32)(_o),(_u32)(_n))))
93 #define CAS64O(_a,_o,_n) ((_u64)(CAS64((long*)(_a),(long)(_o),(long)(_n))))
97 * II. Memory barriers.
98 * WMB(): All preceding write operations must commit before any later writes.
99 * RMB(): All preceding read operations must commit before any later reads.
100 * MB(): All preceding memory accesses must commit before any later accesses.
102 * If the compiler does not observe these barriers (but any sane compiler
103 * will!), then VOLATILE should be defined as 'volatile'.
106 static void WMB(void);
107 static void RMB(void);
108 static void MB(void);
110 #pragma mc_func WMB { "7c0004ac" } /* msync (orders memory transactions) */
111 #pragma mc_func RMB { "4c00012c" } /* isync (orders instruction issue) */
112 #pragma mc_func MB { "7c0004ac" } /* msync (orders memory transactions) */
114 #define VOLATILE /*volatile*/
118 * III. Cycle counter access.
121 typedef unsigned long tick_t;
122 static tick_t RDTICK(void);
123 #pragma mc_func RDTICK { "7c6c42e6" } /* mftb r3 */
127 * IV. Types.
130 typedef unsigned char _u8;
131 typedef unsigned short _u16;
132 typedef unsigned int _u32;
133 typedef unsigned long _u64;
135 #endif /* __PPC_DEFNS_H__ */