1 Binary file Targets/EV64240/compile/EV64240EL/disassemble.o matches
2 Targets/EV64240/compile/EV64240EL/machine/cpu.h:#define COP_0_PRID $15
3 Targets/EV64240/compile/EV64240EL/machine/cpu.h: * CPU identification, from PRID register.
4 Targets/EV64240/compile/EV64240EL/machine/cpu.h~:#define COP_0_PRID $15
5 Targets/EV64240/compile/EV64240EL/machine/cpu.h~: * CPU identification, from PRID register.
6 Targets/EV64240/compile/EV64240EL/machine/regnum.h:#define PRID (AUXBASE+25)
7 Binary file Targets/EV64240/compile/EV64240EL/pmon matches
8 Binary file Targets/EV64240/compile/EV64240EL/pmon.bin matches
9 Targets/EV64240/compile/EV64240EL/pmon.dis:ffffffff80094fe0: 00000047 00000000 505f3043 00444952 G.......C0_PRID.
10 doc/cat/c_r:C0_PRID: IMP Rev
11 pmon/arch/mips/cache.S: mfc0 v1, COP_0_PRID # read processor ID register
12 pmon/arch/mips/cache.S: sw v1, CpuProcessorId # save PRID register
13 pmon/arch/mips/cache.S~: mfc0 v1, COP_0_PRID # read processor ID register
14 pmon/arch/mips/cache.S~: sw v1, CpuProcessorId # save PRID register
15 pmon/arch/mips/disassemble.c: "C0_SR", "C0_CAUSE", "C0_EPC", "C0_PRID",
16 pmon/arch/mips/mips.S: mfc0 t0, COP_0_PRID
17 pmon/arch/mips/mips.S: mfc0 t0, COP_0_PRID
18 pmon/arch/mips/mips.S: sd t0, PRID * RSIZE(k0)
19 pmon/arch/mips/mips.S: mfc0 v0, COP_0_PRID
20 sys/arch/mips/include/cpu.h:#define COP_0_PRID $15
21 sys/arch/mips/include/cpu.h: * CPU identification, from PRID register.
22 sys/arch/mips/include/cpu.h~:#define COP_0_PRID $15
23 sys/arch/mips/include/cpu.h~: * CPU identification, from PRID register.
24 sys/arch/mips/include/regnum.h:#define PRID (AUXBASE+25)
25 tags:COP_0_PRID Targets/EV64240/compile/EV64240EL/machine/cpu.h 172;" d
26 tags:COP_0_PRID sys/arch/mips/include/cpu.h 172;" d
27 tags:PRID Targets/EV64240/compile/EV64240EL/machine/regnum.h 159;" d
28 tags:PRID sys/arch/mips/include/regnum.h 159;" d