drivers/media/dvb/frontends/dibx000_common.h

   1 #ifndef DIBX000_COMMON_H
   2 #define DIBX000_COMMON_H
   3
   4 enum dibx000_i2c_interface {
   5         DIBX000_I2C_INTERFACE_TUNER = 0,
   6         DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
   7         DIBX000_I2C_INTERFACE_GPIO_3_4 = 2
   8 };
   9
  10 struct dibx000_i2c_master {
  11 #define DIB3000MC 1
  12 #define DIB7000   2
  13 #define DIB7000P  11
  14 #define DIB7000MC 12
  15 #define DIB8000   13
  16         u16 device_rev;
  17
  18         enum dibx000_i2c_interface selected_interface;
  19
  20 //      struct i2c_adapter  tuner_i2c_adap;
  21         struct i2c_adapter gated_tuner_i2c_adap;
  22
  23         struct i2c_adapter *i2c_adap;
  24         u8 i2c_addr;
  25
  26         u16 base_reg;
  27 };
  28
  29 extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
  30                                    u16 device_rev, struct i2c_adapter *i2c_adap,
  31                                    u8 i2c_addr);
  32 extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
  33                                                    *mst,
  34                                                    enum dibx000_i2c_interface
  35                                                    intf, int gating);
  36 extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
  37 extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
  38
  39 extern u32 systime(void);
  40
  41 #define BAND_LBAND 0x01
  42 #define BAND_UHF   0x02
  43 #define BAND_VHF   0x04
  44 #define BAND_SBAND 0x08
  45 #define BAND_FM    0x10
  46 #define BAND_CBAND 0x20
  47
  48 #define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
  49                                                                         (freq_kHz) <= 115000 ? BAND_FM : \
  50                                                                         (freq_kHz) <= 250000 ? BAND_VHF : \
  51                                                                         (freq_kHz) <= 863000 ? BAND_UHF : \
  52                                                                         (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
  53
  54 struct dibx000_agc_config {
  55         /* defines the capabilities of this AGC-setting - using the BAND_-defines */
  56         u8 band_caps;
  57
  58         u16 setup;
  59
  60         u16 inv_gain;
  61         u16 time_stabiliz;
  62
  63         u8 alpha_level;
  64         u16 thlock;
  65
  66         u8 wbd_inv;
  67         u16 wbd_ref;
  68         u8 wbd_sel;
  69         u8 wbd_alpha;
  70
  71         u16 agc1_max;
  72         u16 agc1_min;
  73         u16 agc2_max;
  74         u16 agc2_min;
  75
  76         u8 agc1_pt1;
  77         u8 agc1_pt2;
  78         u8 agc1_pt3;
  79
  80         u8 agc1_slope1;
  81         u8 agc1_slope2;
  82
  83         u8 agc2_pt1;
  84         u8 agc2_pt2;
  85
  86         u8 agc2_slope1;
  87         u8 agc2_slope2;
  88
  89         u8 alpha_mant;
  90         u8 alpha_exp;
  91
  92         u8 beta_mant;
  93         u8 beta_exp;
  94
  95         u8 perform_agc_softsplit;
  96
  97         struct {
  98                 u16 min;
  99                 u16 max;
 100                 u16 min_thres;
 101                 u16 max_thres;
 102         } split;
 103 };
 104
 105 struct dibx000_bandwidth_config {
 106         u32 internal;
 107         u32 sampling;
 108
 109         u8 pll_prediv;
 110         u8 pll_ratio;
 111         u8 pll_range;
 112         u8 pll_reset;
 113         u8 pll_bypass;
 114
 115         u8 enable_refdiv;
 116         u8 bypclk_div;
 117         u8 IO_CLK_en_core;
 118         u8 ADClkSrc;
 119         u8 modulo;
 120
 121         u16 sad_cfg;
 122
 123         u32 ifreq;
 124         u32 timf;
 125
 126         u32 xtal_hz;
 127 };
 128
 129 enum dibx000_adc_states {
 130         DIBX000_SLOW_ADC_ON = 0,
 131         DIBX000_SLOW_ADC_OFF,
 132         DIBX000_ADC_ON,
 133         DIBX000_ADC_OFF,
 134         DIBX000_VBG_ENABLE,
 135         DIBX000_VBG_DISABLE,
 136 };
 137
 138 #define BANDWIDTH_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ  ? 8000 : \
 139                              (v) == BANDWIDTH_7_MHZ  ? 7000 : \
 140                              (v) == BANDWIDTH_6_MHZ  ? 6000 : 8000 )
 141
 142 #define BANDWIDTH_TO_INDEX(v) ( \
 143         (v) == 8000 ? BANDWIDTH_8_MHZ : \
 144                 (v) == 7000 ? BANDWIDTH_7_MHZ : \
 145                 (v) == 6000 ? BANDWIDTH_6_MHZ : BANDWIDTH_8_MHZ )
 146
 147 /* Chip output mode. */
 148 #define OUTMODE_HIGH_Z              0
 149 #define OUTMODE_MPEG2_PAR_GATED_CLK 1
 150 #define OUTMODE_MPEG2_PAR_CONT_CLK  2
 151 #define OUTMODE_MPEG2_SERIAL        7
 152 #define OUTMODE_DIVERSITY           4
 153 #define OUTMODE_MPEG2_FIFO          5
 154 #define OUTMODE_ANALOG_ADC          6
 155
 156 enum frontend_tune_state {
 157     CT_TUNER_START = 10,
 158     CT_TUNER_STEP_0,
 159     CT_TUNER_STEP_1,
 160     CT_TUNER_STEP_2,
 161     CT_TUNER_STEP_3,
 162     CT_TUNER_STEP_4,
 163     CT_TUNER_STEP_5,
 164     CT_TUNER_STEP_6,
 165     CT_TUNER_STEP_7,
 166     CT_TUNER_STOP,
 167
 168     CT_AGC_START = 20,
 169     CT_AGC_STEP_0,
 170     CT_AGC_STEP_1,
 171     CT_AGC_STEP_2,
 172     CT_AGC_STEP_3,
 173     CT_AGC_STEP_4,
 174     CT_AGC_STOP,
 175
 176         CT_DEMOD_START = 30,
 177     CT_DEMOD_STEP_1,
 178     CT_DEMOD_STEP_2,
 179     CT_DEMOD_STEP_3,
 180     CT_DEMOD_STEP_4,
 181     CT_DEMOD_STEP_5,
 182     CT_DEMOD_STEP_6,
 183     CT_DEMOD_STEP_7,
 184     CT_DEMOD_STEP_8,
 185     CT_DEMOD_STEP_9,
 186     CT_DEMOD_STEP_10,
 187     CT_DEMOD_SEARCH_NEXT = 41,
 188     CT_DEMOD_STEP_LOCKED,
 189     CT_DEMOD_STOP,
 190
 191     CT_DONE = 100,
 192     CT_SHUTDOWN,
 193
 194 };
 195
 196 struct dvb_frontend_parametersContext {
 197 #define CHANNEL_STATUS_PARAMETERS_UNKNOWN   0x01
 198 #define CHANNEL_STATUS_PARAMETERS_SET       0x02
 199     u8 status;
 200     u32 tune_time_estimation[2];
 201     s32 tps_available;
 202     u16 tps[9];
 203 };
 204
 205 #define FE_STATUS_TUNE_FAILED          0
 206 #define FE_STATUS_TUNE_TIMED_OUT      -1
 207 #define FE_STATUS_TUNE_TIME_TOO_SHORT -2
 208 #define FE_STATUS_TUNE_PENDING        -3
 209 #define FE_STATUS_STD_SUCCESS         -4
 210 #define FE_STATUS_FFT_SUCCESS         -5
 211 #define FE_STATUS_DEMOD_SUCCESS       -6
 212 #define FE_STATUS_LOCKED              -7
 213 #define FE_STATUS_DATA_LOCKED         -8
 214
 215 #define FE_CALLBACK_TIME_NEVER 0xffffffff
 216
 217 #define ABS(x) ((x < 0) ? (-x) : (x))
 218
 219 #endif