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Linux 2.6.34-rc3
[pohmelfs.git] / drivers / media / video / cx18 / cx18-av-core.c
blob4392c76af5df91da615f4ef67c766ebd34985e2a
1 /*
2 * cx18 ADEC audio functions
3 *
4 * Derived from cx25840-core.c
5 *
6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
7 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22 * 02110-1301, USA.
23 */
24
25 #include <media/v4l2-chip-ident.h>
26 #include "cx18-driver.h"
27 #include "cx18-io.h"
28 #include "cx18-cards.h"
29
30 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value)
31 {
32 u32 reg = 0xc40000 + (addr & ~3);
33 u32 mask = 0xff;
34 int shift = (addr & 3) * 8;
35 u32 x = cx18_read_reg(cx, reg);
36
37 x = (x & ~(mask << shift)) | ((u32)value << shift);
38 cx18_write_reg(cx, x, reg);
39 return 0;
40 }
41
42 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask)
43 {
44 u32 reg = 0xc40000 + (addr & ~3);
45 int shift = (addr & 3) * 8;
46 u32 x = cx18_read_reg(cx, reg);
47
48 x = (x & ~((u32)0xff << shift)) | ((u32)value << shift);
49 cx18_write_reg_expect(cx, x, reg,
50 ((u32)eval << shift), ((u32)mask << shift));
51 return 0;
52 }
53
54 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
55 {
56 cx18_write_reg(cx, value, 0xc40000 + addr);
57 return 0;
58 }
59
60 int
61 cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask)
62 {
63 cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask);
64 return 0;
65 }
66
67 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
68 {
69 cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
70 return 0;
71 }
72
73 u8 cx18_av_read(struct cx18 *cx, u16 addr)
74 {
75 u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
76 int shift = (addr & 3) * 8;
77
78 return (x >> shift) & 0xff;
79 }
80
81 u32 cx18_av_read4(struct cx18 *cx, u16 addr)
82 {
83 return cx18_read_reg(cx, 0xc40000 + addr);
84 }
85
86 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
87 u8 or_value)
88 {
89 return cx18_av_write(cx, addr,
90 (cx18_av_read(cx, addr) & and_mask) |
91 or_value);
92 }
93
94 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask,
95 u32 or_value)
96 {
97 return cx18_av_write4(cx, addr,
98 (cx18_av_read4(cx, addr) & and_mask) |
99 or_value);
100 }
101
102 static void cx18_av_init(struct cx18 *cx)
103 {
104 /*
105 * The crystal freq used in calculations in this driver will be
106 * 28.636360 MHz.
107 * Aim to run the PLLs' VCOs near 400 MHz to minimze errors.
108 */
109
110 /*
111 * VDCLK Integer = 0x0f, Post Divider = 0x04
112 * AIMCLK Integer = 0x0e, Post Divider = 0x16
113 */
114 cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
115
116 /* VDCLK Fraction = 0x2be2fe */
117 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
118 cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
119
120 /* AIMCLK Fraction = 0x05227ad */
121 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/
122 cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
123
124 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
125 cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
126 }
127
128 static void cx18_av_initialize(struct v4l2_subdev *sd)
129 {
130 struct cx18_av_state *state = to_cx18_av_state(sd);
131 struct cx18 *cx = v4l2_get_subdevdata(sd);
132 u32 v;
133
134 cx18_av_loadfw(cx);
135 /* Stop 8051 code execution */
136 cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
137 0x03000000, 0x13000000);
138
139 /* initallize the PLL by toggling sleep bit */
140 v = cx18_av_read4(cx, CXADEC_HOST_REG1);
141 /* enable sleep mode - register appears to be read only... */
142 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);
143 /* disable sleep mode */
144 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe,
145 v & 0xfffe, 0xffff);
146
147 /* initialize DLLs */
148 v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
149 /* disable FLD */
150 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v);
151 /* enable FLD */
152 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100);
153
154 v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
155 /* disable FLD */
156 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v);
157 /* enable FLD */
158 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100);
159
160 /* set analog bias currents. Set Vreg to 1.20V. */
161 cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802);
162
163 v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
164 /* enable TUNE_FIL_RST */
165 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F);
166 /* disable TUNE_FIL_RST */
167 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3,
168 v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F);
169
170 /* enable 656 output */
171 cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00);
172
173 /* video output drive strength */
174 cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2);
175
176 /* reset video */
177 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000);
178 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0);
179
180 /*
181 * Disable Video Auto-config of the Analog Front End and Video PLL.
182 *
183 * Since we only use BT.656 pixel mode, which works for both 525 and 625
184 * line systems, it's just easier for us to set registers
185 * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL),
186 * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC)
187 * ourselves, than to run around cleaning up after the auto-config.
188 *
189 * (Note: my CX23418 chip doesn't seem to let the ACFG_DIS bit
190 * get set to 1, but OTOH, it doesn't seem to do AFE and VID PLL
191 * autoconfig either.)
192 *
193 * As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3.
194 */
195 cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000);
196
197 /* Setup the Video and and Aux/Audio PLLs */
198 cx18_av_init(cx);
199
200 /* set video to auto-detect */
201 /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */
202 /* set the comb notch = 1 */
203 cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800);
204
205 /* Enable wtw_en in CRUSH_CTRL (Set bit 22) */
206 /* Enable maj_sel in CRUSH_CTRL (Set bit 20) */
207 cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000);
208
209 /* Set VGA_TRACK_RANGE to 0x20 */
210 cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000);
211
212 /*
213 * Initial VBI setup
214 * VIP-1.1, 10 bit mode, enable Raw, disable sliced,
215 * don't clamp raw samples when codes are in use, 1 byte user D-words,
216 * IDID0 has line #, RP code V bit transition on VBLANK, data during
217 * blanking intervals
218 */
219 cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e);
220
221 /* Set the video input.
222 The setting in MODE_CTRL gets lost when we do the above setup */
223 /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */
224 /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */
225
226 /*
227 * Analog Front End (AFE)
228 * Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2
229 * bypass_ch[1-3] use filter
230 * droop_comp_ch[1-3] disable
231 * clamp_en_ch[1-3] disable
232 * aud_in_sel ADC2
233 * luma_in_sel ADC1
234 * chroma_in_sel ADC2
235 * clamp_sel_ch[2-3] midcode
236 * clamp_sel_ch1 video decoder
237 * vga_sel_ch3 audio decoder
238 * vga_sel_ch[1-2] video decoder
239 * half_bw_ch[1-3] disable
240 * +12db_ch[1-3] disable
241 */
242 cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00);
243
244 /* if(dwEnable && dw3DCombAvailable) { */
245 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
246 /* } else { */
247 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
248 /* } */
249 cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F);
250 state->default_volume = 228 - cx18_av_read(cx, 0x8d4);
251 state->default_volume = ((state->default_volume / 2) + 23) << 9;
252 }
253
254 static int cx18_av_reset(struct v4l2_subdev *sd, u32 val)
255 {
256 cx18_av_initialize(sd);
257 return 0;
258 }
259
260 static int cx18_av_load_fw(struct v4l2_subdev *sd)
261 {
262 struct cx18_av_state *state = to_cx18_av_state(sd);
263
264 if (!state->is_initialized) {
265 /* initialize on first use */
266 state->is_initialized = 1;
267 cx18_av_initialize(sd);
268 }
269 return 0;
270 }
271
272 void cx18_av_std_setup(struct cx18 *cx)
273 {
274 struct cx18_av_state *state = &cx->av_state;
275 struct v4l2_subdev *sd = &state->sd;
276 v4l2_std_id std = state->std;
277
278 /*
279 * Video ADC crystal clock to pixel clock SRC decimation ratio
280 * 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b
281 */
282 const int src_decimation = 0x21f;
283
284 int hblank, hactive, burst, vblank, vactive, sc;
285 int vblank656;
286 int luma_lpf, uv_lpf, comb;
287 u32 pll_int, pll_frac, pll_post;
288
289 /* datasheet startup, step 8d */
290 if (std & ~V4L2_STD_NTSC)
291 cx18_av_write(cx, 0x49f, 0x11);
292 else
293 cx18_av_write(cx, 0x49f, 0x14);
294
295 /*
296 * Note: At the end of a field, there are 3 sets of half line duration
297 * (double horizontal rate) pulses:
298 *
299 * 5 (625) or 6 (525) half-lines to blank for the vertical retrace
300 * 5 (625) or 6 (525) vertical sync pulses of half line duration
301 * 5 (625) or 6 (525) half-lines of equalization pulses
302 */
303 if (std & V4L2_STD_625_50) {
304 /*
305 * The following relationships of half line counts should hold:
306 * 625 = vblank656 + vactive
307 * 10 = vblank656 - vblank = vsync pulses + equalization pulses
308 *
309 * vblank656: half lines after line 625/mid-313 of blanked video
310 * vblank: half lines, after line 5/317, of blanked video
311 * vactive: half lines of active video +
312 * 5 half lines after the end of active video
313 *
314 * As far as I can tell:
315 * vblank656 starts counting from the falling edge of the first
316 * vsync pulse (start of line 1 or mid-313)
317 * vblank starts counting from the after the 5 vsync pulses and
318 * 5 or 4 equalization pulses (start of line 6 or 318)
319 *
320 * For 625 line systems the driver will extract VBI information
321 * from lines 6-23 and lines 318-335 (but the slicer can only
322 * handle 17 lines, not the 18 in the vblank region).
323 * In addition, we need vblank656 and vblank to be one whole
324 * line longer, to cover line 24 and 336, so the SAV/EAV RP
325 * codes get generated such that the encoder can actually
326 * extract line 23 & 335 (WSS). We'll lose 1 line in each field
327 * at the top of the screen.
328 *
329 * It appears the 5 half lines that happen after active
330 * video must be included in vactive (579 instead of 574),
331 * otherwise the colors get badly displayed in various regions
332 * of the screen. I guess the chroma comb filter gets confused
333 * without them (at least when a PVR-350 is the PAL source).
334 */
335 vblank656 = 48; /* lines 1 - 24 & 313 - 336 */
336 vblank = 38; /* lines 6 - 24 & 318 - 336 */
337 vactive = 579; /* lines 24 - 313 & 337 - 626 */
338
339 /*
340 * For a 13.5 Mpps clock and 15,625 Hz line rate, a line is
341 * is 864 pixels = 720 active + 144 blanking. ITU-R BT.601
342 * specifies 12 luma clock periods or ~ 0.9 * 13.5 Mpps after
343 * the end of active video to start a horizontal line, so that
344 * leaves 132 pixels of hblank to ignore.
345 */
346 hblank = 132;
347 hactive = 720;
348
349 /*
350 * Burst gate delay (for 625 line systems)
351 * Hsync leading edge to color burst rise = 5.6 us
352 * Color burst width = 2.25 us
353 * Gate width = 4 pixel clocks
354 * (5.6 us + 2.25/2 us) * 13.5 Mpps + 4/2 clocks = 92.79 clocks
355 */
356 burst = 93;
357 luma_lpf = 2;
358 if (std & V4L2_STD_PAL) {
359 uv_lpf = 1;
360 comb = 0x20;
361 /* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
362 sc = 688700;
363 } else if (std == V4L2_STD_PAL_Nc) {
364 uv_lpf = 1;
365 comb = 0x20;
366 /* sc = 3582056.25 * src_decimation/28636360 * 2^13 */
367 sc = 556422;
368 } else { /* SECAM */
369 uv_lpf = 0;
370 comb = 0;
371 /* (fr + fb)/2 = (4406260 + 4250000)/2 = 4328130 */
372 /* sc = 4328130 * src_decimation/28636360 * 2^13 */
373 sc = 672314;
374 }
375 } else {
376 /*
377 * The following relationships of half line counts should hold:
378 * 525 = prevsync + vblank656 + vactive
379 * 12 = vblank656 - vblank = vsync pulses + equalization pulses
380 *
381 * prevsync: 6 half-lines before the vsync pulses
382 * vblank656: half lines, after line 3/mid-266, of blanked video
383 * vblank: half lines, after line 9/272, of blanked video
384 * vactive: half lines of active video
385 *
386 * As far as I can tell:
387 * vblank656 starts counting from the falling edge of the first
388 * vsync pulse (start of line 4 or mid-266)
389 * vblank starts counting from the after the 6 vsync pulses and
390 * 6 or 5 equalization pulses (start of line 10 or 272)
391 *
392 * For 525 line systems the driver will extract VBI information
393 * from lines 10-21 and lines 273-284.
394 */
395 vblank656 = 38; /* lines 4 - 22 & 266 - 284 */
396 vblank = 26; /* lines 10 - 22 & 272 - 284 */
397 vactive = 481; /* lines 23 - 263 & 285 - 525 */
398
399 /*
400 * For a 13.5 Mpps clock and 15,734.26 Hz line rate, a line is
401 * is 858 pixels = 720 active + 138 blanking. The Hsync leading
402 * edge should happen 1.2 us * 13.5 Mpps ~= 16 pixels after the
403 * end of active video, leaving 122 pixels of hblank to ignore
404 * before active video starts.
405 */
406 hactive = 720;
407 hblank = 122;
408 luma_lpf = 1;
409 uv_lpf = 1;
410
411 /*
412 * Burst gate delay (for 525 line systems)
413 * Hsync leading edge to color burst rise = 5.3 us
414 * Color burst width = 2.5 us
415 * Gate width = 4 pixel clocks
416 * (5.3 us + 2.5/2 us) * 13.5 Mpps + 4/2 clocks = 90.425 clocks
417 */
418 if (std == V4L2_STD_PAL_60) {
419 burst = 90;
420 luma_lpf = 2;
421 comb = 0x20;
422 /* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
423 sc = 688700;
424 } else if (std == V4L2_STD_PAL_M) {
425 /* The 97 needs to be verified against PAL-M timings */
426 burst = 97;
427 comb = 0x20;
428 /* sc = 3575611.49 * src_decimation/28636360 * 2^13 */
429 sc = 555421;
430 } else {
431 burst = 90;
432 comb = 0x66;
433 /* sc = 3579545.45.. * src_decimation/28636360 * 2^13 */
434 sc = 556032;
435 }
436 }
437
438 /* DEBUG: Displays configured PLL frequency */
439 pll_int = cx18_av_read(cx, 0x108);
440 pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
441 pll_post = cx18_av_read(cx, 0x109);
442 CX18_DEBUG_INFO_DEV(sd, "PLL regs = int: %u, frac: %u, post: %u\n",
443 pll_int, pll_frac, pll_post);
444
445 if (pll_post) {
446 int fsc, pll;
447 u64 tmp;
448
449 pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
450 pll /= pll_post;
451 CX18_DEBUG_INFO_DEV(sd, "Video PLL = %d.%06d MHz\n",
452 pll / 1000000, pll % 1000000);
453 CX18_DEBUG_INFO_DEV(sd, "Pixel rate = %d.%06d Mpixel/sec\n",
454 pll / 8000000, (pll / 8) % 1000000);
455
456 CX18_DEBUG_INFO_DEV(sd, "ADC XTAL/pixel clock decimation ratio "
457 "= %d.%03d\n", src_decimation / 256,
458 ((src_decimation % 256) * 1000) / 256);
459
460 tmp = 28636360 * (u64) sc;
461 do_div(tmp, src_decimation);
462 fsc = tmp >> 13;
463 CX18_DEBUG_INFO_DEV(sd,
464 "Chroma sub-carrier initial freq = %d.%06d "
465 "MHz\n", fsc / 1000000, fsc % 1000000);
466
467 CX18_DEBUG_INFO_DEV(sd, "hblank %i, hactive %i, vblank %i, "
468 "vactive %i, vblank656 %i, src_dec %i, "
469 "burst 0x%02x, luma_lpf %i, uv_lpf %i, "
470 "comb 0x%02x, sc 0x%06x\n",
471 hblank, hactive, vblank, vactive, vblank656,
472 src_decimation, burst, luma_lpf, uv_lpf,
473 comb, sc);
474 }
475
476 /* Sets horizontal blanking delay and active lines */
477 cx18_av_write(cx, 0x470, hblank);
478 cx18_av_write(cx, 0x471, 0xff & (((hblank >> 8) & 0x3) |
479 (hactive << 4)));
480 cx18_av_write(cx, 0x472, hactive >> 4);
481
482 /* Sets burst gate delay */
483 cx18_av_write(cx, 0x473, burst);
484
485 /* Sets vertical blanking delay and active duration */
486 cx18_av_write(cx, 0x474, vblank);
487 cx18_av_write(cx, 0x475, 0xff & (((vblank >> 8) & 0x3) |
488 (vactive << 4)));
489 cx18_av_write(cx, 0x476, vactive >> 4);
490 cx18_av_write(cx, 0x477, vblank656);
491
492 /* Sets src decimation rate */
493 cx18_av_write(cx, 0x478, 0xff & src_decimation);
494 cx18_av_write(cx, 0x479, 0xff & (src_decimation >> 8));
495
496 /* Sets Luma and UV Low pass filters */
497 cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
498
499 /* Enables comb filters */
500 cx18_av_write(cx, 0x47b, comb);
501
502 /* Sets SC Step*/
503 cx18_av_write(cx, 0x47c, sc);
504 cx18_av_write(cx, 0x47d, 0xff & sc >> 8);
505 cx18_av_write(cx, 0x47e, 0xff & sc >> 16);
506
507 if (std & V4L2_STD_625_50) {
508 state->slicer_line_delay = 1;
509 state->slicer_line_offset = (6 + state->slicer_line_delay - 2);
510 } else {
511 state->slicer_line_delay = 0;
512 state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
513 }
514 cx18_av_write(cx, 0x47f, state->slicer_line_delay);
515 }
516
517 static void input_change(struct cx18 *cx)
518 {
519 struct cx18_av_state *state = &cx->av_state;
520 v4l2_std_id std = state->std;
521 u8 v;
522
523 /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */
524 cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
525 cx18_av_and_or(cx, 0x401, ~0x60, 0);
526 cx18_av_and_or(cx, 0x401, ~0x60, 0x60);
527
528 if (std & V4L2_STD_525_60) {
529 if (std == V4L2_STD_NTSC_M_JP) {
530 /* Japan uses EIAJ audio standard */
531 cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff);
532 cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f);
533 } else if (std == V4L2_STD_NTSC_M_KR) {
534 /* South Korea uses A2 audio standard */
535 cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff);
536 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
537 } else {
538 /* Others use the BTSC audio standard */
539 cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff);
540 cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f);
541 }
542 } else if (std & V4L2_STD_PAL) {
543 /* Follow tuner change procedure for PAL */
544 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
545 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
546 } else if (std & V4L2_STD_SECAM) {
547 /* Select autodetect for SECAM */
548 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
549 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
550 }
551
552 v = cx18_av_read(cx, 0x803);
553 if (v & 0x10) {
554 /* restart audio decoder microcontroller */
555 v &= ~0x10;
556 cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
557 v |= 0x10;
558 cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
559 }
560 }
561
562 static int cx18_av_s_frequency(struct v4l2_subdev *sd,
563 struct v4l2_frequency *freq)
564 {
565 struct cx18 *cx = v4l2_get_subdevdata(sd);
566 input_change(cx);
567 return 0;
568 }
569
570 static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
571 enum cx18_av_audio_input aud_input)
572 {
573 struct cx18_av_state *state = &cx->av_state;
574 struct v4l2_subdev *sd = &state->sd;
575
576 enum analog_signal_type {
577 NONE, CVBS, Y, C, SIF, Pb, Pr
578 } ch[3] = {NONE, NONE, NONE};
579
580 u8 afe_mux_cfg;
581 u8 adc2_cfg;
582 u32 afe_cfg;
583 int i;
584
585 CX18_DEBUG_INFO_DEV(sd, "decoder set video input %d, audio input %d\n",
586 vid_input, aud_input);
587
588 if (vid_input >= CX18_AV_COMPOSITE1 &&
589 vid_input <= CX18_AV_COMPOSITE8) {
590 afe_mux_cfg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1);
591 ch[0] = CVBS;
592 } else {
593 int luma = vid_input & 0xf0;
594 int chroma = vid_input & 0xf00;
595
596 if ((vid_input & ~0xff0) ||
597 luma < CX18_AV_SVIDEO_LUMA1 ||
598 luma > CX18_AV_SVIDEO_LUMA8 ||
599 chroma < CX18_AV_SVIDEO_CHROMA4 ||
600 chroma > CX18_AV_SVIDEO_CHROMA8) {
601 CX18_ERR_DEV(sd, "0x%04x is not a valid video input!\n",
602 vid_input);
603 return -EINVAL;
604 }
605 afe_mux_cfg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4);
606 ch[0] = Y;
607 if (chroma >= CX18_AV_SVIDEO_CHROMA7) {
608 afe_mux_cfg &= 0x3f;
609 afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2;
610 ch[2] = C;
611 } else {
612 afe_mux_cfg &= 0xcf;
613 afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4;
614 ch[1] = C;
615 }
616 }
617 /* TODO: LeadTek WinFast DVR3100 H & WinFast PVR2100 can do Y/Pb/Pr */
618
619 switch (aud_input) {
620 case CX18_AV_AUDIO_SERIAL1:
621 case CX18_AV_AUDIO_SERIAL2:
622 /* do nothing, use serial audio input */
623 break;
624 case CX18_AV_AUDIO4:
625 afe_mux_cfg &= ~0x30;
626 ch[1] = SIF;
627 break;
628 case CX18_AV_AUDIO5:
629 afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x10;
630 ch[1] = SIF;
631 break;
632 case CX18_AV_AUDIO6:
633 afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x20;
634 ch[1] = SIF;
635 break;
636 case CX18_AV_AUDIO7:
637 afe_mux_cfg &= ~0xc0;
638 ch[2] = SIF;
639 break;
640 case CX18_AV_AUDIO8:
641 afe_mux_cfg = (afe_mux_cfg & ~0xc0) | 0x40;
642 ch[2] = SIF;
643 break;
644
645 default:
646 CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n",
647 aud_input);
648 return -EINVAL;
649 }
650
651 /* Set up analog front end multiplexers */
652 cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7);
653 /* Set INPUT_MODE to Composite (0) or S-Video (1) */
654 cx18_av_and_or(cx, 0x401, ~0x6, ch[0] == CVBS ? 0 : 0x02);
655
656 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
657 adc2_cfg = cx18_av_read(cx, 0x102);
658 if (ch[2] == NONE)
659 adc2_cfg &= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */
660 else
661 adc2_cfg |= 0x2; /* Signal on CH3, set ADC2 to CH3 for input */
662
663 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */
664 if (ch[1] != NONE && ch[2] != NONE)
665 adc2_cfg |= 0x4; /* Set dual mode */
666 else
667 adc2_cfg &= ~0x4; /* Clear dual mode */
668 cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17);
669
670 /* Configure the analog front end */
671 afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL);
672 afe_cfg &= 0xff000000;
673 afe_cfg |= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */
674 if (ch[1] != NONE && ch[2] != NONE)
675 afe_cfg |= 0x00000030; /* half_bw_ch[2-3] since in dual mode */
676
677 for (i = 0; i < 3; i++) {
678 switch (ch[i]) {
679 default:
680 case NONE:
681 /* CLAMP_SEL = Fixed to midcode clamp level */
682 afe_cfg |= (0x00000200 << i);
683 break;
684 case CVBS:
685 case Y:
686 if (i > 0)
687 afe_cfg |= 0x00002000; /* LUMA_IN_SEL: ADC2 */
688 break;
689 case C:
690 case Pb:
691 case Pr:
692 /* CLAMP_SEL = Fixed to midcode clamp level */
693 afe_cfg |= (0x00000200 << i);
694 if (i == 0 && ch[i] == C)
695 afe_cfg &= ~0x00001000; /* CHROMA_IN_SEL ADC1 */
696 break;
697 case SIF:
698 /*
699 * VGA_GAIN_SEL = Audio Decoder
700 * CLAMP_SEL = Fixed to midcode clamp level
701 */
702 afe_cfg |= (0x00000240 << i);
703 if (i == 0)
704 afe_cfg &= ~0x00004000; /* AUD_IN_SEL ADC1 */
705 break;
706 }
707 }
708
709 cx18_av_write4(cx, CXADEC_AFE_CTRL, afe_cfg);
710
711 state->vid_input = vid_input;
712 state->aud_input = aud_input;
713 cx18_av_audio_set_path(cx);
714 input_change(cx);
715 return 0;
716 }
717
718 static int cx18_av_s_video_routing(struct v4l2_subdev *sd,
719 u32 input, u32 output, u32 config)
720 {
721 struct cx18_av_state *state = to_cx18_av_state(sd);
722 struct cx18 *cx = v4l2_get_subdevdata(sd);
723 return set_input(cx, input, state->aud_input);
724 }
725
726 static int cx18_av_s_audio_routing(struct v4l2_subdev *sd,
727 u32 input, u32 output, u32 config)
728 {
729 struct cx18_av_state *state = to_cx18_av_state(sd);
730 struct cx18 *cx = v4l2_get_subdevdata(sd);
731 return set_input(cx, state->vid_input, input);
732 }
733
734 static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
735 {
736 struct cx18_av_state *state = to_cx18_av_state(sd);
737 struct cx18 *cx = v4l2_get_subdevdata(sd);
738 u8 vpres;
739 u8 mode;
740 int val = 0;
741
742 if (state->radio)
743 return 0;
744
745 vpres = cx18_av_read(cx, 0x40e) & 0x20;
746 vt->signal = vpres ? 0xffff : 0x0;
747
748 vt->capability |=
749 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
750 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
751
752 mode = cx18_av_read(cx, 0x804);
753
754 /* get rxsubchans and audmode */
755 if ((mode & 0xf) == 1)
756 val |= V4L2_TUNER_SUB_STEREO;
757 else
758 val |= V4L2_TUNER_SUB_MONO;
759
760 if (mode == 2 || mode == 4)
761 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
762
763 if (mode & 0x10)
764 val |= V4L2_TUNER_SUB_SAP;
765
766 vt->rxsubchans = val;
767 vt->audmode = state->audmode;
768 return 0;
769 }
770
771 static int cx18_av_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
772 {
773 struct cx18_av_state *state = to_cx18_av_state(sd);
774 struct cx18 *cx = v4l2_get_subdevdata(sd);
775 u8 v;
776
777 if (state->radio)
778 return 0;
779
780 v = cx18_av_read(cx, 0x809);
781 v &= ~0xf;
782
783 switch (vt->audmode) {
784 case V4L2_TUNER_MODE_MONO:
785 /* mono -> mono
786 stereo -> mono
787 bilingual -> lang1 */
788 break;
789 case V4L2_TUNER_MODE_STEREO:
790 case V4L2_TUNER_MODE_LANG1:
791 /* mono -> mono
792 stereo -> stereo
793 bilingual -> lang1 */
794 v |= 0x4;
795 break;
796 case V4L2_TUNER_MODE_LANG1_LANG2:
797 /* mono -> mono
798 stereo -> stereo
799 bilingual -> lang1/lang2 */
800 v |= 0x7;
801 break;
802 case V4L2_TUNER_MODE_LANG2:
803 /* mono -> mono
804 stereo -> stereo
805 bilingual -> lang2 */
806 v |= 0x1;
807 break;
808 default:
809 return -EINVAL;
810 }
811 cx18_av_write_expect(cx, 0x809, v, v, 0xff);
812 state->audmode = vt->audmode;
813 return 0;
814 }
815
816 static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
817 {
818 struct cx18_av_state *state = to_cx18_av_state(sd);
819 struct cx18 *cx = v4l2_get_subdevdata(sd);
820
821 u8 fmt = 0; /* zero is autodetect */
822 u8 pal_m = 0;
823
824 if (state->radio == 0 && state->std == norm)
825 return 0;
826
827 state->radio = 0;
828 state->std = norm;
829
830 /* First tests should be against specific std */
831 if (state->std == V4L2_STD_NTSC_M_JP) {
832 fmt = 0x2;
833 } else if (state->std == V4L2_STD_NTSC_443) {
834 fmt = 0x3;
835 } else if (state->std == V4L2_STD_PAL_M) {
836 pal_m = 1;
837 fmt = 0x5;
838 } else if (state->std == V4L2_STD_PAL_N) {
839 fmt = 0x6;
840 } else if (state->std == V4L2_STD_PAL_Nc) {
841 fmt = 0x7;
842 } else if (state->std == V4L2_STD_PAL_60) {
843 fmt = 0x8;
844 } else {
845 /* Then, test against generic ones */
846 if (state->std & V4L2_STD_NTSC)
847 fmt = 0x1;
848 else if (state->std & V4L2_STD_PAL)
849 fmt = 0x4;
850 else if (state->std & V4L2_STD_SECAM)
851 fmt = 0xc;
852 }
853
854 CX18_DEBUG_INFO_DEV(sd, "changing video std to fmt %i\n", fmt);
855
856 /* Follow step 9 of section 3.16 in the cx18_av datasheet.
857 Without this PAL may display a vertical ghosting effect.
858 This happens for example with the Yuan MPC622. */
859 if (fmt >= 4 && fmt < 8) {
860 /* Set format to NTSC-M */
861 cx18_av_and_or(cx, 0x400, ~0xf, 1);
862 /* Turn off LCOMB */
863 cx18_av_and_or(cx, 0x47b, ~6, 0);
864 }
865 cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20);
866 cx18_av_and_or(cx, 0x403, ~0x3, pal_m);
867 cx18_av_std_setup(cx);
868 input_change(cx);
869 return 0;
870 }
871
872 static int cx18_av_s_radio(struct v4l2_subdev *sd)
873 {
874 struct cx18_av_state *state = to_cx18_av_state(sd);
875 state->radio = 1;
876 return 0;
877 }
878
879 static int cx18_av_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
880 {
881 struct cx18 *cx = v4l2_get_subdevdata(sd);
882
883 switch (ctrl->id) {
884 case V4L2_CID_BRIGHTNESS:
885 if (ctrl->value < 0 || ctrl->value > 255) {
886 CX18_ERR_DEV(sd, "invalid brightness setting %d\n",
887 ctrl->value);
888 return -ERANGE;
889 }
890
891 cx18_av_write(cx, 0x414, ctrl->value - 128);
892 break;
893
894 case V4L2_CID_CONTRAST:
895 if (ctrl->value < 0 || ctrl->value > 127) {
896 CX18_ERR_DEV(sd, "invalid contrast setting %d\n",
897 ctrl->value);
898 return -ERANGE;
899 }
900
901 cx18_av_write(cx, 0x415, ctrl->value << 1);
902 break;
903
904 case V4L2_CID_SATURATION:
905 if (ctrl->value < 0 || ctrl->value > 127) {
906 CX18_ERR_DEV(sd, "invalid saturation setting %d\n",
907 ctrl->value);
908 return -ERANGE;
909 }
910
911 cx18_av_write(cx, 0x420, ctrl->value << 1);
912 cx18_av_write(cx, 0x421, ctrl->value << 1);
913 break;
914
915 case V4L2_CID_HUE:
916 if (ctrl->value < -128 || ctrl->value > 127) {
917 CX18_ERR_DEV(sd, "invalid hue setting %d\n",
918 ctrl->value);
919 return -ERANGE;
920 }
921
922 cx18_av_write(cx, 0x422, ctrl->value);
923 break;
924
925 case V4L2_CID_AUDIO_VOLUME:
926 case V4L2_CID_AUDIO_BASS:
927 case V4L2_CID_AUDIO_TREBLE:
928 case V4L2_CID_AUDIO_BALANCE:
929 case V4L2_CID_AUDIO_MUTE:
930 return cx18_av_audio_s_ctrl(cx, ctrl);
931
932 default:
933 return -EINVAL;
934 }
935 return 0;
936 }
937
938 static int cx18_av_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
939 {
940 struct cx18 *cx = v4l2_get_subdevdata(sd);
941
942 switch (ctrl->id) {
943 case V4L2_CID_BRIGHTNESS:
944 ctrl->value = (s8)cx18_av_read(cx, 0x414) + 128;
945 break;
946 case V4L2_CID_CONTRAST:
947 ctrl->value = cx18_av_read(cx, 0x415) >> 1;
948 break;
949 case V4L2_CID_SATURATION:
950 ctrl->value = cx18_av_read(cx, 0x420) >> 1;
951 break;
952 case V4L2_CID_HUE:
953 ctrl->value = (s8)cx18_av_read(cx, 0x422);
954 break;
955 case V4L2_CID_AUDIO_VOLUME:
956 case V4L2_CID_AUDIO_BASS:
957 case V4L2_CID_AUDIO_TREBLE:
958 case V4L2_CID_AUDIO_BALANCE:
959 case V4L2_CID_AUDIO_MUTE:
960 return cx18_av_audio_g_ctrl(cx, ctrl);
961 default:
962 return -EINVAL;
963 }
964 return 0;
965 }
966
967 static int cx18_av_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
968 {
969 struct cx18_av_state *state = to_cx18_av_state(sd);
970
971 switch (qc->id) {
972 case V4L2_CID_BRIGHTNESS:
973 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
974 case V4L2_CID_CONTRAST:
975 case V4L2_CID_SATURATION:
976 return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64);
977 case V4L2_CID_HUE:
978 return v4l2_ctrl_query_fill(qc, -128, 127, 1, 0);
979 default:
980 break;
981 }
982
983 switch (qc->id) {
984 case V4L2_CID_AUDIO_VOLUME:
985 return v4l2_ctrl_query_fill(qc, 0, 65535,
986 65535 / 100, state->default_volume);
987 case V4L2_CID_AUDIO_MUTE:
988 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
989 case V4L2_CID_AUDIO_BALANCE:
990 case V4L2_CID_AUDIO_BASS:
991 case V4L2_CID_AUDIO_TREBLE:
992 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
993 default:
994 return -EINVAL;
995 }
996 return -EINVAL;
997 }
998
999 static int cx18_av_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
1000 {
1001 struct cx18 *cx = v4l2_get_subdevdata(sd);
1002
1003 return cx18_av_vbi_g_fmt(cx, fmt);
1004 }
1005
1006 static int cx18_av_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
1007 {
1008 struct cx18_av_state *state = to_cx18_av_state(sd);
1009 struct cx18 *cx = v4l2_get_subdevdata(sd);
1010
1011 struct v4l2_pix_format *pix;
1012 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
1013 int is_50Hz = !(state->std & V4L2_STD_525_60);
1014
1015 switch (fmt->type) {
1016 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
1017 pix = &(fmt->fmt.pix);
1018
1019 Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4;
1020 Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4;
1021
1022 Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4;
1023 Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4;
1024
1025 /*
1026 * This adjustment reflects the excess of vactive, set in
1027 * cx18_av_std_setup(), above standard values:
1028 *
1029 * 480 + 1 for 60 Hz systems
1030 * 576 + 3 for 50 Hz systems
1031 */
1032 Vlines = pix->height + (is_50Hz ? 3 : 1);
1033
1034 /*
1035 * Invalid height and width scaling requests are:
1036 * 1. width less than 1/16 of the source width
1037 * 2. width greater than the source width
1038 * 3. height less than 1/8 of the source height
1039 * 4. height greater than the source height
1040 */
1041 if ((pix->width * 16 < Hsrc) || (Hsrc < pix->width) ||
1042 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
1043 CX18_ERR_DEV(sd, "%dx%d is not a valid size!\n",
1044 pix->width, pix->height);
1045 return -ERANGE;
1046 }
1047
1048 HSC = (Hsrc * (1 << 20)) / pix->width - (1 << 20);
1049 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
1050 VSC &= 0x1fff;
1051
1052 if (pix->width >= 385)
1053 filter = 0;
1054 else if (pix->width > 192)
1055 filter = 1;
1056 else if (pix->width > 96)
1057 filter = 2;
1058 else
1059 filter = 3;
1060
1061 CX18_DEBUG_INFO_DEV(sd,
1062 "decoder set size %dx%d -> scale %ux%u\n",
1063 pix->width, pix->height, HSC, VSC);
1064
1065 /* HSCALE=HSC */
1066 cx18_av_write(cx, 0x418, HSC & 0xff);
1067 cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff);
1068 cx18_av_write(cx, 0x41a, HSC >> 16);
1069 /* VSCALE=VSC */
1070 cx18_av_write(cx, 0x41c, VSC & 0xff);
1071 cx18_av_write(cx, 0x41d, VSC >> 8);
1072 /* VS_INTRLACE=1 VFILT=filter */
1073 cx18_av_write(cx, 0x41e, 0x8 | filter);
1074 break;
1075
1076 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
1077 return cx18_av_vbi_s_fmt(cx, fmt);
1078
1079 case V4L2_BUF_TYPE_VBI_CAPTURE:
1080 return cx18_av_vbi_s_fmt(cx, fmt);
1081
1082 default:
1083 return -EINVAL;
1084 }
1085 return 0;
1086 }
1087
1088 static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable)
1089 {
1090 struct cx18 *cx = v4l2_get_subdevdata(sd);
1091
1092 CX18_DEBUG_INFO_DEV(sd, "%s output\n", enable ? "enable" : "disable");
1093 if (enable) {
1094 cx18_av_write(cx, 0x115, 0x8c);
1095 cx18_av_write(cx, 0x116, 0x07);
1096 } else {
1097 cx18_av_write(cx, 0x115, 0x00);
1098 cx18_av_write(cx, 0x116, 0x00);
1099 }
1100 return 0;
1101 }
1102
1103 static void log_video_status(struct cx18 *cx)
1104 {
1105 static const char *const fmt_strs[] = {
1106 "0x0",
1107 "NTSC-M", "NTSC-J", "NTSC-4.43",
1108 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1109 "0x9", "0xA", "0xB",
1110 "SECAM",
1111 "0xD", "0xE", "0xF"
1112 };
1113
1114 struct cx18_av_state *state = &cx->av_state;
1115 struct v4l2_subdev *sd = &state->sd;
1116 u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf;
1117 u8 gen_stat1 = cx18_av_read(cx, 0x40d);
1118 u8 gen_stat2 = cx18_av_read(cx, 0x40e);
1119 int vid_input = state->vid_input;
1120
1121 CX18_INFO_DEV(sd, "Video signal: %spresent\n",
1122 (gen_stat2 & 0x20) ? "" : "not ");
1123 CX18_INFO_DEV(sd, "Detected format: %s\n",
1124 fmt_strs[gen_stat1 & 0xf]);
1125
1126 CX18_INFO_DEV(sd, "Specified standard: %s\n",
1127 vidfmt_sel ? fmt_strs[vidfmt_sel]
1128 : "automatic detection");
1129
1130 if (vid_input >= CX18_AV_COMPOSITE1 &&
1131 vid_input <= CX18_AV_COMPOSITE8) {
1132 CX18_INFO_DEV(sd, "Specified video input: Composite %d\n",
1133 vid_input - CX18_AV_COMPOSITE1 + 1);
1134 } else {
1135 CX18_INFO_DEV(sd, "Specified video input: "
1136 "S-Video (Luma In%d, Chroma In%d)\n",
1137 (vid_input & 0xf0) >> 4,
1138 (vid_input & 0xf00) >> 8);
1139 }
1140
1141 CX18_INFO_DEV(sd, "Specified audioclock freq: %d Hz\n",
1142 state->audclk_freq);
1143 }
1144
1145 static void log_audio_status(struct cx18 *cx)
1146 {
1147 struct cx18_av_state *state = &cx->av_state;
1148 struct v4l2_subdev *sd = &state->sd;
1149 u8 download_ctl = cx18_av_read(cx, 0x803);
1150 u8 mod_det_stat0 = cx18_av_read(cx, 0x804);
1151 u8 mod_det_stat1 = cx18_av_read(cx, 0x805);
1152 u8 audio_config = cx18_av_read(cx, 0x808);
1153 u8 pref_mode = cx18_av_read(cx, 0x809);
1154 u8 afc0 = cx18_av_read(cx, 0x80b);
1155 u8 mute_ctl = cx18_av_read(cx, 0x8d3);
1156 int aud_input = state->aud_input;
1157 char *p;
1158
1159 switch (mod_det_stat0) {
1160 case 0x00: p = "mono"; break;
1161 case 0x01: p = "stereo"; break;
1162 case 0x02: p = "dual"; break;
1163 case 0x04: p = "tri"; break;
1164 case 0x10: p = "mono with SAP"; break;
1165 case 0x11: p = "stereo with SAP"; break;
1166 case 0x12: p = "dual with SAP"; break;
1167 case 0x14: p = "tri with SAP"; break;
1168 case 0xfe: p = "forced mode"; break;
1169 default: p = "not defined"; break;
1170 }
1171 CX18_INFO_DEV(sd, "Detected audio mode: %s\n", p);
1172
1173 switch (mod_det_stat1) {
1174 case 0x00: p = "not defined"; break;
1175 case 0x01: p = "EIAJ"; break;
1176 case 0x02: p = "A2-M"; break;
1177 case 0x03: p = "A2-BG"; break;
1178 case 0x04: p = "A2-DK1"; break;
1179 case 0x05: p = "A2-DK2"; break;
1180 case 0x06: p = "A2-DK3"; break;
1181 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1182 case 0x08: p = "AM-L"; break;
1183 case 0x09: p = "NICAM-BG"; break;
1184 case 0x0a: p = "NICAM-DK"; break;
1185 case 0x0b: p = "NICAM-I"; break;
1186 case 0x0c: p = "NICAM-L"; break;
1187 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1188 case 0x0e: p = "IF FM Radio"; break;
1189 case 0x0f: p = "BTSC"; break;
1190 case 0x10: p = "detected chrominance"; break;
1191 case 0xfd: p = "unknown audio standard"; break;
1192 case 0xfe: p = "forced audio standard"; break;
1193 case 0xff: p = "no detected audio standard"; break;
1194 default: p = "not defined"; break;
1195 }
1196 CX18_INFO_DEV(sd, "Detected audio standard: %s\n", p);
1197 CX18_INFO_DEV(sd, "Audio muted: %s\n",
1198 (mute_ctl & 0x2) ? "yes" : "no");
1199 CX18_INFO_DEV(sd, "Audio microcontroller: %s\n",
1200 (download_ctl & 0x10) ? "running" : "stopped");
1201
1202 switch (audio_config >> 4) {
1203 case 0x00: p = "undefined"; break;
1204 case 0x01: p = "BTSC"; break;
1205 case 0x02: p = "EIAJ"; break;
1206 case 0x03: p = "A2-M"; break;
1207 case 0x04: p = "A2-BG"; break;
1208 case 0x05: p = "A2-DK1"; break;
1209 case 0x06: p = "A2-DK2"; break;
1210 case 0x07: p = "A2-DK3"; break;
1211 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1212 case 0x09: p = "AM-L"; break;
1213 case 0x0a: p = "NICAM-BG"; break;
1214 case 0x0b: p = "NICAM-DK"; break;
1215 case 0x0c: p = "NICAM-I"; break;
1216 case 0x0d: p = "NICAM-L"; break;
1217 case 0x0e: p = "FM radio"; break;
1218 case 0x0f: p = "automatic detection"; break;
1219 default: p = "undefined"; break;
1220 }
1221 CX18_INFO_DEV(sd, "Configured audio standard: %s\n", p);
1222
1223 if ((audio_config >> 4) < 0xF) {
1224 switch (audio_config & 0xF) {
1225 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1226 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1227 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1228 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1229 case 0x04: p = "STEREO"; break;
1230 case 0x05: p = "DUAL1 (AC)"; break;
1231 case 0x06: p = "DUAL2 (BC)"; break;
1232 case 0x07: p = "DUAL3 (AB)"; break;
1233 default: p = "undefined";
1234 }
1235 CX18_INFO_DEV(sd, "Configured audio mode: %s\n", p);
1236 } else {
1237 switch (audio_config & 0xF) {
1238 case 0x00: p = "BG"; break;
1239 case 0x01: p = "DK1"; break;
1240 case 0x02: p = "DK2"; break;
1241 case 0x03: p = "DK3"; break;
1242 case 0x04: p = "I"; break;
1243 case 0x05: p = "L"; break;
1244 case 0x06: p = "BTSC"; break;
1245 case 0x07: p = "EIAJ"; break;
1246 case 0x08: p = "A2-M"; break;
1247 case 0x09: p = "FM Radio (4.5 MHz)"; break;
1248 case 0x0a: p = "FM Radio (5.5 MHz)"; break;
1249 case 0x0b: p = "S-Video"; break;
1250 case 0x0f: p = "automatic standard and mode detection"; break;
1251 default: p = "undefined"; break;
1252 }
1253 CX18_INFO_DEV(sd, "Configured audio system: %s\n", p);
1254 }
1255
1256 if (aud_input)
1257 CX18_INFO_DEV(sd, "Specified audio input: Tuner (In%d)\n",
1258 aud_input);
1259 else
1260 CX18_INFO_DEV(sd, "Specified audio input: External\n");
1261
1262 switch (pref_mode & 0xf) {
1263 case 0: p = "mono/language A"; break;
1264 case 1: p = "language B"; break;
1265 case 2: p = "language C"; break;
1266 case 3: p = "analog fallback"; break;
1267 case 4: p = "stereo"; break;
1268 case 5: p = "language AC"; break;
1269 case 6: p = "language BC"; break;
1270 case 7: p = "language AB"; break;
1271 default: p = "undefined"; break;
1272 }
1273 CX18_INFO_DEV(sd, "Preferred audio mode: %s\n", p);
1274
1275 if ((audio_config & 0xf) == 0xf) {
1276 switch ((afc0 >> 3) & 0x1) {
1277 case 0: p = "system DK"; break;
1278 case 1: p = "system L"; break;
1279 }
1280 CX18_INFO_DEV(sd, "Selected 65 MHz format: %s\n", p);
1281
1282 switch (afc0 & 0x7) {
1283 case 0: p = "Chroma"; break;
1284 case 1: p = "BTSC"; break;
1285 case 2: p = "EIAJ"; break;
1286 case 3: p = "A2-M"; break;
1287 case 4: p = "autodetect"; break;
1288 default: p = "undefined"; break;
1289 }
1290 CX18_INFO_DEV(sd, "Selected 45 MHz format: %s\n", p);
1291 }
1292 }
1293
1294 static int cx18_av_log_status(struct v4l2_subdev *sd)
1295 {
1296 struct cx18 *cx = v4l2_get_subdevdata(sd);
1297 log_video_status(cx);
1298 log_audio_status(cx);
1299 return 0;
1300 }
1301
1302 static inline int cx18_av_dbg_match(const struct v4l2_dbg_match *match)
1303 {
1304 return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 1;
1305 }
1306
1307 static int cx18_av_g_chip_ident(struct v4l2_subdev *sd,
1308 struct v4l2_dbg_chip_ident *chip)
1309 {
1310 struct cx18_av_state *state = to_cx18_av_state(sd);
1311
1312 if (cx18_av_dbg_match(&chip->match)) {
1313 chip->ident = state->id;
1314 chip->revision = state->rev;
1315 }
1316 return 0;
1317 }
1318
1319 #ifdef CONFIG_VIDEO_ADV_DEBUG
1320 static int cx18_av_g_register(struct v4l2_subdev *sd,
1321 struct v4l2_dbg_register *reg)
1322 {
1323 struct cx18 *cx = v4l2_get_subdevdata(sd);
1324
1325 if (!cx18_av_dbg_match(&reg->match))
1326 return -EINVAL;
1327 if ((reg->reg & 0x3) != 0)
1328 return -EINVAL;
1329 if (!capable(CAP_SYS_ADMIN))
1330 return -EPERM;
1331 reg->size = 4;
1332 reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc);
1333 return 0;
1334 }
1335
1336 static int cx18_av_s_register(struct v4l2_subdev *sd,
1337 struct v4l2_dbg_register *reg)
1338 {
1339 struct cx18 *cx = v4l2_get_subdevdata(sd);
1340
1341 if (!cx18_av_dbg_match(&reg->match))
1342 return -EINVAL;
1343 if ((reg->reg & 0x3) != 0)
1344 return -EINVAL;
1345 if (!capable(CAP_SYS_ADMIN))
1346 return -EPERM;
1347 cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val);
1348 return 0;
1349 }
1350 #endif
1351
1352 static const struct v4l2_subdev_core_ops cx18_av_general_ops = {
1353 .g_chip_ident = cx18_av_g_chip_ident,
1354 .log_status = cx18_av_log_status,
1355 .load_fw = cx18_av_load_fw,
1356 .reset = cx18_av_reset,
1357 .queryctrl = cx18_av_queryctrl,
1358 .g_ctrl = cx18_av_g_ctrl,
1359 .s_ctrl = cx18_av_s_ctrl,
1360 .s_std = cx18_av_s_std,
1361 #ifdef CONFIG_VIDEO_ADV_DEBUG
1362 .g_register = cx18_av_g_register,
1363 .s_register = cx18_av_s_register,
1364 #endif
1365 };
1366
1367 static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = {
1368 .s_radio = cx18_av_s_radio,
1369 .s_frequency = cx18_av_s_frequency,
1370 .g_tuner = cx18_av_g_tuner,
1371 .s_tuner = cx18_av_s_tuner,
1372 };
1373
1374 static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = {
1375 .s_clock_freq = cx18_av_s_clock_freq,
1376 .s_routing = cx18_av_s_audio_routing,
1377 };
1378
1379 static const struct v4l2_subdev_video_ops cx18_av_video_ops = {
1380 .s_routing = cx18_av_s_video_routing,
1381 .decode_vbi_line = cx18_av_decode_vbi_line,
1382 .s_stream = cx18_av_s_stream,
1383 .g_fmt = cx18_av_g_fmt,
1384 .s_fmt = cx18_av_s_fmt,
1385 };
1386
1387 static const struct v4l2_subdev_ops cx18_av_ops = {
1388 .core = &cx18_av_general_ops,
1389 .tuner = &cx18_av_tuner_ops,
1390 .audio = &cx18_av_audio_ops,
1391 .video = &cx18_av_video_ops,
1392 };
1393
1394 int cx18_av_probe(struct cx18 *cx)
1395 {
1396 struct cx18_av_state *state = &cx->av_state;
1397 struct v4l2_subdev *sd;
1398 int err;
1399
1400 state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff;
1401 state->id = ((state->rev >> 4) == CXADEC_CHIP_TYPE_MAKO)
1402 ? V4L2_IDENT_CX23418_843 : V4L2_IDENT_UNKNOWN;
1403
1404 state->vid_input = CX18_AV_COMPOSITE7;
1405 state->aud_input = CX18_AV_AUDIO8;
1406 state->audclk_freq = 48000;
1407 state->audmode = V4L2_TUNER_MODE_LANG1;
1408 state->slicer_line_delay = 0;
1409 state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
1410
1411 sd = &state->sd;
1412 v4l2_subdev_init(sd, &cx18_av_ops);
1413 v4l2_set_subdevdata(sd, cx);
1414 snprintf(sd->name, sizeof(sd->name),
1415 "%s %03x", cx->v4l2_dev.name, (state->rev >> 4));
1416 sd->grp_id = CX18_HW_418_AV;
1417 err = v4l2_device_register_subdev(&cx->v4l2_dev, sd);
1418 if (!err)
1419 cx18_av_init(cx);
1420 return err;
1421 }