4 * Derived from cx25840-core.h
6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
7 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 #ifndef _CX18_AV_CORE_H_
26 #define _CX18_AV_CORE_H_
28 #include <media/v4l2-device.h>
32 enum cx18_av_video_input
{
33 /* Composite video inputs In1-In8 */
34 CX18_AV_COMPOSITE1
= 1,
43 /* S-Video inputs consist of one luma input (In1-In8) ORed with one
44 chroma input (In5-In8) */
45 CX18_AV_SVIDEO_LUMA1
= 0x10,
46 CX18_AV_SVIDEO_LUMA2
= 0x20,
47 CX18_AV_SVIDEO_LUMA3
= 0x30,
48 CX18_AV_SVIDEO_LUMA4
= 0x40,
49 CX18_AV_SVIDEO_LUMA5
= 0x50,
50 CX18_AV_SVIDEO_LUMA6
= 0x60,
51 CX18_AV_SVIDEO_LUMA7
= 0x70,
52 CX18_AV_SVIDEO_LUMA8
= 0x80,
53 CX18_AV_SVIDEO_CHROMA4
= 0x400,
54 CX18_AV_SVIDEO_CHROMA5
= 0x500,
55 CX18_AV_SVIDEO_CHROMA6
= 0x600,
56 CX18_AV_SVIDEO_CHROMA7
= 0x700,
57 CX18_AV_SVIDEO_CHROMA8
= 0x800,
59 /* S-Video aliases for common luma/chroma combinations */
60 CX18_AV_SVIDEO1
= 0x510,
61 CX18_AV_SVIDEO2
= 0x620,
62 CX18_AV_SVIDEO3
= 0x730,
63 CX18_AV_SVIDEO4
= 0x840,
66 enum cx18_av_audio_input
{
67 /* Audio inputs: serial or In4-In8 */
68 CX18_AV_AUDIO_SERIAL1
,
69 CX18_AV_AUDIO_SERIAL2
,
77 struct cx18_av_state
{
78 struct v4l2_subdev sd
;
81 enum cx18_av_video_input vid_input
;
82 enum cx18_av_audio_input aud_input
;
91 * The VBI slicer starts operating and counting lines, begining at
92 * slicer line count of 1, at D lines after the deassertion of VRESET.
93 * This staring field line, S, is 6 (& 319) or 10 (& 273) for 625 or 525
94 * line systems respectively. Sliced ancillary data captured on VBI
95 * slicer line M is inserted after the VBI slicer is done with line M,
96 * when VBI slicer line count is N = M+1. Thus when the VBI slicer
97 * reports a VBI slicer line number with ancillary data, the IDID0 byte
98 * indicates VBI slicer line N. The actual field line that the captured
101 * L = M+(S+D-1) = N-1+(S+D-1) = N + (S+D-2).
103 * L is the line in the field, not frame, from which the VBI data came.
104 * N is the line reported by the slicer in the ancillary data.
105 * D is the slicer_line_delay value programmed into register 0x47f.
106 * S is 6 for 625 line systems or 10 for 525 line systems
107 * (S+D-2) is the slicer_line_offset used to convert slicer reported
108 * line counts to actual field lines.
110 int slicer_line_delay
;
111 int slicer_line_offset
;
116 #define CXADEC_CHIP_TYPE_TIGER 0x837
117 #define CXADEC_CHIP_TYPE_MAKO 0x843
119 #define CXADEC_HOST_REG1 0x000
120 #define CXADEC_HOST_REG2 0x001
122 #define CXADEC_CHIP_CTRL 0x100
123 #define CXADEC_AFE_CTRL 0x104
124 #define CXADEC_PLL_CTRL1 0x108
125 #define CXADEC_VID_PLL_FRAC 0x10C
126 #define CXADEC_AUX_PLL_FRAC 0x110
127 #define CXADEC_PIN_CTRL1 0x114
128 #define CXADEC_PIN_CTRL2 0x118
129 #define CXADEC_PIN_CFG1 0x11C
130 #define CXADEC_PIN_CFG2 0x120
132 #define CXADEC_PIN_CFG3 0x124
133 #define CXADEC_I2S_MCLK 0x127
135 #define CXADEC_AUD_LOCK1 0x128
136 #define CXADEC_AUD_LOCK2 0x12C
137 #define CXADEC_POWER_CTRL 0x130
138 #define CXADEC_AFE_DIAG_CTRL1 0x134
139 #define CXADEC_AFE_DIAG_CTRL2 0x138
140 #define CXADEC_AFE_DIAG_CTRL3 0x13C
141 #define CXADEC_PLL_DIAG_CTRL 0x140
142 #define CXADEC_TEST_CTRL1 0x144
143 #define CXADEC_TEST_CTRL2 0x148
144 #define CXADEC_BIST_STAT 0x14C
145 #define CXADEC_DLL1_DIAG_CTRL 0x158
146 #define CXADEC_DLL2_DIAG_CTRL 0x15C
149 #define CXADEC_IR_CTRL_REG 0x200
150 #define CXADEC_IR_TXCLK_REG 0x204
151 #define CXADEC_IR_RXCLK_REG 0x208
152 #define CXADEC_IR_CDUTY_REG 0x20C
153 #define CXADEC_IR_STAT_REG 0x210
154 #define CXADEC_IR_IRQEN_REG 0x214
155 #define CXADEC_IR_FILTER_REG 0x218
156 #define CXADEC_IR_FIFO_REG 0x21C
158 /* Video Registers */
159 #define CXADEC_MODE_CTRL 0x400
160 #define CXADEC_OUT_CTRL1 0x404
161 #define CXADEC_OUT_CTRL2 0x408
162 #define CXADEC_GEN_STAT 0x40C
163 #define CXADEC_INT_STAT_MASK 0x410
164 #define CXADEC_LUMA_CTRL 0x414
166 #define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414
167 #define CXADEC_CONTRAST_CTRL_BYTE 0x415
168 #define CXADEC_LUMA_CTRL_BYTE_3 0x416
170 #define CXADEC_HSCALE_CTRL 0x418
171 #define CXADEC_VSCALE_CTRL 0x41C
173 #define CXADEC_CHROMA_CTRL 0x420
175 #define CXADEC_USAT_CTRL_BYTE 0x420
176 #define CXADEC_VSAT_CTRL_BYTE 0x421
177 #define CXADEC_HUE_CTRL_BYTE 0x422
179 #define CXADEC_VBI_LINE_CTRL1 0x424
180 #define CXADEC_VBI_LINE_CTRL2 0x428
181 #define CXADEC_VBI_LINE_CTRL3 0x42C
182 #define CXADEC_VBI_LINE_CTRL4 0x430
183 #define CXADEC_VBI_LINE_CTRL5 0x434
184 #define CXADEC_VBI_FC_CFG 0x438
185 #define CXADEC_VBI_MISC_CFG1 0x43C
186 #define CXADEC_VBI_MISC_CFG2 0x440
187 #define CXADEC_VBI_PAY1 0x444
188 #define CXADEC_VBI_PAY2 0x448
189 #define CXADEC_VBI_CUST1_CFG1 0x44C
190 #define CXADEC_VBI_CUST1_CFG2 0x450
191 #define CXADEC_VBI_CUST1_CFG3 0x454
192 #define CXADEC_VBI_CUST2_CFG1 0x458
193 #define CXADEC_VBI_CUST2_CFG2 0x45C
194 #define CXADEC_VBI_CUST2_CFG3 0x460
195 #define CXADEC_VBI_CUST3_CFG1 0x464
196 #define CXADEC_VBI_CUST3_CFG2 0x468
197 #define CXADEC_VBI_CUST3_CFG3 0x46C
198 #define CXADEC_HORIZ_TIM_CTRL 0x470
199 #define CXADEC_VERT_TIM_CTRL 0x474
200 #define CXADEC_SRC_COMB_CFG 0x478
201 #define CXADEC_CHROMA_VBIOFF_CFG 0x47C
202 #define CXADEC_FIELD_COUNT 0x480
203 #define CXADEC_MISC_TIM_CTRL 0x484
204 #define CXADEC_DFE_CTRL1 0x488
205 #define CXADEC_DFE_CTRL2 0x48C
206 #define CXADEC_DFE_CTRL3 0x490
207 #define CXADEC_PLL_CTRL2 0x494
208 #define CXADEC_HTL_CTRL 0x498
209 #define CXADEC_COMB_CTRL 0x49C
210 #define CXADEC_CRUSH_CTRL 0x4A0
211 #define CXADEC_SOFT_RST_CTRL 0x4A4
212 #define CXADEC_MV_DT_CTRL2 0x4A8
213 #define CXADEC_MV_DT_CTRL3 0x4AC
214 #define CXADEC_MISC_DIAG_CTRL 0x4B8
216 #define CXADEC_DL_CTL 0x800
217 #define CXADEC_DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */
218 #define CXADEC_DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */
219 #define CXADEC_DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */
220 #define CXADEC_DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */
222 #define CXADEC_STD_DET_STATUS 0x804
224 #define CXADEC_STD_DET_CTL 0x808
225 #define CXADEC_STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */
226 #define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
228 #define CXADEC_DW8051_INT 0x80C
229 #define CXADEC_GENERAL_CTL 0x810
230 #define CXADEC_AAGC_CTL 0x814
231 #define CXADEC_IF_SRC_CTL 0x818
232 #define CXADEC_ANLOG_DEMOD_CTL 0x81C
233 #define CXADEC_ROT_FREQ_CTL 0x820
234 #define CXADEC_FM1_CTL 0x824
235 #define CXADEC_PDF_CTL 0x828
236 #define CXADEC_DFT1_CTL1 0x82C
237 #define CXADEC_DFT1_CTL2 0x830
238 #define CXADEC_DFT_STATUS 0x834
239 #define CXADEC_DFT2_CTL1 0x838
240 #define CXADEC_DFT2_CTL2 0x83C
241 #define CXADEC_DFT2_STATUS 0x840
242 #define CXADEC_DFT3_CTL1 0x844
243 #define CXADEC_DFT3_CTL2 0x848
244 #define CXADEC_DFT3_STATUS 0x84C
245 #define CXADEC_DFT4_CTL1 0x850
246 #define CXADEC_DFT4_CTL2 0x854
247 #define CXADEC_DFT4_STATUS 0x858
248 #define CXADEC_AM_MTS_DET 0x85C
249 #define CXADEC_ANALOG_MUX_CTL 0x860
250 #define CXADEC_DIG_PLL_CTL1 0x864
251 #define CXADEC_DIG_PLL_CTL2 0x868
252 #define CXADEC_DIG_PLL_CTL3 0x86C
253 #define CXADEC_DIG_PLL_CTL4 0x870
254 #define CXADEC_DIG_PLL_CTL5 0x874
255 #define CXADEC_DEEMPH_GAIN_CTL 0x878
256 #define CXADEC_DEEMPH_COEF1 0x87C
257 #define CXADEC_DEEMPH_COEF2 0x880
258 #define CXADEC_DBX1_CTL1 0x884
259 #define CXADEC_DBX1_CTL2 0x888
260 #define CXADEC_DBX1_STATUS 0x88C
261 #define CXADEC_DBX2_CTL1 0x890
262 #define CXADEC_DBX2_CTL2 0x894
263 #define CXADEC_DBX2_STATUS 0x898
264 #define CXADEC_AM_FM_DIFF 0x89C
266 /* NICAM registers go here */
267 #define CXADEC_NICAM_STATUS 0x8C8
268 #define CXADEC_DEMATRIX_CTL 0x8CC
270 #define CXADEC_PATH1_CTL1 0x8D0
271 #define CXADEC_PATH1_VOL_CTL 0x8D4
272 #define CXADEC_PATH1_EQ_CTL 0x8D8
273 #define CXADEC_PATH1_SC_CTL 0x8DC
275 #define CXADEC_PATH2_CTL1 0x8E0
276 #define CXADEC_PATH2_VOL_CTL 0x8E4
277 #define CXADEC_PATH2_EQ_CTL 0x8E8
278 #define CXADEC_PATH2_SC_CTL 0x8EC
280 #define CXADEC_SRC_CTL 0x8F0
281 #define CXADEC_SRC_LF_COEF 0x8F4
282 #define CXADEC_SRC1_CTL 0x8F8
283 #define CXADEC_SRC2_CTL 0x8FC
284 #define CXADEC_SRC3_CTL 0x900
285 #define CXADEC_SRC4_CTL 0x904
286 #define CXADEC_SRC5_CTL 0x908
287 #define CXADEC_SRC6_CTL 0x90C
289 #define CXADEC_BASEBAND_OUT_SEL 0x910
290 #define CXADEC_I2S_IN_CTL 0x914
291 #define CXADEC_I2S_OUT_CTL 0x918
292 #define CXADEC_AC97_CTL 0x91C
293 #define CXADEC_QAM_PDF 0x920
294 #define CXADEC_QAM_CONST_DEC 0x924
295 #define CXADEC_QAM_ROTATOR_FREQ 0x948
297 /* Bit definitions / settings used in Mako Audio */
298 #define CXADEC_PREF_MODE_MONO_LANGA 0
299 #define CXADEC_PREF_MODE_MONO_LANGB 1
300 #define CXADEC_PREF_MODE_MONO_LANGC 2
301 #define CXADEC_PREF_MODE_FALLBACK 3
302 #define CXADEC_PREF_MODE_STEREO 4
303 #define CXADEC_PREF_MODE_DUAL_LANG_AC 5
304 #define CXADEC_PREF_MODE_DUAL_LANG_BC 6
305 #define CXADEC_PREF_MODE_DUAL_LANG_AB 7
308 #define CXADEC_DETECT_STEREO 1
309 #define CXADEC_DETECT_DUAL 2
310 #define CXADEC_DETECT_TRI 4
311 #define CXADEC_DETECT_SAP 0x10
312 #define CXADEC_DETECT_NO_SIGNAL 0xFF
314 #define CXADEC_SELECT_AUDIO_STANDARD_BG 0xF0 /* NICAM BG and A2 BG */
315 #define CXADEC_SELECT_AUDIO_STANDARD_DK1 0xF1 /* NICAM DK and A2 DK */
316 #define CXADEC_SELECT_AUDIO_STANDARD_DK2 0xF2
317 #define CXADEC_SELECT_AUDIO_STANDARD_DK3 0xF3
318 #define CXADEC_SELECT_AUDIO_STANDARD_I 0xF4 /* NICAM I and A1 */
319 #define CXADEC_SELECT_AUDIO_STANDARD_L 0xF5 /* NICAM L and System L AM */
320 #define CXADEC_SELECT_AUDIO_STANDARD_BTSC 0xF6
321 #define CXADEC_SELECT_AUDIO_STANDARD_EIAJ 0xF7
322 #define CXADEC_SELECT_AUDIO_STANDARD_A2_M 0xF8 /* A2 M */
323 #define CXADEC_SELECT_AUDIO_STANDARD_FM 0xF9 /* FM radio */
324 #define CXADEC_SELECT_AUDIO_STANDARD_AUTO 0xFF /* Auto detect */
326 static inline struct cx18_av_state
*to_cx18_av_state(struct v4l2_subdev
*sd
)
328 return container_of(sd
, struct cx18_av_state
, sd
);
331 /* ----------------------------------------------------------------------- */
333 int cx18_av_write(struct cx18
*cx
, u16 addr
, u8 value
);
334 int cx18_av_write4(struct cx18
*cx
, u16 addr
, u32 value
);
335 int cx18_av_write4_noretry(struct cx18
*cx
, u16 addr
, u32 value
);
336 int cx18_av_write_expect(struct cx18
*cx
, u16 addr
, u8 value
, u8 eval
, u8 mask
);
337 int cx18_av_write4_expect(struct cx18
*cx
, u16 addr
, u32 value
, u32 eval
,
339 u8
cx18_av_read(struct cx18
*cx
, u16 addr
);
340 u32
cx18_av_read4(struct cx18
*cx
, u16 addr
);
341 int cx18_av_and_or(struct cx18
*cx
, u16 addr
, unsigned mask
, u8 value
);
342 int cx18_av_and_or4(struct cx18
*cx
, u16 addr
, u32 mask
, u32 value
);
343 void cx18_av_std_setup(struct cx18
*cx
);
345 int cx18_av_probe(struct cx18
*cx
);
347 /* ----------------------------------------------------------------------- */
348 /* cx18_av-firmware.c */
349 int cx18_av_loadfw(struct cx18
*cx
);
351 /* ----------------------------------------------------------------------- */
352 /* cx18_av-audio.c */
353 int cx18_av_audio_g_ctrl(struct cx18
*cx
, struct v4l2_control
*ctrl
);
354 int cx18_av_audio_s_ctrl(struct cx18
*cx
, struct v4l2_control
*ctrl
);
355 int cx18_av_s_clock_freq(struct v4l2_subdev
*sd
, u32 freq
);
356 void cx18_av_audio_set_path(struct cx18
*cx
);
358 /* ----------------------------------------------------------------------- */
360 int cx18_av_decode_vbi_line(struct v4l2_subdev
*sd
,
361 struct v4l2_decode_vbi_line
*vbi
);
362 int cx18_av_vbi_g_fmt(struct cx18
*cx
, struct v4l2_format
*fmt
);
363 int cx18_av_vbi_s_fmt(struct cx18
*cx
, struct v4l2_format
*fmt
);