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Linux 2.6.34-rc3
[pohmelfs.git] / drivers / media / video / davinci / dm644x_ccdc.c
blob0c394cade22a5919173c0ea9b0e612d480f2022b
1 /*
2 * Copyright (C) 2006-2009 Texas Instruments Inc
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * CCDC hardware module for DM6446
19 * ------------------------------
20 *
21 * This module is for configuring CCD controller of DM6446 VPFE to capture
22 * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
23 * such as Defect Pixel Correction, Color Space Conversion etc to
24 * pre-process the Raw Bayer RGB data, before writing it to SDRAM. This
25 * module also allows application to configure individual
26 * module parameters through VPFE_CMD_S_CCDC_RAW_PARAMS IOCTL.
27 * To do so, application includes dm644x_ccdc.h and vpfe_capture.h header
28 * files. The setparams() API is called by vpfe_capture driver
29 * to configure module parameters. This file is named DM644x so that other
30 * variants such DM6443 may be supported using the same module.
31 *
32 * TODO: Test Raw bayer parameter settings and bayer capture
33 * Split module parameter structure to module specific ioctl structs
34 * investigate if enum used for user space type definition
35 * to be replaced by #defines or integer
36 */
37 #include <linux/platform_device.h>
38 #include <linux/uaccess.h>
39 #include <linux/videodev2.h>
40 #include <linux/clk.h>
41 #include <linux/err.h>
42
43 #include <media/davinci/dm644x_ccdc.h>
44 #include <media/davinci/vpss.h>
45
46 #include "dm644x_ccdc_regs.h"
47 #include "ccdc_hw_device.h"
48
49 MODULE_LICENSE("GPL");
50 MODULE_DESCRIPTION("CCDC Driver for DM6446");
51 MODULE_AUTHOR("Texas Instruments");
52
53 static struct ccdc_oper_config {
54 struct device *dev;
55 /* CCDC interface type */
56 enum vpfe_hw_if_type if_type;
57 /* Raw Bayer configuration */
58 struct ccdc_params_raw bayer;
59 /* YCbCr configuration */
60 struct ccdc_params_ycbcr ycbcr;
61 /* Master clock */
62 struct clk *mclk;
63 /* slave clock */
64 struct clk *sclk;
65 /* ccdc base address */
66 void __iomem *base_addr;
67 } ccdc_cfg = {
68 /* Raw configurations */
69 .bayer = {
70 .pix_fmt = CCDC_PIXFMT_RAW,
71 .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
72 .win = CCDC_WIN_VGA,
73 .fid_pol = VPFE_PINPOL_POSITIVE,
74 .vd_pol = VPFE_PINPOL_POSITIVE,
75 .hd_pol = VPFE_PINPOL_POSITIVE,
76 .config_params = {
77 .data_sz = CCDC_DATA_10BITS,
78 },
79 },
80 .ycbcr = {
81 .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
82 .frm_fmt = CCDC_FRMFMT_INTERLACED,
83 .win = CCDC_WIN_PAL,
84 .fid_pol = VPFE_PINPOL_POSITIVE,
85 .vd_pol = VPFE_PINPOL_POSITIVE,
86 .hd_pol = VPFE_PINPOL_POSITIVE,
87 .bt656_enable = 1,
88 .pix_order = CCDC_PIXORDER_CBYCRY,
89 .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
90 },
91 };
92
93 #define CCDC_MAX_RAW_YUV_FORMATS 2
94
95 /* Raw Bayer formats */
96 static u32 ccdc_raw_bayer_pix_formats[] =
97 {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
98
99 /* Raw YUV formats */
100 static u32 ccdc_raw_yuv_pix_formats[] =
101 {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
102
103 /* register access routines */
104 static inline u32 regr(u32 offset)
105 {
106 return __raw_readl(ccdc_cfg.base_addr + offset);
107 }
108
109 static inline void regw(u32 val, u32 offset)
110 {
111 __raw_writel(val, ccdc_cfg.base_addr + offset);
112 }
113
114 static void ccdc_enable(int flag)
115 {
116 regw(flag, CCDC_PCR);
117 }
118
119 static void ccdc_enable_vport(int flag)
120 {
121 if (flag)
122 /* enable video port */
123 regw(CCDC_ENABLE_VIDEO_PORT, CCDC_FMTCFG);
124 else
125 regw(CCDC_DISABLE_VIDEO_PORT, CCDC_FMTCFG);
126 }
127
128 /*
129 * ccdc_setwin()
130 * This function will configure the window size
131 * to be capture in CCDC reg
132 */
133 void ccdc_setwin(struct v4l2_rect *image_win,
134 enum ccdc_frmfmt frm_fmt,
135 int ppc)
136 {
137 int horz_start, horz_nr_pixels;
138 int vert_start, vert_nr_lines;
139 int val = 0, mid_img = 0;
140
141 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin...");
142 /*
143 * ppc - per pixel count. indicates how many pixels per cell
144 * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
145 * raw capture this is 1
146 */
147 horz_start = image_win->left << (ppc - 1);
148 horz_nr_pixels = (image_win->width << (ppc - 1)) - 1;
149 regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels,
150 CCDC_HORZ_INFO);
151
152 vert_start = image_win->top;
153
154 if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
155 vert_nr_lines = (image_win->height >> 1) - 1;
156 vert_start >>= 1;
157 /* Since first line doesn't have any data */
158 vert_start += 1;
159 /* configure VDINT0 */
160 val = (vert_start << CCDC_VDINT_VDINT0_SHIFT);
161 regw(val, CCDC_VDINT);
162
163 } else {
164 /* Since first line doesn't have any data */
165 vert_start += 1;
166 vert_nr_lines = image_win->height - 1;
167 /*
168 * configure VDINT0 and VDINT1. VDINT1 will be at half
169 * of image height
170 */
171 mid_img = vert_start + (image_win->height / 2);
172 val = (vert_start << CCDC_VDINT_VDINT0_SHIFT) |
173 (mid_img & CCDC_VDINT_VDINT1_MASK);
174 regw(val, CCDC_VDINT);
175
176 }
177 regw((vert_start << CCDC_VERT_START_SLV0_SHIFT) | vert_start,
178 CCDC_VERT_START);
179 regw(vert_nr_lines, CCDC_VERT_LINES);
180 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin...");
181 }
182
183 static void ccdc_readregs(void)
184 {
185 unsigned int val = 0;
186
187 val = regr(CCDC_ALAW);
188 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to ALAW...\n", val);
189 val = regr(CCDC_CLAMP);
190 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to CLAMP...\n", val);
191 val = regr(CCDC_DCSUB);
192 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to DCSUB...\n", val);
193 val = regr(CCDC_BLKCMP);
194 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to BLKCMP...\n", val);
195 val = regr(CCDC_FPC_ADDR);
196 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC_ADDR...\n", val);
197 val = regr(CCDC_FPC);
198 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC...\n", val);
199 val = regr(CCDC_FMTCFG);
200 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMTCFG...\n", val);
201 val = regr(CCDC_COLPTN);
202 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to COLPTN...\n", val);
203 val = regr(CCDC_FMT_HORZ);
204 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_HORZ...\n", val);
205 val = regr(CCDC_FMT_VERT);
206 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_VERT...\n", val);
207 val = regr(CCDC_HSIZE_OFF);
208 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HSIZE_OFF...\n", val);
209 val = regr(CCDC_SDOFST);
210 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SDOFST...\n", val);
211 val = regr(CCDC_VP_OUT);
212 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VP_OUT...\n", val);
213 val = regr(CCDC_SYN_MODE);
214 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SYN_MODE...\n", val);
215 val = regr(CCDC_HORZ_INFO);
216 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HORZ_INFO...\n", val);
217 val = regr(CCDC_VERT_START);
218 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_START...\n", val);
219 val = regr(CCDC_VERT_LINES);
220 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_LINES...\n", val);
221 }
222
223 static int validate_ccdc_param(struct ccdc_config_params_raw *ccdcparam)
224 {
225 if (ccdcparam->alaw.enable) {
226 if ((ccdcparam->alaw.gama_wd > CCDC_GAMMA_BITS_09_0) ||
227 (ccdcparam->alaw.gama_wd < CCDC_GAMMA_BITS_15_6) ||
228 (ccdcparam->alaw.gama_wd < ccdcparam->data_sz)) {
229 dev_dbg(ccdc_cfg.dev, "\nInvalid data line select");
230 return -1;
231 }
232 }
233 return 0;
234 }
235
236 static int ccdc_update_raw_params(struct ccdc_config_params_raw *raw_params)
237 {
238 struct ccdc_config_params_raw *config_params =
239 &ccdc_cfg.bayer.config_params;
240 unsigned int *fpc_virtaddr = NULL;
241 unsigned int *fpc_physaddr = NULL;
242
243 memcpy(config_params, raw_params, sizeof(*raw_params));
244 /*
245 * allocate memory for fault pixel table and copy the user
246 * values to the table
247 */
248 if (!config_params->fault_pxl.enable)
249 return 0;
250
251 fpc_physaddr = (unsigned int *)config_params->fault_pxl.fpc_table_addr;
252 fpc_virtaddr = (unsigned int *)phys_to_virt(
253 (unsigned long)fpc_physaddr);
254 /*
255 * Allocate memory for FPC table if current
256 * FPC table buffer is not big enough to
257 * accomodate FPC Number requested
258 */
259 if (raw_params->fault_pxl.fp_num != config_params->fault_pxl.fp_num) {
260 if (fpc_physaddr != NULL) {
261 free_pages((unsigned long)fpc_physaddr,
262 get_order
263 (config_params->fault_pxl.fp_num *
264 FP_NUM_BYTES));
265 }
266
267 /* Allocate memory for FPC table */
268 fpc_virtaddr =
269 (unsigned int *)__get_free_pages(GFP_KERNEL | GFP_DMA,
270 get_order(raw_params->
271 fault_pxl.fp_num *
272 FP_NUM_BYTES));
273
274 if (fpc_virtaddr == NULL) {
275 dev_dbg(ccdc_cfg.dev,
276 "\nUnable to allocate memory for FPC");
277 return -EFAULT;
278 }
279 fpc_physaddr =
280 (unsigned int *)virt_to_phys((void *)fpc_virtaddr);
281 }
282
283 /* Copy number of fault pixels and FPC table */
284 config_params->fault_pxl.fp_num = raw_params->fault_pxl.fp_num;
285 if (copy_from_user(fpc_virtaddr,
286 (void __user *)raw_params->fault_pxl.fpc_table_addr,
287 config_params->fault_pxl.fp_num * FP_NUM_BYTES)) {
288 dev_dbg(ccdc_cfg.dev, "\n copy_from_user failed");
289 return -EFAULT;
290 }
291 config_params->fault_pxl.fpc_table_addr = (unsigned int)fpc_physaddr;
292 return 0;
293 }
294
295 static int ccdc_close(struct device *dev)
296 {
297 struct ccdc_config_params_raw *config_params =
298 &ccdc_cfg.bayer.config_params;
299 unsigned int *fpc_physaddr = NULL, *fpc_virtaddr = NULL;
300
301 fpc_physaddr = (unsigned int *)config_params->fault_pxl.fpc_table_addr;
302
303 if (fpc_physaddr != NULL) {
304 fpc_virtaddr = (unsigned int *)
305 phys_to_virt((unsigned long)fpc_physaddr);
306 free_pages((unsigned long)fpc_virtaddr,
307 get_order(config_params->fault_pxl.fp_num *
308 FP_NUM_BYTES));
309 }
310 return 0;
311 }
312
313 /*
314 * ccdc_restore_defaults()
315 * This function will write defaults to all CCDC registers
316 */
317 static void ccdc_restore_defaults(void)
318 {
319 int i;
320
321 /* disable CCDC */
322 ccdc_enable(0);
323 /* set all registers to default value */
324 for (i = 4; i <= 0x94; i += 4)
325 regw(0, i);
326 regw(CCDC_NO_CULLING, CCDC_CULLING);
327 regw(CCDC_GAMMA_BITS_11_2, CCDC_ALAW);
328 }
329
330 static int ccdc_open(struct device *device)
331 {
332 ccdc_restore_defaults();
333 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
334 ccdc_enable_vport(1);
335 return 0;
336 }
337
338 static void ccdc_sbl_reset(void)
339 {
340 vpss_clear_wbl_overflow(VPSS_PCR_CCDC_WBL_O);
341 }
342
343 /* Parameter operations */
344 static int ccdc_set_params(void __user *params)
345 {
346 struct ccdc_config_params_raw ccdc_raw_params;
347 int x;
348
349 if (ccdc_cfg.if_type != VPFE_RAW_BAYER)
350 return -EINVAL;
351
352 x = copy_from_user(&ccdc_raw_params, params, sizeof(ccdc_raw_params));
353 if (x) {
354 dev_dbg(ccdc_cfg.dev, "ccdc_set_params: error in copying"
355 "ccdc params, %d\n", x);
356 return -EFAULT;
357 }
358
359 if (!validate_ccdc_param(&ccdc_raw_params)) {
360 if (!ccdc_update_raw_params(&ccdc_raw_params))
361 return 0;
362 }
363 return -EINVAL;
364 }
365
366 /*
367 * ccdc_config_ycbcr()
368 * This function will configure CCDC for YCbCr video capture
369 */
370 void ccdc_config_ycbcr(void)
371 {
372 struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr;
373 u32 syn_mode;
374
375 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr...");
376 /*
377 * first restore the CCDC registers to default values
378 * This is important since we assume default values to be set in
379 * a lot of registers that we didn't touch
380 */
381 ccdc_restore_defaults();
382
383 /*
384 * configure pixel format, frame format, configure video frame
385 * format, enable output to SDRAM, enable internal timing generator
386 * and 8bit pack mode
387 */
388 syn_mode = (((params->pix_fmt & CCDC_SYN_MODE_INPMOD_MASK) <<
389 CCDC_SYN_MODE_INPMOD_SHIFT) |
390 ((params->frm_fmt & CCDC_SYN_FLDMODE_MASK) <<
391 CCDC_SYN_FLDMODE_SHIFT) | CCDC_VDHDEN_ENABLE |
392 CCDC_WEN_ENABLE | CCDC_DATA_PACK_ENABLE);
393
394 /* setup BT.656 sync mode */
395 if (params->bt656_enable) {
396 regw(CCDC_REC656IF_BT656_EN, CCDC_REC656IF);
397
398 /*
399 * configure the FID, VD, HD pin polarity,
400 * fld,hd pol positive, vd negative, 8-bit data
401 */
402 syn_mode |= CCDC_SYN_MODE_VD_POL_NEGATIVE | CCDC_SYN_MODE_8BITS;
403 } else {
404 /* y/c external sync mode */
405 syn_mode |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
406 CCDC_FID_POL_SHIFT) |
407 ((params->hd_pol & CCDC_HD_POL_MASK) <<
408 CCDC_HD_POL_SHIFT) |
409 ((params->vd_pol & CCDC_VD_POL_MASK) <<
410 CCDC_VD_POL_SHIFT));
411 }
412 regw(syn_mode, CCDC_SYN_MODE);
413
414 /* configure video window */
415 ccdc_setwin(&params->win, params->frm_fmt, 2);
416
417 /*
418 * configure the order of y cb cr in SDRAM, and disable latch
419 * internal register on vsync
420 */
421 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
422 CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
423
424 /*
425 * configure the horizontal line offset. This should be a
426 * on 32 byte bondary. So clear LSB 5 bits
427 */
428 regw(((params->win.width * 2 + 31) & ~0x1f), CCDC_HSIZE_OFF);
429
430 /* configure the memory line offset */
431 if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED)
432 /* two fields are interleaved in memory */
433 regw(CCDC_SDOFST_FIELD_INTERLEAVED, CCDC_SDOFST);
434
435 ccdc_sbl_reset();
436 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n");
437 ccdc_readregs();
438 }
439
440 static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
441 {
442 u32 val;
443
444 if (!bclamp->enable) {
445 /* configure DCSub */
446 val = (bclamp->dc_sub) & CCDC_BLK_DC_SUB_MASK;
447 regw(val, CCDC_DCSUB);
448 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to DCSUB...\n", val);
449 regw(CCDC_CLAMP_DEFAULT_VAL, CCDC_CLAMP);
450 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to CLAMP...\n");
451 return;
452 }
453 /*
454 * Configure gain, Start pixel, No of line to be avg,
455 * No of pixel/line to be avg, & Enable the Black clamping
456 */
457 val = ((bclamp->sgain & CCDC_BLK_SGAIN_MASK) |
458 ((bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) <<
459 CCDC_BLK_ST_PXL_SHIFT) |
460 ((bclamp->sample_ln & CCDC_BLK_SAMPLE_LINE_MASK) <<
461 CCDC_BLK_SAMPLE_LINE_SHIFT) |
462 ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
463 CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE);
464 regw(val, CCDC_CLAMP);
465 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to CLAMP...\n", val);
466 /* If Black clamping is enable then make dcsub 0 */
467 regw(CCDC_DCSUB_DEFAULT_VAL, CCDC_DCSUB);
468 dev_dbg(ccdc_cfg.dev, "\nWriting 0x00000000 to DCSUB...\n");
469 }
470
471 static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
472 {
473 u32 val;
474
475 val = ((bcomp->b & CCDC_BLK_COMP_MASK) |
476 ((bcomp->gb & CCDC_BLK_COMP_MASK) <<
477 CCDC_BLK_COMP_GB_COMP_SHIFT) |
478 ((bcomp->gr & CCDC_BLK_COMP_MASK) <<
479 CCDC_BLK_COMP_GR_COMP_SHIFT) |
480 ((bcomp->r & CCDC_BLK_COMP_MASK) <<
481 CCDC_BLK_COMP_R_COMP_SHIFT));
482 regw(val, CCDC_BLKCMP);
483 }
484
485 static void ccdc_config_fpc(struct ccdc_fault_pixel *fpc)
486 {
487 u32 val;
488
489 /* Initially disable FPC */
490 val = CCDC_FPC_DISABLE;
491 regw(val, CCDC_FPC);
492
493 if (!fpc->enable)
494 return;
495
496 /* Configure Fault pixel if needed */
497 regw(fpc->fpc_table_addr, CCDC_FPC_ADDR);
498 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FPC_ADDR...\n",
499 (fpc->fpc_table_addr));
500 /* Write the FPC params with FPC disable */
501 val = fpc->fp_num & CCDC_FPC_FPC_NUM_MASK;
502 regw(val, CCDC_FPC);
503
504 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FPC...\n", val);
505 /* read the FPC register */
506 val = regr(CCDC_FPC) | CCDC_FPC_ENABLE;
507 regw(val, CCDC_FPC);
508 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FPC...\n", val);
509 }
510
511 /*
512 * ccdc_config_raw()
513 * This function will configure CCDC for Raw capture mode
514 */
515 void ccdc_config_raw(void)
516 {
517 struct ccdc_params_raw *params = &ccdc_cfg.bayer;
518 struct ccdc_config_params_raw *config_params =
519 &ccdc_cfg.bayer.config_params;
520 unsigned int syn_mode = 0;
521 unsigned int val;
522
523 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw...");
524
525 /* Reset CCDC */
526 ccdc_restore_defaults();
527
528 /* Disable latching function registers on VSYNC */
529 regw(CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
530
531 /*
532 * Configure the vertical sync polarity(SYN_MODE.VDPOL),
533 * horizontal sync polarity (SYN_MODE.HDPOL), frame id polarity
534 * (SYN_MODE.FLDPOL), frame format(progressive or interlace),
535 * data size(SYNMODE.DATSIZ), &pixel format (Input mode), output
536 * SDRAM, enable internal timing generator
537 */
538 syn_mode =
539 (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
540 ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
541 ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
542 ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
543 ((config_params->data_sz & CCDC_DATA_SZ_MASK) <<
544 CCDC_DATA_SZ_SHIFT) |
545 ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT) |
546 CCDC_WEN_ENABLE | CCDC_VDHDEN_ENABLE);
547
548 /* Enable and configure aLaw register if needed */
549 if (config_params->alaw.enable) {
550 val = ((config_params->alaw.gama_wd &
551 CCDC_ALAW_GAMA_WD_MASK) | CCDC_ALAW_ENABLE);
552 regw(val, CCDC_ALAW);
553 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to ALAW...\n", val);
554 }
555
556 /* Configure video window */
557 ccdc_setwin(&params->win, params->frm_fmt, CCDC_PPC_RAW);
558
559 /* Configure Black Clamp */
560 ccdc_config_black_clamp(&config_params->blk_clamp);
561
562 /* Configure Black level compensation */
563 ccdc_config_black_compense(&config_params->blk_comp);
564
565 /* Configure Fault Pixel Correction */
566 ccdc_config_fpc(&config_params->fault_pxl);
567
568 /* If data size is 8 bit then pack the data */
569 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
570 config_params->alaw.enable)
571 syn_mode |= CCDC_DATA_PACK_ENABLE;
572
573 #ifdef CONFIG_DM644X_VIDEO_PORT_ENABLE
574 /* enable video port */
575 val = CCDC_ENABLE_VIDEO_PORT;
576 #else
577 /* disable video port */
578 val = CCDC_DISABLE_VIDEO_PORT;
579 #endif
580
581 if (config_params->data_sz == CCDC_DATA_8BITS)
582 val |= (CCDC_DATA_10BITS & CCDC_FMTCFG_VPIN_MASK)
583 << CCDC_FMTCFG_VPIN_SHIFT;
584 else
585 val |= (config_params->data_sz & CCDC_FMTCFG_VPIN_MASK)
586 << CCDC_FMTCFG_VPIN_SHIFT;
587 /* Write value in FMTCFG */
588 regw(val, CCDC_FMTCFG);
589
590 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMTCFG...\n", val);
591 /* Configure the color pattern according to mt9t001 sensor */
592 regw(CCDC_COLPTN_VAL, CCDC_COLPTN);
593
594 dev_dbg(ccdc_cfg.dev, "\nWriting 0xBB11BB11 to COLPTN...\n");
595 /*
596 * Configure Data formatter(Video port) pixel selection
597 * (FMT_HORZ, FMT_VERT)
598 */
599 val = ((params->win.left & CCDC_FMT_HORZ_FMTSPH_MASK) <<
600 CCDC_FMT_HORZ_FMTSPH_SHIFT) |
601 (params->win.width & CCDC_FMT_HORZ_FMTLNH_MASK);
602 regw(val, CCDC_FMT_HORZ);
603
604 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_HORZ...\n", val);
605 val = (params->win.top & CCDC_FMT_VERT_FMTSLV_MASK)
606 << CCDC_FMT_VERT_FMTSLV_SHIFT;
607 if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
608 val |= (params->win.height) & CCDC_FMT_VERT_FMTLNV_MASK;
609 else
610 val |= (params->win.height >> 1) & CCDC_FMT_VERT_FMTLNV_MASK;
611
612 dev_dbg(ccdc_cfg.dev, "\nparams->win.height 0x%x ...\n",
613 params->win.height);
614 regw(val, CCDC_FMT_VERT);
615
616 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_VERT...\n", val);
617
618 dev_dbg(ccdc_cfg.dev, "\nbelow regw(val, FMT_VERT)...");
619
620 /*
621 * Configure Horizontal offset register. If pack 8 is enabled then
622 * 1 pixel will take 1 byte
623 */
624 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
625 config_params->alaw.enable)
626 regw((params->win.width + CCDC_32BYTE_ALIGN_VAL) &
627 CCDC_HSIZE_OFF_MASK, CCDC_HSIZE_OFF);
628 else
629 /* else one pixel will take 2 byte */
630 regw(((params->win.width * CCDC_TWO_BYTES_PER_PIXEL) +
631 CCDC_32BYTE_ALIGN_VAL) & CCDC_HSIZE_OFF_MASK,
632 CCDC_HSIZE_OFF);
633
634 /* Set value for SDOFST */
635 if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
636 if (params->image_invert_enable) {
637 /* For intelace inverse mode */
638 regw(CCDC_INTERLACED_IMAGE_INVERT, CCDC_SDOFST);
639 dev_dbg(ccdc_cfg.dev, "\nWriting 0x4B6D to SDOFST..\n");
640 }
641
642 else {
643 /* For intelace non inverse mode */
644 regw(CCDC_INTERLACED_NO_IMAGE_INVERT, CCDC_SDOFST);
645 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0249 to SDOFST..\n");
646 }
647 } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
648 regw(CCDC_PROGRESSIVE_NO_IMAGE_INVERT, CCDC_SDOFST);
649 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to SDOFST...\n");
650 }
651
652 /*
653 * Configure video port pixel selection (VPOUT)
654 * Here -1 is to make the height value less than FMT_VERT.FMTLNV
655 */
656 if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
657 val = (((params->win.height - 1) & CCDC_VP_OUT_VERT_NUM_MASK))
658 << CCDC_VP_OUT_VERT_NUM_SHIFT;
659 else
660 val =
661 ((((params->win.height >> CCDC_INTERLACED_HEIGHT_SHIFT) -
662 1) & CCDC_VP_OUT_VERT_NUM_MASK)) <<
663 CCDC_VP_OUT_VERT_NUM_SHIFT;
664
665 val |= ((((params->win.width))) & CCDC_VP_OUT_HORZ_NUM_MASK)
666 << CCDC_VP_OUT_HORZ_NUM_SHIFT;
667 val |= (params->win.left) & CCDC_VP_OUT_HORZ_ST_MASK;
668 regw(val, CCDC_VP_OUT);
669
670 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to VP_OUT...\n", val);
671 regw(syn_mode, CCDC_SYN_MODE);
672 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to SYN_MODE...\n", syn_mode);
673
674 ccdc_sbl_reset();
675 dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw...");
676 ccdc_readregs();
677 }
678
679 static int ccdc_configure(void)
680 {
681 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
682 ccdc_config_raw();
683 else
684 ccdc_config_ycbcr();
685 return 0;
686 }
687
688 static int ccdc_set_buftype(enum ccdc_buftype buf_type)
689 {
690 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
691 ccdc_cfg.bayer.buf_type = buf_type;
692 else
693 ccdc_cfg.ycbcr.buf_type = buf_type;
694 return 0;
695 }
696
697 static enum ccdc_buftype ccdc_get_buftype(void)
698 {
699 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
700 return ccdc_cfg.bayer.buf_type;
701 return ccdc_cfg.ycbcr.buf_type;
702 }
703
704 static int ccdc_enum_pix(u32 *pix, int i)
705 {
706 int ret = -EINVAL;
707 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
708 if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
709 *pix = ccdc_raw_bayer_pix_formats[i];
710 ret = 0;
711 }
712 } else {
713 if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
714 *pix = ccdc_raw_yuv_pix_formats[i];
715 ret = 0;
716 }
717 }
718 return ret;
719 }
720
721 static int ccdc_set_pixel_format(u32 pixfmt)
722 {
723 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
724 ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
725 if (pixfmt == V4L2_PIX_FMT_SBGGR8)
726 ccdc_cfg.bayer.config_params.alaw.enable = 1;
727 else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
728 return -EINVAL;
729 } else {
730 if (pixfmt == V4L2_PIX_FMT_YUYV)
731 ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
732 else if (pixfmt == V4L2_PIX_FMT_UYVY)
733 ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
734 else
735 return -EINVAL;
736 }
737 return 0;
738 }
739
740 static u32 ccdc_get_pixel_format(void)
741 {
742 struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
743 u32 pixfmt;
744
745 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
746 if (alaw->enable)
747 pixfmt = V4L2_PIX_FMT_SBGGR8;
748 else
749 pixfmt = V4L2_PIX_FMT_SBGGR16;
750 else {
751 if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
752 pixfmt = V4L2_PIX_FMT_YUYV;
753 else
754 pixfmt = V4L2_PIX_FMT_UYVY;
755 }
756 return pixfmt;
757 }
758
759 static int ccdc_set_image_window(struct v4l2_rect *win)
760 {
761 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
762 ccdc_cfg.bayer.win = *win;
763 else
764 ccdc_cfg.ycbcr.win = *win;
765 return 0;
766 }
767
768 static void ccdc_get_image_window(struct v4l2_rect *win)
769 {
770 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
771 *win = ccdc_cfg.bayer.win;
772 else
773 *win = ccdc_cfg.ycbcr.win;
774 }
775
776 static unsigned int ccdc_get_line_length(void)
777 {
778 struct ccdc_config_params_raw *config_params =
779 &ccdc_cfg.bayer.config_params;
780 unsigned int len;
781
782 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
783 if ((config_params->alaw.enable) ||
784 (config_params->data_sz == CCDC_DATA_8BITS))
785 len = ccdc_cfg.bayer.win.width;
786 else
787 len = ccdc_cfg.bayer.win.width * 2;
788 } else
789 len = ccdc_cfg.ycbcr.win.width * 2;
790 return ALIGN(len, 32);
791 }
792
793 static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
794 {
795 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
796 ccdc_cfg.bayer.frm_fmt = frm_fmt;
797 else
798 ccdc_cfg.ycbcr.frm_fmt = frm_fmt;
799 return 0;
800 }
801
802 static enum ccdc_frmfmt ccdc_get_frame_format(void)
803 {
804 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
805 return ccdc_cfg.bayer.frm_fmt;
806 else
807 return ccdc_cfg.ycbcr.frm_fmt;
808 }
809
810 static int ccdc_getfid(void)
811 {
812 return (regr(CCDC_SYN_MODE) >> 15) & 1;
813 }
814
815 /* misc operations */
816 static inline void ccdc_setfbaddr(unsigned long addr)
817 {
818 regw(addr & 0xffffffe0, CCDC_SDR_ADDR);
819 }
820
821 static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
822 {
823 ccdc_cfg.if_type = params->if_type;
824
825 switch (params->if_type) {
826 case VPFE_BT656:
827 case VPFE_YCBCR_SYNC_16:
828 case VPFE_YCBCR_SYNC_8:
829 ccdc_cfg.ycbcr.vd_pol = params->vdpol;
830 ccdc_cfg.ycbcr.hd_pol = params->hdpol;
831 break;
832 default:
833 /* TODO add support for raw bayer here */
834 return -EINVAL;
835 }
836 return 0;
837 }
838
839 static struct ccdc_hw_device ccdc_hw_dev = {
840 .name = "DM6446 CCDC",
841 .owner = THIS_MODULE,
842 .hw_ops = {
843 .open = ccdc_open,
844 .close = ccdc_close,
845 .reset = ccdc_sbl_reset,
846 .enable = ccdc_enable,
847 .set_hw_if_params = ccdc_set_hw_if_params,
848 .set_params = ccdc_set_params,
849 .configure = ccdc_configure,
850 .set_buftype = ccdc_set_buftype,
851 .get_buftype = ccdc_get_buftype,
852 .enum_pix = ccdc_enum_pix,
853 .set_pixel_format = ccdc_set_pixel_format,
854 .get_pixel_format = ccdc_get_pixel_format,
855 .set_frame_format = ccdc_set_frame_format,
856 .get_frame_format = ccdc_get_frame_format,
857 .set_image_window = ccdc_set_image_window,
858 .get_image_window = ccdc_get_image_window,
859 .get_line_length = ccdc_get_line_length,
860 .setfbaddr = ccdc_setfbaddr,
861 .getfid = ccdc_getfid,
862 },
863 };
864
865 static int __init dm644x_ccdc_probe(struct platform_device *pdev)
866 {
867 struct resource *res;
868 int status = 0;
869
870 /*
871 * first try to register with vpfe. If not correct platform, then we
872 * don't have to iomap
873 */
874 status = vpfe_register_ccdc_device(&ccdc_hw_dev);
875 if (status < 0)
876 return status;
877
878 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
879 if (!res) {
880 status = -ENODEV;
881 goto fail_nores;
882 }
883
884 res = request_mem_region(res->start, resource_size(res), res->name);
885 if (!res) {
886 status = -EBUSY;
887 goto fail_nores;
888 }
889
890 ccdc_cfg.base_addr = ioremap_nocache(res->start, resource_size(res));
891 if (!ccdc_cfg.base_addr) {
892 status = -ENOMEM;
893 goto fail_nomem;
894 }
895
896 /* Get and enable Master clock */
897 ccdc_cfg.mclk = clk_get(&pdev->dev, "master");
898 if (IS_ERR(ccdc_cfg.mclk)) {
899 status = PTR_ERR(ccdc_cfg.mclk);
900 goto fail_nomap;
901 }
902 if (clk_enable(ccdc_cfg.mclk)) {
903 status = -ENODEV;
904 goto fail_mclk;
905 }
906
907 /* Get and enable Slave clock */
908 ccdc_cfg.sclk = clk_get(&pdev->dev, "slave");
909 if (IS_ERR(ccdc_cfg.sclk)) {
910 status = PTR_ERR(ccdc_cfg.sclk);
911 goto fail_mclk;
912 }
913 if (clk_enable(ccdc_cfg.sclk)) {
914 status = -ENODEV;
915 goto fail_sclk;
916 }
917 ccdc_cfg.dev = &pdev->dev;
918 printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name);
919 return 0;
920 fail_sclk:
921 clk_put(ccdc_cfg.sclk);
922 fail_mclk:
923 clk_put(ccdc_cfg.mclk);
924 fail_nomap:
925 iounmap(ccdc_cfg.base_addr);
926 fail_nomem:
927 release_mem_region(res->start, resource_size(res));
928 fail_nores:
929 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
930 return status;
931 }
932
933 static int dm644x_ccdc_remove(struct platform_device *pdev)
934 {
935 struct resource *res;
936
937 clk_put(ccdc_cfg.mclk);
938 clk_put(ccdc_cfg.sclk);
939 iounmap(ccdc_cfg.base_addr);
940 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941 if (res)
942 release_mem_region(res->start, resource_size(res));
943 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
944 return 0;
945 }
946
947 static struct platform_driver dm644x_ccdc_driver = {
948 .driver = {
949 .name = "dm644x_ccdc",
950 .owner = THIS_MODULE,
951 },
952 .remove = __devexit_p(dm644x_ccdc_remove),
953 .probe = dm644x_ccdc_probe,
954 };
955
956 static int __init dm644x_ccdc_init(void)
957 {
958 return platform_driver_register(&dm644x_ccdc_driver);
959 }
960
961 static void __exit dm644x_ccdc_exit(void)
962 {
963 platform_driver_unregister(&dm644x_ccdc_driver);
964 }
965
966 module_init(dm644x_ccdc_init);
967 module_exit(dm644x_ccdc_exit);