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Linux 2.6.34-rc3
[pohmelfs.git] / drivers / media / video / gspca / w996Xcf.c
blob2fffe203bed876fdcaf4713ffe32edabd4b5d39f
1 /**
2 *
3 * GSPCA sub driver for W996[78]CF JPEG USB Dual Mode Camera Chip.
4 *
5 * Copyright (C) 2009 Hans de Goede <hdegoede@redhat.com>
6 *
7 * This module is adapted from the in kernel v4l1 w9968cf driver:
8 *
9 * Copyright (C) 2002-2004 by Luca Risolia <luca.risolia@studio.unibo.it>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26
27 /* Note this is not a stand alone driver, it gets included in ov519.c, this
28 is a bit of a hack, but it needs the driver code for a lot of different
29 ov sensors which is already present in ov519.c (the old v4l1 driver used
30 the ovchipcam framework). When we have the time we really should move
31 the sensor drivers to v4l2 sub drivers, and properly split of this
32 driver from ov519.c */
33
34 /* The CONEX_CAM define for jpeg.h needs renaming, now its used here too */
35 #define CONEX_CAM
36 #include "jpeg.h"
37
38 #define W9968CF_I2C_BUS_DELAY 4 /* delay in us for I2C bit r/w operations */
39
40 #define Y_QUANTABLE (sd->jpeg_hdr + JPEG_QT0_OFFSET)
41 #define UV_QUANTABLE (sd->jpeg_hdr + JPEG_QT1_OFFSET)
42
43 static const struct v4l2_pix_format w9968cf_vga_mode[] = {
44 {160, 120, V4L2_PIX_FMT_UYVY, V4L2_FIELD_NONE,
45 .bytesperline = 160 * 2,
46 .sizeimage = 160 * 120 * 2,
47 .colorspace = V4L2_COLORSPACE_JPEG},
48 {176, 144, V4L2_PIX_FMT_UYVY, V4L2_FIELD_NONE,
49 .bytesperline = 176 * 2,
50 .sizeimage = 176 * 144 * 2,
51 .colorspace = V4L2_COLORSPACE_JPEG},
52 {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
53 .bytesperline = 320 * 2,
54 .sizeimage = 320 * 240 * 2,
55 .colorspace = V4L2_COLORSPACE_JPEG},
56 {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
57 .bytesperline = 352 * 2,
58 .sizeimage = 352 * 288 * 2,
59 .colorspace = V4L2_COLORSPACE_JPEG},
60 {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
61 .bytesperline = 640 * 2,
62 .sizeimage = 640 * 480 * 2,
63 .colorspace = V4L2_COLORSPACE_JPEG},
64 };
65
66 static int reg_w(struct sd *sd, __u16 index, __u16 value);
67
68 /*--------------------------------------------------------------------------
69 Write 64-bit data to the fast serial bus registers.
70 Return 0 on success, -1 otherwise.
71 --------------------------------------------------------------------------*/
72 static int w9968cf_write_fsb(struct sd *sd, u16* data)
73 {
74 struct usb_device* udev = sd->gspca_dev.dev;
75 u16 value;
76 int ret;
77
78 value = *data++;
79 memcpy(sd->gspca_dev.usb_buf, data, 6);
80
81 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 0,
82 USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE,
83 value, 0x06, sd->gspca_dev.usb_buf, 6, 500);
84 if (ret < 0) {
85 PDEBUG(D_ERR, "Write FSB registers failed (%d)", ret);
86 return ret;
87 }
88
89 return 0;
90 }
91
92 /*--------------------------------------------------------------------------
93 Write data to the serial bus control register.
94 Return 0 on success, a negative number otherwise.
95 --------------------------------------------------------------------------*/
96 static int w9968cf_write_sb(struct sd *sd, u16 value)
97 {
98 int ret;
99
100 /* We don't use reg_w here, as that would cause all writes when
101 bitbanging i2c to be logged, making the logs impossible to read */
102 ret = usb_control_msg(sd->gspca_dev.dev,
103 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
104 0,
105 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
106 value, 0x01, NULL, 0, 500);
107
108 udelay(W9968CF_I2C_BUS_DELAY);
109
110 if (ret < 0) {
111 PDEBUG(D_ERR, "Write SB reg [01] %04x failed", value);
112 return ret;
113 }
114
115 return 0;
116 }
117
118 /*--------------------------------------------------------------------------
119 Read data from the serial bus control register.
120 Return 0 on success, a negative number otherwise.
121 --------------------------------------------------------------------------*/
122 static int w9968cf_read_sb(struct sd *sd)
123 {
124 int ret;
125
126 /* We don't use reg_r here, as the w9968cf is special and has 16
127 bit registers instead of 8 bit */
128 ret = usb_control_msg(sd->gspca_dev.dev,
129 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
130 1,
131 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
132 0, 0x01, sd->gspca_dev.usb_buf, 2, 500);
133 if (ret >= 0)
134 ret = sd->gspca_dev.usb_buf[0] |
135 (sd->gspca_dev.usb_buf[1] << 8);
136 else
137 PDEBUG(D_ERR, "Read SB reg [01] failed");
138
139 udelay(W9968CF_I2C_BUS_DELAY);
140
141 return ret;
142 }
143
144 /*--------------------------------------------------------------------------
145 Upload quantization tables for the JPEG compression.
146 This function is called by w9968cf_start_transfer().
147 Return 0 on success, a negative number otherwise.
148 --------------------------------------------------------------------------*/
149 static int w9968cf_upload_quantizationtables(struct sd *sd)
150 {
151 u16 a, b;
152 int ret = 0, i, j;
153
154 ret += reg_w(sd, 0x39, 0x0010); /* JPEG clock enable */
155
156 for (i = 0, j = 0; i < 32; i++, j += 2) {
157 a = Y_QUANTABLE[j] | ((unsigned)(Y_QUANTABLE[j+1]) << 8);
158 b = UV_QUANTABLE[j] | ((unsigned)(UV_QUANTABLE[j+1]) << 8);
159 ret += reg_w(sd, 0x40+i, a);
160 ret += reg_w(sd, 0x60+i, b);
161 }
162 ret += reg_w(sd, 0x39, 0x0012); /* JPEG encoder enable */
163
164 return ret;
165 }
166
167 /****************************************************************************
168 * Low-level I2C I/O functions. *
169 * The adapter supports the following I2C transfer functions: *
170 * i2c_adap_fastwrite_byte_data() (at 400 kHz bit frequency only) *
171 * i2c_adap_read_byte_data() *
172 * i2c_adap_read_byte() *
173 ****************************************************************************/
174
175 static int w9968cf_smbus_start(struct sd *sd)
176 {
177 int ret = 0;
178
179 ret += w9968cf_write_sb(sd, 0x0011); /* SDE=1, SDA=0, SCL=1 */
180 ret += w9968cf_write_sb(sd, 0x0010); /* SDE=1, SDA=0, SCL=0 */
181
182 return ret;
183 }
184
185 static int w9968cf_smbus_stop(struct sd *sd)
186 {
187 int ret = 0;
188
189 ret += w9968cf_write_sb(sd, 0x0010); /* SDE=1, SDA=0, SCL=0 */
190 ret += w9968cf_write_sb(sd, 0x0011); /* SDE=1, SDA=0, SCL=1 */
191 ret += w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
192
193 return ret;
194 }
195
196 static int w9968cf_smbus_write_byte(struct sd *sd, u8 v)
197 {
198 u8 bit;
199 int ret = 0, sda;
200
201 for (bit = 0 ; bit < 8 ; bit++) {
202 sda = (v & 0x80) ? 2 : 0;
203 v <<= 1;
204 /* SDE=1, SDA=sda, SCL=0 */
205 ret += w9968cf_write_sb(sd, 0x10 | sda);
206 /* SDE=1, SDA=sda, SCL=1 */
207 ret += w9968cf_write_sb(sd, 0x11 | sda);
208 /* SDE=1, SDA=sda, SCL=0 */
209 ret += w9968cf_write_sb(sd, 0x10 | sda);
210 }
211
212 return ret;
213 }
214
215 static int w9968cf_smbus_read_byte(struct sd *sd, u8* v)
216 {
217 u8 bit;
218 int ret = 0;
219
220 /* No need to ensure SDA is high as we are always called after
221 read_ack which ends with SDA high */
222 *v = 0;
223 for (bit = 0 ; bit < 8 ; bit++) {
224 *v <<= 1;
225 /* SDE=1, SDA=1, SCL=1 */
226 ret += w9968cf_write_sb(sd, 0x0013);
227 *v |= (w9968cf_read_sb(sd) & 0x0008) ? 1 : 0;
228 /* SDE=1, SDA=1, SCL=0 */
229 ret += w9968cf_write_sb(sd, 0x0012);
230 }
231
232 return ret;
233 }
234
235 static int w9968cf_smbus_write_nack(struct sd *sd)
236 {
237 int ret = 0;
238
239 /* No need to ensure SDA is high as we are always called after
240 read_byte which ends with SDA high */
241 ret += w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
242 ret += w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
243
244 return ret;
245 }
246
247 static int w9968cf_smbus_read_ack(struct sd *sd)
248 {
249 int ret = 0, sda;
250
251 /* Ensure SDA is high before raising clock to avoid a spurious stop */
252 ret += w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
253 ret += w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
254 sda = w9968cf_read_sb(sd);
255 ret += w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
256 if (sda < 0)
257 ret += sda;
258 else if (sda & 0x08) {
259 PDEBUG(D_USBI, "Did not receive i2c ACK");
260 ret += -1;
261 }
262
263 return ret;
264 }
265
266 /* SMBus protocol: S Addr Wr [A] Subaddr [A] Value [A] P */
267 static int w9968cf_i2c_w(struct sd *sd, u8 reg, u8 value)
268 {
269 u16* data = (u16 *)sd->gspca_dev.usb_buf;
270 int ret = 0;
271
272 data[0] = 0x082f | ((sd->sensor_addr & 0x80) ? 0x1500 : 0x0);
273 data[0] |= (sd->sensor_addr & 0x40) ? 0x4000 : 0x0;
274 data[1] = 0x2082 | ((sd->sensor_addr & 0x40) ? 0x0005 : 0x0);
275 data[1] |= (sd->sensor_addr & 0x20) ? 0x0150 : 0x0;
276 data[1] |= (sd->sensor_addr & 0x10) ? 0x5400 : 0x0;
277 data[2] = 0x8208 | ((sd->sensor_addr & 0x08) ? 0x0015 : 0x0);
278 data[2] |= (sd->sensor_addr & 0x04) ? 0x0540 : 0x0;
279 data[2] |= (sd->sensor_addr & 0x02) ? 0x5000 : 0x0;
280 data[3] = 0x1d20 | ((sd->sensor_addr & 0x02) ? 0x0001 : 0x0);
281 data[3] |= (sd->sensor_addr & 0x01) ? 0x0054 : 0x0;
282
283 ret += w9968cf_write_fsb(sd, data);
284
285 data[0] = 0x8208 | ((reg & 0x80) ? 0x0015 : 0x0);
286 data[0] |= (reg & 0x40) ? 0x0540 : 0x0;
287 data[0] |= (reg & 0x20) ? 0x5000 : 0x0;
288 data[1] = 0x0820 | ((reg & 0x20) ? 0x0001 : 0x0);
289 data[1] |= (reg & 0x10) ? 0x0054 : 0x0;
290 data[1] |= (reg & 0x08) ? 0x1500 : 0x0;
291 data[1] |= (reg & 0x04) ? 0x4000 : 0x0;
292 data[2] = 0x2082 | ((reg & 0x04) ? 0x0005 : 0x0);
293 data[2] |= (reg & 0x02) ? 0x0150 : 0x0;
294 data[2] |= (reg & 0x01) ? 0x5400 : 0x0;
295 data[3] = 0x001d;
296
297 ret += w9968cf_write_fsb(sd, data);
298
299 data[0] = 0x8208 | ((value & 0x80) ? 0x0015 : 0x0);
300 data[0] |= (value & 0x40) ? 0x0540 : 0x0;
301 data[0] |= (value & 0x20) ? 0x5000 : 0x0;
302 data[1] = 0x0820 | ((value & 0x20) ? 0x0001 : 0x0);
303 data[1] |= (value & 0x10) ? 0x0054 : 0x0;
304 data[1] |= (value & 0x08) ? 0x1500 : 0x0;
305 data[1] |= (value & 0x04) ? 0x4000 : 0x0;
306 data[2] = 0x2082 | ((value & 0x04) ? 0x0005 : 0x0);
307 data[2] |= (value & 0x02) ? 0x0150 : 0x0;
308 data[2] |= (value & 0x01) ? 0x5400 : 0x0;
309 data[3] = 0xfe1d;
310
311 ret += w9968cf_write_fsb(sd, data);
312
313 if (!ret)
314 PDEBUG(D_USBO, "i2c 0x%02x -> [0x%02x]", value, reg);
315 else
316 PDEBUG(D_ERR, "i2c 0x%02x -> [0x%02x] failed", value, reg);
317
318 return ret;
319 }
320
321 /* SMBus protocol: S Addr Wr [A] Subaddr [A] P S Addr+1 Rd [A] [Value] NA P */
322 static int w9968cf_i2c_r(struct sd *sd, u8 reg)
323 {
324 int ret = 0;
325 u8 value;
326
327 /* Fast serial bus data control disable */
328 ret += w9968cf_write_sb(sd, 0x0013); /* don't change ! */
329
330 ret += w9968cf_smbus_start(sd);
331 ret += w9968cf_smbus_write_byte(sd, sd->sensor_addr);
332 ret += w9968cf_smbus_read_ack(sd);
333 ret += w9968cf_smbus_write_byte(sd, reg);
334 ret += w9968cf_smbus_read_ack(sd);
335 ret += w9968cf_smbus_stop(sd);
336 ret += w9968cf_smbus_start(sd);
337 ret += w9968cf_smbus_write_byte(sd, sd->sensor_addr + 1);
338 ret += w9968cf_smbus_read_ack(sd);
339 ret += w9968cf_smbus_read_byte(sd, &value);
340 /* signal we don't want to read anymore, the v4l1 driver used to
341 send an ack here which is very wrong! (and then fixed
342 the issues this gave by retrying reads) */
343 ret += w9968cf_smbus_write_nack(sd);
344 ret += w9968cf_smbus_stop(sd);
345
346 /* Fast serial bus data control re-enable */
347 ret += w9968cf_write_sb(sd, 0x0030);
348
349 if (!ret) {
350 ret = value;
351 PDEBUG(D_USBI, "i2c [0x%02X] -> 0x%02X", reg, value);
352 } else
353 PDEBUG(D_ERR, "i2c read [0x%02x] failed", reg);
354
355 return ret;
356 }
357
358
359 /*--------------------------------------------------------------------------
360 Turn on the LED on some webcams. A beep should be heard too.
361 Return 0 on success, a negative number otherwise.
362 --------------------------------------------------------------------------*/
363 static int w9968cf_configure(struct sd *sd)
364 {
365 int ret = 0;
366
367 ret += reg_w(sd, 0x00, 0xff00); /* power-down */
368 ret += reg_w(sd, 0x00, 0xbf17); /* reset everything */
369 ret += reg_w(sd, 0x00, 0xbf10); /* normal operation */
370 ret += reg_w(sd, 0x01, 0x0010); /* serial bus, SDS high */
371 ret += reg_w(sd, 0x01, 0x0000); /* serial bus, SDS low */
372 ret += reg_w(sd, 0x01, 0x0010); /* ..high 'beep-beep' */
373 ret += reg_w(sd, 0x01, 0x0030); /* Set sda scl to FSB mode */
374
375 if (ret)
376 PDEBUG(D_ERR, "Couldn't turn on the LED");
377
378 sd->stopped = 1;
379
380 return ret;
381 }
382
383 static int w9968cf_init(struct sd *sd)
384 {
385 int ret = 0;
386 unsigned long hw_bufsize = sd->sif ? (352 * 288 * 2) : (640 * 480 * 2),
387 y0 = 0x0000,
388 u0 = y0 + hw_bufsize/2,
389 v0 = u0 + hw_bufsize/4,
390 y1 = v0 + hw_bufsize/4,
391 u1 = y1 + hw_bufsize/2,
392 v1 = u1 + hw_bufsize/4;
393
394 ret += reg_w(sd, 0x00, 0xff00); /* power off */
395 ret += reg_w(sd, 0x00, 0xbf10); /* power on */
396
397 ret += reg_w(sd, 0x03, 0x405d); /* DRAM timings */
398 ret += reg_w(sd, 0x04, 0x0030); /* SDRAM timings */
399
400 ret += reg_w(sd, 0x20, y0 & 0xffff); /* Y buf.0, low */
401 ret += reg_w(sd, 0x21, y0 >> 16); /* Y buf.0, high */
402 ret += reg_w(sd, 0x24, u0 & 0xffff); /* U buf.0, low */
403 ret += reg_w(sd, 0x25, u0 >> 16); /* U buf.0, high */
404 ret += reg_w(sd, 0x28, v0 & 0xffff); /* V buf.0, low */
405 ret += reg_w(sd, 0x29, v0 >> 16); /* V buf.0, high */
406
407 ret += reg_w(sd, 0x22, y1 & 0xffff); /* Y buf.1, low */
408 ret += reg_w(sd, 0x23, y1 >> 16); /* Y buf.1, high */
409 ret += reg_w(sd, 0x26, u1 & 0xffff); /* U buf.1, low */
410 ret += reg_w(sd, 0x27, u1 >> 16); /* U buf.1, high */
411 ret += reg_w(sd, 0x2a, v1 & 0xffff); /* V buf.1, low */
412 ret += reg_w(sd, 0x2b, v1 >> 16); /* V buf.1, high */
413
414 ret += reg_w(sd, 0x32, y1 & 0xffff); /* JPEG buf 0 low */
415 ret += reg_w(sd, 0x33, y1 >> 16); /* JPEG buf 0 high */
416
417 ret += reg_w(sd, 0x34, y1 & 0xffff); /* JPEG buf 1 low */
418 ret += reg_w(sd, 0x35, y1 >> 16); /* JPEG bug 1 high */
419
420 ret += reg_w(sd, 0x36, 0x0000);/* JPEG restart interval */
421 ret += reg_w(sd, 0x37, 0x0804);/*JPEG VLE FIFO threshold*/
422 ret += reg_w(sd, 0x38, 0x0000);/* disable hw up-scaling */
423 ret += reg_w(sd, 0x3f, 0x0000); /* JPEG/MCTL test data */
424
425 return ret;
426 }
427
428 static int w9968cf_set_crop_window(struct sd *sd)
429 {
430 int ret = 0, start_cropx, start_cropy, x, y, fw, fh, cw, ch,
431 max_width, max_height;
432
433 if (sd->sif) {
434 max_width = 352;
435 max_height = 288;
436 } else {
437 max_width = 640;
438 max_height = 480;
439 }
440
441 if (sd->sensor == SEN_OV7620) {
442 /* Sigh, this is dependend on the clock / framerate changes
443 made by the frequency control, sick. */
444 if (sd->freq == 1) {
445 start_cropx = 277;
446 start_cropy = 37;
447 } else {
448 start_cropx = 105;
449 start_cropy = 37;
450 }
451 } else {
452 start_cropx = 320;
453 start_cropy = 35;
454 }
455
456 /* Work around to avoid FP arithmetics */
457 #define SC(x) ((x) << 10)
458
459 /* Scaling factors */
460 fw = SC(sd->gspca_dev.width) / max_width;
461 fh = SC(sd->gspca_dev.height) / max_height;
462
463 cw = (fw >= fh) ? max_width : SC(sd->gspca_dev.width)/fh;
464 ch = (fw >= fh) ? SC(sd->gspca_dev.height)/fw : max_height;
465
466 sd->sensor_width = max_width;
467 sd->sensor_height = max_height;
468
469 x = (max_width - cw) / 2;
470 y = (max_height - ch) / 2;
471
472 ret += reg_w(sd, 0x10, start_cropx + x);
473 ret += reg_w(sd, 0x11, start_cropy + y);
474 ret += reg_w(sd, 0x12, start_cropx + x + cw);
475 ret += reg_w(sd, 0x13, start_cropy + y + ch);
476
477 return ret;
478 }
479
480 static int w9968cf_mode_init_regs(struct sd *sd)
481 {
482 int ret = 0, val, vs_polarity, hs_polarity;
483
484 ret += w9968cf_set_crop_window(sd);
485
486 ret += reg_w(sd, 0x14, sd->gspca_dev.width);
487 ret += reg_w(sd, 0x15, sd->gspca_dev.height);
488
489 /* JPEG width & height */
490 ret += reg_w(sd, 0x30, sd->gspca_dev.width);
491 ret += reg_w(sd, 0x31, sd->gspca_dev.height);
492
493 /* Y & UV frame buffer strides (in WORD) */
494 if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
495 V4L2_PIX_FMT_JPEG) {
496 ret += reg_w(sd, 0x2c, sd->gspca_dev.width/2);
497 ret += reg_w(sd, 0x2d, sd->gspca_dev.width/4);
498 } else
499 ret += reg_w(sd, 0x2c, sd->gspca_dev.width);
500
501 ret += reg_w(sd, 0x00, 0xbf17); /* reset everything */
502 ret += reg_w(sd, 0x00, 0xbf10); /* normal operation */
503
504 /* Transfer size in WORDS (for UYVY format only) */
505 val = sd->gspca_dev.width * sd->gspca_dev.height;
506 ret += reg_w(sd, 0x3d, val & 0xffff); /* low bits */
507 ret += reg_w(sd, 0x3e, val >> 16); /* high bits */
508
509 if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
510 V4L2_PIX_FMT_JPEG) {
511 /* We may get called multiple times (usb isoc bw negotiat.) */
512 if (!sd->jpeg_hdr)
513 sd->jpeg_hdr = kmalloc(JPEG_HDR_SZ, GFP_KERNEL);
514 if (!sd->jpeg_hdr)
515 return -ENOMEM;
516
517 jpeg_define(sd->jpeg_hdr, sd->gspca_dev.height,
518 sd->gspca_dev.width, 0x22); /* JPEG 420 */
519 jpeg_set_qual(sd->jpeg_hdr, sd->quality);
520 ret += w9968cf_upload_quantizationtables(sd);
521 }
522
523 /* Video Capture Control Register */
524 if (sd->sensor == SEN_OV7620) {
525 /* Seems to work around a bug in the image sensor */
526 vs_polarity = 1;
527 hs_polarity = 1;
528 } else {
529 vs_polarity = 1;
530 hs_polarity = 0;
531 }
532
533 val = (vs_polarity << 12) | (hs_polarity << 11);
534
535 /* NOTE: We may not have enough memory to do double buffering while
536 doing compression (amount of memory differs per model cam).
537 So we use the second image buffer also as jpeg stream buffer
538 (see w9968cf_init), and disable double buffering. */
539 if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
540 V4L2_PIX_FMT_JPEG) {
541 /* val |= 0x0002; YUV422P */
542 val |= 0x0003; /* YUV420P */
543 } else
544 val |= 0x0080; /* Enable HW double buffering */
545
546 /* val |= 0x0020; enable clamping */
547 /* val |= 0x0008; enable (1-2-1) filter */
548 /* val |= 0x000c; enable (2-3-6-3-2) filter */
549
550 val |= 0x8000; /* capt. enable */
551
552 ret += reg_w(sd, 0x16, val);
553
554 sd->gspca_dev.empty_packet = 0;
555
556 return ret;
557 }
558
559 static void w9968cf_stop0(struct sd *sd)
560 {
561 if (sd->gspca_dev.present) {
562 reg_w(sd, 0x39, 0x0000); /* disable JPEG encoder */
563 reg_w(sd, 0x16, 0x0000); /* stop video capture */
564 }
565
566 kfree(sd->jpeg_hdr);
567 sd->jpeg_hdr = NULL;
568 }
569
570 /* The w9968cf docs say that a 0 sized packet means EOF (and also SOF
571 for the next frame). This seems to simply not be true when operating
572 in JPEG mode, in this case there may be empty packets within the
573 frame. So in JPEG mode use the JPEG SOI marker to detect SOF.
574
575 Note to make things even more interesting the w9968cf sends *PLANAR* jpeg,
576 to be precise it sends: SOI, SOF, DRI, SOS, Y-data, SOS, U-data, SOS,
577 V-data, EOI. */
578 static void w9968cf_pkt_scan(struct gspca_dev *gspca_dev,
579 u8 *data, /* isoc packet */
580 int len) /* iso packet length */
581 {
582 struct sd *sd = (struct sd *) gspca_dev;
583
584 if (w9968cf_vga_mode[gspca_dev->curr_mode].pixelformat ==
585 V4L2_PIX_FMT_JPEG) {
586 if (len >= 2 &&
587 data[0] == 0xff &&
588 data[1] == 0xd8) {
589 gspca_frame_add(gspca_dev, LAST_PACKET,
590 NULL, 0);
591 gspca_frame_add(gspca_dev, FIRST_PACKET,
592 sd->jpeg_hdr, JPEG_HDR_SZ);
593 /* Strip the ff d8, our own header (which adds
594 huffman and quantization tables) already has this */
595 len -= 2;
596 data += 2;
597 }
598 } else {
599 /* In UYVY mode an empty packet signals EOF */
600 if (gspca_dev->empty_packet) {
601 gspca_frame_add(gspca_dev, LAST_PACKET,
602 NULL, 0);
603 gspca_frame_add(gspca_dev, FIRST_PACKET,
604 NULL, 0);
605 gspca_dev->empty_packet = 0;
606 }
607 }
608 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
609 }