drivers/mfd/mc13783-core.c

   1 /*
   2  * Copyright 2009 Pengutronix
   3  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
   4  *
   5  * loosely based on an earlier driver that has
   6  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it under
   9  * the terms of the GNU General Public License version 2 as published by the
  10  * Free Software Foundation.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/mfd/core.h>
  15 #include <linux/mfd/mc13783-private.h>
  16
  17 #define MC13783_IRQSTAT0        0
  18 #define MC13783_IRQSTAT0_ADCDONEI       (1 << 0)
  19 #define MC13783_IRQSTAT0_ADCBISDONEI    (1 << 1)
  20 #define MC13783_IRQSTAT0_TSI            (1 << 2)
  21 #define MC13783_IRQSTAT0_WHIGHI         (1 << 3)
  22 #define MC13783_IRQSTAT0_WLOWI          (1 << 4)
  23 #define MC13783_IRQSTAT0_CHGDETI        (1 << 6)
  24 #define MC13783_IRQSTAT0_CHGOVI         (1 << 7)
  25 #define MC13783_IRQSTAT0_CHGREVI        (1 << 8)
  26 #define MC13783_IRQSTAT0_CHGSHORTI      (1 << 9)
  27 #define MC13783_IRQSTAT0_CCCVI          (1 << 10)
  28 #define MC13783_IRQSTAT0_CHGCURRI       (1 << 11)
  29 #define MC13783_IRQSTAT0_BPONI          (1 << 12)
  30 #define MC13783_IRQSTAT0_LOBATLI        (1 << 13)
  31 #define MC13783_IRQSTAT0_LOBATHI        (1 << 14)
  32 #define MC13783_IRQSTAT0_UDPI           (1 << 15)
  33 #define MC13783_IRQSTAT0_USBI           (1 << 16)
  34 #define MC13783_IRQSTAT0_IDI            (1 << 19)
  35 #define MC13783_IRQSTAT0_SE1I           (1 << 21)
  36 #define MC13783_IRQSTAT0_CKDETI         (1 << 22)
  37 #define MC13783_IRQSTAT0_UDMI           (1 << 23)
  38
  39 #define MC13783_IRQMASK0        1
  40 #define MC13783_IRQMASK0_ADCDONEM       MC13783_IRQSTAT0_ADCDONEI
  41 #define MC13783_IRQMASK0_ADCBISDONEM    MC13783_IRQSTAT0_ADCBISDONEI
  42 #define MC13783_IRQMASK0_TSM            MC13783_IRQSTAT0_TSI
  43 #define MC13783_IRQMASK0_WHIGHM         MC13783_IRQSTAT0_WHIGHI
  44 #define MC13783_IRQMASK0_WLOWM          MC13783_IRQSTAT0_WLOWI
  45 #define MC13783_IRQMASK0_CHGDETM        MC13783_IRQSTAT0_CHGDETI
  46 #define MC13783_IRQMASK0_CHGOVM         MC13783_IRQSTAT0_CHGOVI
  47 #define MC13783_IRQMASK0_CHGREVM        MC13783_IRQSTAT0_CHGREVI
  48 #define MC13783_IRQMASK0_CHGSHORTM      MC13783_IRQSTAT0_CHGSHORTI
  49 #define MC13783_IRQMASK0_CCCVM          MC13783_IRQSTAT0_CCCVI
  50 #define MC13783_IRQMASK0_CHGCURRM       MC13783_IRQSTAT0_CHGCURRI
  51 #define MC13783_IRQMASK0_BPONM          MC13783_IRQSTAT0_BPONI
  52 #define MC13783_IRQMASK0_LOBATLM        MC13783_IRQSTAT0_LOBATLI
  53 #define MC13783_IRQMASK0_LOBATHM        MC13783_IRQSTAT0_LOBATHI
  54 #define MC13783_IRQMASK0_UDPM           MC13783_IRQSTAT0_UDPI
  55 #define MC13783_IRQMASK0_USBM           MC13783_IRQSTAT0_USBI
  56 #define MC13783_IRQMASK0_IDM            MC13783_IRQSTAT0_IDI
  57 #define MC13783_IRQMASK0_SE1M           MC13783_IRQSTAT0_SE1I
  58 #define MC13783_IRQMASK0_CKDETM         MC13783_IRQSTAT0_CKDETI
  59 #define MC13783_IRQMASK0_UDMM           MC13783_IRQSTAT0_UDMI
  60
  61 #define MC13783_IRQSTAT1        3
  62 #define MC13783_IRQSTAT1_1HZI           (1 << 0)
  63 #define MC13783_IRQSTAT1_TODAI          (1 << 1)
  64 #define MC13783_IRQSTAT1_ONOFD1I        (1 << 3)
  65 #define MC13783_IRQSTAT1_ONOFD2I        (1 << 4)
  66 #define MC13783_IRQSTAT1_ONOFD3I        (1 << 5)
  67 #define MC13783_IRQSTAT1_SYSRSTI        (1 << 6)
  68 #define MC13783_IRQSTAT1_RTCRSTI        (1 << 7)
  69 #define MC13783_IRQSTAT1_PCI            (1 << 8)
  70 #define MC13783_IRQSTAT1_WARMI          (1 << 9)
  71 #define MC13783_IRQSTAT1_MEMHLDI        (1 << 10)
  72 #define MC13783_IRQSTAT1_PWRRDYI        (1 << 11)
  73 #define MC13783_IRQSTAT1_THWARNLI       (1 << 12)
  74 #define MC13783_IRQSTAT1_THWARNHI       (1 << 13)
  75 #define MC13783_IRQSTAT1_CLKI           (1 << 14)
  76 #define MC13783_IRQSTAT1_SEMAFI         (1 << 15)
  77 #define MC13783_IRQSTAT1_MC2BI          (1 << 17)
  78 #define MC13783_IRQSTAT1_HSDETI         (1 << 18)
  79 #define MC13783_IRQSTAT1_HSLI           (1 << 19)
  80 #define MC13783_IRQSTAT1_ALSPTHI        (1 << 20)
  81 #define MC13783_IRQSTAT1_AHSSHORTI      (1 << 21)
  82
  83 #define MC13783_IRQMASK1        4
  84 #define MC13783_IRQMASK1_1HZM           MC13783_IRQSTAT1_1HZI
  85 #define MC13783_IRQMASK1_TODAM          MC13783_IRQSTAT1_TODAI
  86 #define MC13783_IRQMASK1_ONOFD1M        MC13783_IRQSTAT1_ONOFD1I
  87 #define MC13783_IRQMASK1_ONOFD2M        MC13783_IRQSTAT1_ONOFD2I
  88 #define MC13783_IRQMASK1_ONOFD3M        MC13783_IRQSTAT1_ONOFD3I
  89 #define MC13783_IRQMASK1_SYSRSTM        MC13783_IRQSTAT1_SYSRSTI
  90 #define MC13783_IRQMASK1_RTCRSTM        MC13783_IRQSTAT1_RTCRSTI
  91 #define MC13783_IRQMASK1_PCM            MC13783_IRQSTAT1_PCI
  92 #define MC13783_IRQMASK1_WARMM          MC13783_IRQSTAT1_WARMI
  93 #define MC13783_IRQMASK1_MEMHLDM        MC13783_IRQSTAT1_MEMHLDI
  94 #define MC13783_IRQMASK1_PWRRDYM        MC13783_IRQSTAT1_PWRRDYI
  95 #define MC13783_IRQMASK1_THWARNLM       MC13783_IRQSTAT1_THWARNLI
  96 #define MC13783_IRQMASK1_THWARNHM       MC13783_IRQSTAT1_THWARNHI
  97 #define MC13783_IRQMASK1_CLKM           MC13783_IRQSTAT1_CLKI
  98 #define MC13783_IRQMASK1_SEMAFM         MC13783_IRQSTAT1_SEMAFI
  99 #define MC13783_IRQMASK1_MC2BM          MC13783_IRQSTAT1_MC2BI
 100 #define MC13783_IRQMASK1_HSDETM         MC13783_IRQSTAT1_HSDETI
 101 #define MC13783_IRQMASK1_HSLM           MC13783_IRQSTAT1_HSLI
 102 #define MC13783_IRQMASK1_ALSPTHM        MC13783_IRQSTAT1_ALSPTHI
 103 #define MC13783_IRQMASK1_AHSSHORTM      MC13783_IRQSTAT1_AHSSHORTI
 104
 105 #define MC13783_ADC1            44
 106 #define MC13783_ADC1_ADEN               (1 << 0)
 107 #define MC13783_ADC1_RAND               (1 << 1)
 108 #define MC13783_ADC1_ADSEL              (1 << 3)
 109 #define MC13783_ADC1_ASC                (1 << 20)
 110 #define MC13783_ADC1_ADTRIGIGN          (1 << 21)
 111
 112 #define MC13783_NUMREGS 0x3f
 113
 114 void mc13783_lock(struct mc13783 *mc13783)
 115 {
 116         if (!mutex_trylock(&mc13783->lock)) {
 117                 dev_dbg(&mc13783->spidev->dev, "wait for %s from %pf\n",
 118                                 __func__, __builtin_return_address(0));
 119
 120                 mutex_lock(&mc13783->lock);
 121         }
 122         dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
 123                         __func__, __builtin_return_address(0));
 124 }
 125 EXPORT_SYMBOL(mc13783_lock);
 126
 127 void mc13783_unlock(struct mc13783 *mc13783)
 128 {
 129         dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
 130                         __func__, __builtin_return_address(0));
 131         mutex_unlock(&mc13783->lock);
 132 }
 133 EXPORT_SYMBOL(mc13783_unlock);
 134
 135 #define MC13783_REGOFFSET_SHIFT 25
 136 int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val)
 137 {
 138         struct spi_transfer t;
 139         struct spi_message m;
 140         int ret;
 141
 142         BUG_ON(!mutex_is_locked(&mc13783->lock));
 143
 144         if (offset > MC13783_NUMREGS)
 145                 return -EINVAL;
 146
 147         *val = offset << MC13783_REGOFFSET_SHIFT;
 148
 149         memset(&t, 0, sizeof(t));
 150
 151         t.tx_buf = val;
 152         t.rx_buf = val;
 153         t.len = sizeof(u32);
 154
 155         spi_message_init(&m);
 156         spi_message_add_tail(&t, &m);
 157
 158         ret = spi_sync(mc13783->spidev, &m);
 159
 160         /* error in message.status implies error return from spi_sync */
 161         BUG_ON(!ret && m.status);
 162
 163         if (ret)
 164                 return ret;
 165
 166         *val &= 0xffffff;
 167
 168         dev_vdbg(&mc13783->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
 169
 170         return 0;
 171 }
 172 EXPORT_SYMBOL(mc13783_reg_read);
 173
 174 int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val)
 175 {
 176         u32 buf;
 177         struct spi_transfer t;
 178         struct spi_message m;
 179         int ret;
 180
 181         BUG_ON(!mutex_is_locked(&mc13783->lock));
 182
 183         dev_vdbg(&mc13783->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
 184
 185         if (offset > MC13783_NUMREGS || val > 0xffffff)
 186                 return -EINVAL;
 187
 188         buf = 1 << 31 | offset << MC13783_REGOFFSET_SHIFT | val;
 189
 190         memset(&t, 0, sizeof(t));
 191
 192         t.tx_buf = &buf;
 193         t.rx_buf = &buf;
 194         t.len = sizeof(u32);
 195
 196         spi_message_init(&m);
 197         spi_message_add_tail(&t, &m);
 198
 199         ret = spi_sync(mc13783->spidev, &m);
 200
 201         BUG_ON(!ret && m.status);
 202
 203         if (ret)
 204                 return ret;
 205
 206         return 0;
 207 }
 208 EXPORT_SYMBOL(mc13783_reg_write);
 209
 210 int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
 211                 u32 mask, u32 val)
 212 {
 213         int ret;
 214         u32 valread;
 215
 216         BUG_ON(val & ~mask);
 217
 218         ret = mc13783_reg_read(mc13783, offset, &valread);
 219         if (ret)
 220                 return ret;
 221
 222         valread = (valread & ~mask) | val;
 223
 224         return mc13783_reg_write(mc13783, offset, valread);
 225 }
 226 EXPORT_SYMBOL(mc13783_reg_rmw);
 227
 228 int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
 229 {
 230         int ret;
 231         unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
 232         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 233         u32 mask;
 234
 235         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 236                 return -EINVAL;
 237
 238         ret = mc13783_reg_read(mc13783, offmask, &mask);
 239         if (ret)
 240                 return ret;
 241
 242         if (mask & irqbit)
 243                 /* already masked */
 244                 return 0;
 245
 246         return mc13783_reg_write(mc13783, offmask, mask | irqbit);
 247 }
 248 EXPORT_SYMBOL(mc13783_irq_mask);
 249
 250 int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
 251 {
 252         int ret;
 253         unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
 254         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 255         u32 mask;
 256
 257         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 258                 return -EINVAL;
 259
 260         ret = mc13783_reg_read(mc13783, offmask, &mask);
 261         if (ret)
 262                 return ret;
 263
 264         if (!(mask & irqbit))
 265                 /* already unmasked */
 266                 return 0;
 267
 268         return mc13783_reg_write(mc13783, offmask, mask & ~irqbit);
 269 }
 270 EXPORT_SYMBOL(mc13783_irq_unmask);
 271
 272 int mc13783_irq_status(struct mc13783 *mc13783, int irq,
 273                 int *enabled, int *pending)
 274 {
 275         int ret;
 276         unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
 277         unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
 278         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 279
 280         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 281                 return -EINVAL;
 282
 283         if (enabled) {
 284                 u32 mask;
 285
 286                 ret = mc13783_reg_read(mc13783, offmask, &mask);
 287                 if (ret)
 288                         return ret;
 289
 290                 *enabled = mask & irqbit;
 291         }
 292
 293         if (pending) {
 294                 u32 stat;
 295
 296                 ret = mc13783_reg_read(mc13783, offstat, &stat);
 297                 if (ret)
 298                         return ret;
 299
 300                 *pending = stat & irqbit;
 301         }
 302
 303         return 0;
 304 }
 305 EXPORT_SYMBOL(mc13783_irq_status);
 306
 307 int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
 308 {
 309         unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
 310         unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
 311
 312         BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ);
 313
 314         return mc13783_reg_write(mc13783, offstat, val);
 315 }
 316 EXPORT_SYMBOL(mc13783_irq_ack);
 317
 318 int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
 319                 irq_handler_t handler, const char *name, void *dev)
 320 {
 321         BUG_ON(!mutex_is_locked(&mc13783->lock));
 322         BUG_ON(!handler);
 323
 324         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 325                 return -EINVAL;
 326
 327         if (mc13783->irqhandler[irq])
 328                 return -EBUSY;
 329
 330         mc13783->irqhandler[irq] = handler;
 331         mc13783->irqdata[irq] = dev;
 332
 333         return 0;
 334 }
 335 EXPORT_SYMBOL(mc13783_irq_request_nounmask);
 336
 337 int mc13783_irq_request(struct mc13783 *mc13783, int irq,
 338                 irq_handler_t handler, const char *name, void *dev)
 339 {
 340         int ret;
 341
 342         ret = mc13783_irq_request_nounmask(mc13783, irq, handler, name, dev);
 343         if (ret)
 344                 return ret;
 345
 346         ret = mc13783_irq_unmask(mc13783, irq);
 347         if (ret) {
 348                 mc13783->irqhandler[irq] = NULL;
 349                 mc13783->irqdata[irq] = NULL;
 350                 return ret;
 351         }
 352
 353         return 0;
 354 }
 355 EXPORT_SYMBOL(mc13783_irq_request);
 356
 357 int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
 358 {
 359         int ret;
 360         BUG_ON(!mutex_is_locked(&mc13783->lock));
 361
 362         if (irq < 0 || irq >= MC13783_NUM_IRQ || !mc13783->irqhandler[irq] ||
 363                         mc13783->irqdata[irq] != dev)
 364                 return -EINVAL;
 365
 366         ret = mc13783_irq_mask(mc13783, irq);
 367         if (ret)
 368                 return ret;
 369
 370         mc13783->irqhandler[irq] = NULL;
 371         mc13783->irqdata[irq] = NULL;
 372
 373         return 0;
 374 }
 375 EXPORT_SYMBOL(mc13783_irq_free);
 376
 377 static inline irqreturn_t mc13783_irqhandler(struct mc13783 *mc13783, int irq)
 378 {
 379         return mc13783->irqhandler[irq](irq, mc13783->irqdata[irq]);
 380 }
 381
 382 /*
 383  * returns: number of handled irqs or negative error
 384  * locking: holds mc13783->lock
 385  */
 386 static int mc13783_irq_handle(struct mc13783 *mc13783,
 387                 unsigned int offstat, unsigned int offmask, int baseirq)
 388 {
 389         u32 stat, mask;
 390         int ret = mc13783_reg_read(mc13783, offstat, &stat);
 391         int num_handled = 0;
 392
 393         if (ret)
 394                 return ret;
 395
 396         ret = mc13783_reg_read(mc13783, offmask, &mask);
 397         if (ret)
 398                 return ret;
 399
 400         while (stat & ~mask) {
 401                 int irq = __ffs(stat & ~mask);
 402
 403                 stat &= ~(1 << irq);
 404
 405                 if (likely(mc13783->irqhandler[baseirq + irq])) {
 406                         irqreturn_t handled;
 407
 408                         handled = mc13783_irqhandler(mc13783, baseirq + irq);
 409                         if (handled == IRQ_HANDLED)
 410                                 num_handled++;
 411                 } else {
 412                         dev_err(&mc13783->spidev->dev,
 413                                         "BUG: irq %u but no handler\n",
 414                                         baseirq + irq);
 415
 416                         mask |= 1 << irq;
 417
 418                         ret = mc13783_reg_write(mc13783, offmask, mask);
 419                 }
 420         }
 421
 422         return num_handled;
 423 }
 424
 425 static irqreturn_t mc13783_irq_thread(int irq, void *data)
 426 {
 427         struct mc13783 *mc13783 = data;
 428         irqreturn_t ret;
 429         int handled = 0;
 430
 431         mc13783_lock(mc13783);
 432
 433         ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT0,
 434                         MC13783_IRQMASK0, MC13783_IRQ_ADCDONE);
 435         if (ret > 0)
 436                 handled = 1;
 437
 438         ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT1,
 439                         MC13783_IRQMASK1, MC13783_IRQ_1HZ);
 440         if (ret > 0)
 441                 handled = 1;
 442
 443         mc13783_unlock(mc13783);
 444
 445         return IRQ_RETVAL(handled);
 446 }
 447
 448 #define MC13783_ADC1_CHAN0_SHIFT        5
 449 #define MC13783_ADC1_CHAN1_SHIFT        8
 450
 451 struct mc13783_adcdone_data {
 452         struct mc13783 *mc13783;
 453         struct completion done;
 454 };
 455
 456 static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
 457 {
 458         struct mc13783_adcdone_data *adcdone_data = data;
 459
 460         mc13783_irq_ack(adcdone_data->mc13783, irq);
 461
 462         complete_all(&adcdone_data->done);
 463
 464         return IRQ_HANDLED;
 465 }
 466
 467 #define MC13783_ADC_WORKING (1 << 16)
 468
 469 int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
 470                 unsigned int channel, unsigned int *sample)
 471 {
 472         u32 adc0, adc1, old_adc0;
 473         int i, ret;
 474         struct mc13783_adcdone_data adcdone_data = {
 475                 .mc13783 = mc13783,
 476         };
 477         init_completion(&adcdone_data.done);
 478
 479         dev_dbg(&mc13783->spidev->dev, "%s\n", __func__);
 480
 481         mc13783_lock(mc13783);
 482
 483         if (mc13783->flags & MC13783_ADC_WORKING) {
 484                 ret = -EBUSY;
 485                 goto out;
 486         }
 487
 488         mc13783->flags |= MC13783_ADC_WORKING;
 489
 490         mc13783_reg_read(mc13783, MC13783_ADC0, &old_adc0);
 491
 492         adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
 493         adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
 494
 495         if (channel > 7)
 496                 adc1 |= MC13783_ADC1_ADSEL;
 497
 498         switch (mode) {
 499         case MC13783_ADC_MODE_TS:
 500                 adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
 501                         MC13783_ADC0_TSMOD1;
 502                 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
 503                 break;
 504
 505         case MC13783_ADC_MODE_SINGLE_CHAN:
 506                 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
 507                 adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
 508                 adc1 |= MC13783_ADC1_RAND;
 509                 break;
 510
 511         case MC13783_ADC_MODE_MULT_CHAN:
 512                 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
 513                 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
 514                 break;
 515
 516         default:
 517                 mc13783_unlock(mc13783);
 518                 return -EINVAL;
 519         }
 520
 521         dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__);
 522         mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE,
 523                         mc13783_handler_adcdone, __func__, &adcdone_data);
 524         mc13783_irq_ack(mc13783, MC13783_IRQ_ADCDONE);
 525
 526         mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0);
 527         mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1);
 528
 529         mc13783_unlock(mc13783);
 530
 531         ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
 532
 533         if (!ret)
 534                 ret = -ETIMEDOUT;
 535
 536         mc13783_lock(mc13783);
 537
 538         mc13783_irq_free(mc13783, MC13783_IRQ_ADCDONE, &adcdone_data);
 539
 540         if (ret > 0)
 541                 for (i = 0; i < 4; ++i) {
 542                         ret = mc13783_reg_read(mc13783,
 543                                         MC13783_REG_ADC_2, &sample[i]);
 544                         if (ret)
 545                                 break;
 546                 }
 547
 548         if (mode == MC13783_ADC_MODE_TS)
 549                 /* restore TSMOD */
 550                 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, old_adc0);
 551
 552         mc13783->flags &= ~MC13783_ADC_WORKING;
 553 out:
 554         mc13783_unlock(mc13783);
 555
 556         return ret;
 557 }
 558 EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
 559
 560 static int mc13783_add_subdevice_pdata(struct mc13783 *mc13783,
 561                 const char *name, void *pdata, size_t pdata_size)
 562 {
 563         struct mfd_cell cell = {
 564                 .name = name,
 565                 .platform_data = pdata,
 566                 .data_size = pdata_size,
 567         };
 568
 569         return mfd_add_devices(&mc13783->spidev->dev, -1, &cell, 1, NULL, 0);
 570 }
 571
 572 static int mc13783_add_subdevice(struct mc13783 *mc13783, const char *name)
 573 {
 574         return mc13783_add_subdevice_pdata(mc13783, name, NULL, 0);
 575 }
 576
 577 static int mc13783_check_revision(struct mc13783 *mc13783)
 578 {
 579         u32 rev_id, rev1, rev2, finid, icid;
 580
 581         mc13783_reg_read(mc13783, MC13783_REG_REVISION, &rev_id);
 582
 583         rev1 = (rev_id & 0x018) >> 3;
 584         rev2 = (rev_id & 0x007);
 585         icid = (rev_id & 0x01C0) >> 6;
 586         finid = (rev_id & 0x01E00) >> 9;
 587
 588         /* Ver 0.2 is actually 3.2a.  Report as 3.2 */
 589         if ((rev1 == 0) && (rev2 == 2))
 590                 rev1 = 3;
 591
 592         if (rev1 == 0 || icid != 2) {
 593                 dev_err(&mc13783->spidev->dev, "No MC13783 detected.\n");
 594                 return -ENODEV;
 595         }
 596
 597         dev_info(&mc13783->spidev->dev,
 598                         "MC13783 Rev %d.%d FinVer %x detected\n",
 599                         rev1, rev2, finid);
 600
 601         return 0;
 602 }
 603
 604 static int mc13783_probe(struct spi_device *spi)
 605 {
 606         struct mc13783 *mc13783;
 607         struct mc13783_platform_data *pdata = dev_get_platdata(&spi->dev);
 608         int ret;
 609
 610         mc13783 = kzalloc(sizeof(*mc13783), GFP_KERNEL);
 611         if (!mc13783)
 612                 return -ENOMEM;
 613
 614         dev_set_drvdata(&spi->dev, mc13783);
 615         spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
 616         spi->bits_per_word = 32;
 617         spi_setup(spi);
 618
 619         mc13783->spidev = spi;
 620
 621         mutex_init(&mc13783->lock);
 622         mc13783_lock(mc13783);
 623
 624         ret = mc13783_check_revision(mc13783);
 625         if (ret)
 626                 goto err_revision;
 627
 628         /* mask all irqs */
 629         ret = mc13783_reg_write(mc13783, MC13783_IRQMASK0, 0x00ffffff);
 630         if (ret)
 631                 goto err_mask;
 632
 633         ret = mc13783_reg_write(mc13783, MC13783_IRQMASK1, 0x00ffffff);
 634         if (ret)
 635                 goto err_mask;
 636
 637         ret = request_threaded_irq(spi->irq, NULL, mc13783_irq_thread,
 638                         IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13783", mc13783);
 639
 640         if (ret) {
 641 err_mask:
 642 err_revision:
 643                 mutex_unlock(&mc13783->lock);
 644                 dev_set_drvdata(&spi->dev, NULL);
 645                 kfree(mc13783);
 646                 return ret;
 647         }
 648
 649         /* This should go away (BEGIN) */
 650         if (pdata) {
 651                 mc13783->flags = pdata->flags;
 652                 mc13783->regulators = pdata->regulators;
 653                 mc13783->num_regulators = pdata->num_regulators;
 654         }
 655         /* This should go away (END) */
 656
 657         mc13783_unlock(mc13783);
 658
 659         if (pdata->flags & MC13783_USE_ADC)
 660                 mc13783_add_subdevice(mc13783, "mc13783-adc");
 661
 662         if (pdata->flags & MC13783_USE_CODEC)
 663                 mc13783_add_subdevice(mc13783, "mc13783-codec");
 664
 665         if (pdata->flags & MC13783_USE_REGULATOR) {
 666                 struct mc13783_regulator_platform_data regulator_pdata = {
 667                         .num_regulators = pdata->num_regulators,
 668                         .regulators = pdata->regulators,
 669                 };
 670
 671                 mc13783_add_subdevice_pdata(mc13783, "mc13783-regulator",
 672                                 &regulator_pdata, sizeof(regulator_pdata));
 673         }
 674
 675         if (pdata->flags & MC13783_USE_RTC)
 676                 mc13783_add_subdevice(mc13783, "mc13783-rtc");
 677
 678         if (pdata->flags & MC13783_USE_TOUCHSCREEN)
 679                 mc13783_add_subdevice(mc13783, "mc13783-ts");
 680
 681         return 0;
 682 }
 683
 684 static int __devexit mc13783_remove(struct spi_device *spi)
 685 {
 686         struct mc13783 *mc13783 = dev_get_drvdata(&spi->dev);
 687
 688         free_irq(mc13783->spidev->irq, mc13783);
 689
 690         mfd_remove_devices(&spi->dev);
 691
 692         return 0;
 693 }
 694
 695 static struct spi_driver mc13783_driver = {
 696         .driver = {
 697                 .name = "mc13783",
 698                 .bus = &spi_bus_type,
 699                 .owner = THIS_MODULE,
 700         },
 701         .probe = mc13783_probe,
 702         .remove = __devexit_p(mc13783_remove),
 703 };
 704
 705 static int __init mc13783_init(void)
 706 {
 707         return spi_register_driver(&mc13783_driver);
 708 }
 709 subsys_initcall(mc13783_init);
 710
 711 static void __exit mc13783_exit(void)
 712 {
 713         spi_unregister_driver(&mc13783_driver);
 714 }
 715 module_exit(mc13783_exit);
 716
 717 MODULE_DESCRIPTION("Core driver for Freescale MC13783 PMIC");
 718 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
 719 MODULE_LICENSE("GPL v2");