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Linux 2.6.34-rc3
[pohmelfs.git] / drivers / net / sfc / siena.c
blob1619fb5a64f5c0574b3dca25cdb49abd7d5f5571
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include "net_driver.h"
16 #include "bitfield.h"
17 #include "efx.h"
18 #include "nic.h"
19 #include "mac.h"
20 #include "spi.h"
21 #include "regs.h"
22 #include "io.h"
23 #include "phy.h"
24 #include "workarounds.h"
25 #include "mcdi.h"
26 #include "mcdi_pcol.h"
27
28 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
29
30 static void siena_init_wol(struct efx_nic *efx);
31
32
33 static void siena_push_irq_moderation(struct efx_channel *channel)
34 {
35 efx_dword_t timer_cmd;
36
37 if (channel->irq_moderation)
38 EFX_POPULATE_DWORD_2(timer_cmd,
39 FRF_CZ_TC_TIMER_MODE,
40 FFE_CZ_TIMER_MODE_INT_HLDOFF,
41 FRF_CZ_TC_TIMER_VAL,
42 channel->irq_moderation - 1);
43 else
44 EFX_POPULATE_DWORD_2(timer_cmd,
45 FRF_CZ_TC_TIMER_MODE,
46 FFE_CZ_TIMER_MODE_DIS,
47 FRF_CZ_TC_TIMER_VAL, 0);
48 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
49 channel->channel);
50 }
51
52 static void siena_push_multicast_hash(struct efx_nic *efx)
53 {
54 WARN_ON(!mutex_is_locked(&efx->mac_lock));
55
56 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
57 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
58 NULL, 0, NULL);
59 }
60
61 static int siena_mdio_write(struct net_device *net_dev,
62 int prtad, int devad, u16 addr, u16 value)
63 {
64 struct efx_nic *efx = netdev_priv(net_dev);
65 uint32_t status;
66 int rc;
67
68 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
69 addr, value, &status);
70 if (rc)
71 return rc;
72 if (status != MC_CMD_MDIO_STATUS_GOOD)
73 return -EIO;
74
75 return 0;
76 }
77
78 static int siena_mdio_read(struct net_device *net_dev,
79 int prtad, int devad, u16 addr)
80 {
81 struct efx_nic *efx = netdev_priv(net_dev);
82 uint16_t value;
83 uint32_t status;
84 int rc;
85
86 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
87 addr, &value, &status);
88 if (rc)
89 return rc;
90 if (status != MC_CMD_MDIO_STATUS_GOOD)
91 return -EIO;
92
93 return (int)value;
94 }
95
96 /* This call is responsible for hooking in the MAC and PHY operations */
97 static int siena_probe_port(struct efx_nic *efx)
98 {
99 int rc;
100
101 /* Hook in PHY operations table */
102 efx->phy_op = &efx_mcdi_phy_ops;
103
104 /* Set up MDIO structure for PHY */
105 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
106 efx->mdio.mdio_read = siena_mdio_read;
107 efx->mdio.mdio_write = siena_mdio_write;
108
109 /* Fill out MDIO structure, loopback modes, and initial link state */
110 rc = efx->phy_op->probe(efx);
111 if (rc != 0)
112 return rc;
113
114 /* Allocate buffer for stats */
115 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
116 MC_CMD_MAC_NSTATS * sizeof(u64));
117 if (rc)
118 return rc;
119 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
120 (u64)efx->stats_buffer.dma_addr,
121 efx->stats_buffer.addr,
122 (u64)virt_to_phys(efx->stats_buffer.addr));
123
124 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
125
126 return 0;
127 }
128
129 void siena_remove_port(struct efx_nic *efx)
130 {
131 efx->phy_op->remove(efx);
132 efx_nic_free_buffer(efx, &efx->stats_buffer);
133 }
134
135 static const struct efx_nic_register_test siena_register_tests[] = {
136 { FR_AZ_ADR_REGION,
137 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
138 { FR_CZ_USR_EV_CFG,
139 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
140 { FR_AZ_RX_CFG,
141 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
142 { FR_AZ_TX_CFG,
143 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
144 { FR_AZ_TX_RESERVED,
145 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
146 { FR_AZ_SRM_TX_DC_CFG,
147 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
148 { FR_AZ_RX_DC_CFG,
149 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
150 { FR_AZ_RX_DC_PF_WM,
151 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
152 { FR_BZ_DP_CTRL,
153 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
154 { FR_BZ_RX_RSS_TKEY,
155 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
156 { FR_CZ_RX_RSS_IPV6_REG1,
157 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
158 { FR_CZ_RX_RSS_IPV6_REG2,
159 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
160 { FR_CZ_RX_RSS_IPV6_REG3,
161 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
162 };
163
164 static int siena_test_registers(struct efx_nic *efx)
165 {
166 return efx_nic_test_registers(efx, siena_register_tests,
167 ARRAY_SIZE(siena_register_tests));
168 }
169
170 /**************************************************************************
171 *
172 * Device reset
173 *
174 **************************************************************************
175 */
176
177 static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
178 {
179 int rc;
180
181 /* Recover from a failed assertion pre-reset */
182 rc = efx_mcdi_handle_assertion(efx);
183 if (rc)
184 return rc;
185
186 if (method == RESET_TYPE_WORLD)
187 return efx_mcdi_reset_mc(efx);
188 else
189 return efx_mcdi_reset_port(efx);
190 }
191
192 static int siena_probe_nvconfig(struct efx_nic *efx)
193 {
194 int rc;
195
196 rc = efx_mcdi_get_board_cfg(efx, efx->mac_address, NULL);
197 if (rc)
198 return rc;
199
200 return 0;
201 }
202
203 static int siena_probe_nic(struct efx_nic *efx)
204 {
205 struct siena_nic_data *nic_data;
206 bool already_attached = 0;
207 int rc;
208
209 /* Allocate storage for hardware specific data */
210 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
211 if (!nic_data)
212 return -ENOMEM;
213 efx->nic_data = nic_data;
214
215 if (efx_nic_fpga_ver(efx) != 0) {
216 EFX_ERR(efx, "Siena FPGA not supported\n");
217 rc = -ENODEV;
218 goto fail1;
219 }
220
221 efx_mcdi_init(efx);
222
223 /* Recover from a failed assertion before probing */
224 rc = efx_mcdi_handle_assertion(efx);
225 if (rc)
226 goto fail1;
227
228 rc = efx_mcdi_fwver(efx, &nic_data->fw_version, &nic_data->fw_build);
229 if (rc) {
230 EFX_ERR(efx, "Failed to read MCPU firmware version - "
231 "rc %d\n", rc);
232 goto fail1; /* MCPU absent? */
233 }
234
235 /* Let the BMC know that the driver is now in charge of link and
236 * filter settings. We must do this before we reset the NIC */
237 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
238 if (rc) {
239 EFX_ERR(efx, "Unable to register driver with MCPU\n");
240 goto fail2;
241 }
242 if (already_attached)
243 /* Not a fatal error */
244 EFX_ERR(efx, "Host already registered with MCPU\n");
245
246 /* Now we can reset the NIC */
247 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
248 if (rc) {
249 EFX_ERR(efx, "failed to reset NIC\n");
250 goto fail3;
251 }
252
253 siena_init_wol(efx);
254
255 /* Allocate memory for INT_KER */
256 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
257 if (rc)
258 goto fail4;
259 BUG_ON(efx->irq_status.dma_addr & 0x0f);
260
261 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
262 (unsigned long long)efx->irq_status.dma_addr,
263 efx->irq_status.addr,
264 (unsigned long long)virt_to_phys(efx->irq_status.addr));
265
266 /* Read in the non-volatile configuration */
267 rc = siena_probe_nvconfig(efx);
268 if (rc == -EINVAL) {
269 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
270 efx->phy_type = PHY_TYPE_NONE;
271 efx->mdio.prtad = MDIO_PRTAD_NONE;
272 } else if (rc) {
273 goto fail5;
274 }
275
276 return 0;
277
278 fail5:
279 efx_nic_free_buffer(efx, &efx->irq_status);
280 fail4:
281 fail3:
282 efx_mcdi_drv_attach(efx, false, NULL);
283 fail2:
284 fail1:
285 kfree(efx->nic_data);
286 return rc;
287 }
288
289 /* This call performs hardware-specific global initialisation, such as
290 * defining the descriptor cache sizes and number of RSS channels.
291 * It does not set up any buffers, descriptor rings or event queues.
292 */
293 static int siena_init_nic(struct efx_nic *efx)
294 {
295 efx_oword_t temp;
296 int rc;
297
298 /* Recover from a failed assertion post-reset */
299 rc = efx_mcdi_handle_assertion(efx);
300 if (rc)
301 return rc;
302
303 /* Squash TX of packets of 16 bytes or less */
304 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
305 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
306 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
307
308 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
309 * descriptors (which is bad).
310 */
311 efx_reado(efx, &temp, FR_AZ_TX_CFG);
312 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
313 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
314 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
315
316 efx_reado(efx, &temp, FR_AZ_RX_CFG);
317 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
318 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
319 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
320
321 if (efx_nic_rx_xoff_thresh >= 0 || efx_nic_rx_xon_thresh >= 0)
322 /* No MCDI operation has been defined to set thresholds */
323 EFX_ERR(efx, "ignoring RX flow control thresholds\n");
324
325 /* Enable event logging */
326 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
327 if (rc)
328 return rc;
329
330 /* Set destination of both TX and RX Flush events */
331 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
332 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
333
334 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
335 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
336
337 efx_nic_init_common(efx);
338 return 0;
339 }
340
341 static void siena_remove_nic(struct efx_nic *efx)
342 {
343 efx_nic_free_buffer(efx, &efx->irq_status);
344
345 siena_reset_hw(efx, RESET_TYPE_ALL);
346
347 /* Relinquish the device back to the BMC */
348 if (efx_nic_has_mc(efx))
349 efx_mcdi_drv_attach(efx, false, NULL);
350
351 /* Tear down the private nic state */
352 kfree(efx->nic_data);
353 efx->nic_data = NULL;
354 }
355
356 #define STATS_GENERATION_INVALID ((u64)(-1))
357
358 static int siena_try_update_nic_stats(struct efx_nic *efx)
359 {
360 u64 *dma_stats;
361 struct efx_mac_stats *mac_stats;
362 u64 generation_start;
363 u64 generation_end;
364
365 mac_stats = &efx->mac_stats;
366 dma_stats = (u64 *)efx->stats_buffer.addr;
367
368 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
369 if (generation_end == STATS_GENERATION_INVALID)
370 return 0;
371 rmb();
372
373 #define MAC_STAT(M, D) \
374 mac_stats->M = dma_stats[MC_CMD_MAC_ ## D]
375
376 MAC_STAT(tx_bytes, TX_BYTES);
377 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
378 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
379 mac_stats->tx_bad_bytes);
380 MAC_STAT(tx_packets, TX_PKTS);
381 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
382 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
383 MAC_STAT(tx_control, TX_CONTROL_PKTS);
384 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
385 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
386 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
387 MAC_STAT(tx_lt64, TX_LT64_PKTS);
388 MAC_STAT(tx_64, TX_64_PKTS);
389 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
390 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
391 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
392 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
393 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
394 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
395 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
396 mac_stats->tx_collision = 0;
397 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
398 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
399 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
400 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
401 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
402 mac_stats->tx_collision = (mac_stats->tx_single_collision +
403 mac_stats->tx_multiple_collision +
404 mac_stats->tx_excessive_collision +
405 mac_stats->tx_late_collision);
406 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
407 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
408 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
409 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
410 MAC_STAT(rx_bytes, RX_BYTES);
411 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
412 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
413 mac_stats->rx_bad_bytes);
414 MAC_STAT(rx_packets, RX_PKTS);
415 MAC_STAT(rx_good, RX_GOOD_PKTS);
416 mac_stats->rx_bad = mac_stats->rx_packets - mac_stats->rx_good;
417 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
418 MAC_STAT(rx_control, RX_CONTROL_PKTS);
419 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
420 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
421 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
422 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
423 MAC_STAT(rx_64, RX_64_PKTS);
424 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
425 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
426 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
427 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
428 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
429 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
430 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
431 mac_stats->rx_bad_lt64 = 0;
432 mac_stats->rx_bad_64_to_15xx = 0;
433 mac_stats->rx_bad_15xx_to_jumbo = 0;
434 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
435 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
436 mac_stats->rx_missed = 0;
437 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
438 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
439 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
440 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
441 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
442 mac_stats->rx_good_lt64 = 0;
443
444 efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS];
445
446 #undef MAC_STAT
447
448 rmb();
449 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
450 if (generation_end != generation_start)
451 return -EAGAIN;
452
453 return 0;
454 }
455
456 static void siena_update_nic_stats(struct efx_nic *efx)
457 {
458 while (siena_try_update_nic_stats(efx) == -EAGAIN)
459 cpu_relax();
460 }
461
462 static void siena_start_nic_stats(struct efx_nic *efx)
463 {
464 u64 *dma_stats = (u64 *)efx->stats_buffer.addr;
465
466 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
467
468 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
469 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
470 }
471
472 static void siena_stop_nic_stats(struct efx_nic *efx)
473 {
474 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
475 }
476
477 void siena_print_fwver(struct efx_nic *efx, char *buf, size_t len)
478 {
479 struct siena_nic_data *nic_data = efx->nic_data;
480 snprintf(buf, len, "%u.%u.%u.%u",
481 (unsigned int)(nic_data->fw_version >> 48),
482 (unsigned int)(nic_data->fw_version >> 32 & 0xffff),
483 (unsigned int)(nic_data->fw_version >> 16 & 0xffff),
484 (unsigned int)(nic_data->fw_version & 0xffff));
485 }
486
487 /**************************************************************************
488 *
489 * Wake on LAN
490 *
491 **************************************************************************
492 */
493
494 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
495 {
496 struct siena_nic_data *nic_data = efx->nic_data;
497
498 wol->supported = WAKE_MAGIC;
499 if (nic_data->wol_filter_id != -1)
500 wol->wolopts = WAKE_MAGIC;
501 else
502 wol->wolopts = 0;
503 memset(&wol->sopass, 0, sizeof(wol->sopass));
504 }
505
506
507 static int siena_set_wol(struct efx_nic *efx, u32 type)
508 {
509 struct siena_nic_data *nic_data = efx->nic_data;
510 int rc;
511
512 if (type & ~WAKE_MAGIC)
513 return -EINVAL;
514
515 if (type & WAKE_MAGIC) {
516 if (nic_data->wol_filter_id != -1)
517 efx_mcdi_wol_filter_remove(efx,
518 nic_data->wol_filter_id);
519 rc = efx_mcdi_wol_filter_set_magic(efx, efx->mac_address,
520 &nic_data->wol_filter_id);
521 if (rc)
522 goto fail;
523
524 pci_wake_from_d3(efx->pci_dev, true);
525 } else {
526 rc = efx_mcdi_wol_filter_reset(efx);
527 nic_data->wol_filter_id = -1;
528 pci_wake_from_d3(efx->pci_dev, false);
529 if (rc)
530 goto fail;
531 }
532
533 return 0;
534 fail:
535 EFX_ERR(efx, "%s failed: type=%d rc=%d\n", __func__, type, rc);
536 return rc;
537 }
538
539
540 static void siena_init_wol(struct efx_nic *efx)
541 {
542 struct siena_nic_data *nic_data = efx->nic_data;
543 int rc;
544
545 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
546
547 if (rc != 0) {
548 /* If it failed, attempt to get into a synchronised
549 * state with MC by resetting any set WoL filters */
550 efx_mcdi_wol_filter_reset(efx);
551 nic_data->wol_filter_id = -1;
552 } else if (nic_data->wol_filter_id != -1) {
553 pci_wake_from_d3(efx->pci_dev, true);
554 }
555 }
556
557
558 /**************************************************************************
559 *
560 * Revision-dependent attributes used by efx.c and nic.c
561 *
562 **************************************************************************
563 */
564
565 struct efx_nic_type siena_a0_nic_type = {
566 .probe = siena_probe_nic,
567 .remove = siena_remove_nic,
568 .init = siena_init_nic,
569 .fini = efx_port_dummy_op_void,
570 .monitor = NULL,
571 .reset = siena_reset_hw,
572 .probe_port = siena_probe_port,
573 .remove_port = siena_remove_port,
574 .prepare_flush = efx_port_dummy_op_void,
575 .update_stats = siena_update_nic_stats,
576 .start_stats = siena_start_nic_stats,
577 .stop_stats = siena_stop_nic_stats,
578 .set_id_led = efx_mcdi_set_id_led,
579 .push_irq_moderation = siena_push_irq_moderation,
580 .push_multicast_hash = siena_push_multicast_hash,
581 .reconfigure_port = efx_mcdi_phy_reconfigure,
582 .get_wol = siena_get_wol,
583 .set_wol = siena_set_wol,
584 .resume_wol = siena_init_wol,
585 .test_registers = siena_test_registers,
586 .test_nvram = efx_mcdi_nvram_test_all,
587 .default_mac_ops = &efx_mcdi_mac_operations,
588
589 .revision = EFX_REV_SIENA_A0,
590 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
591 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
592 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
593 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
594 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
595 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
596 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
597 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
598 .rx_buffer_padding = 0,
599 .max_interrupt_mode = EFX_INT_MODE_MSIX,
600 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
601 * interrupt handler only supports 32
602 * channels */
603 .tx_dc_base = 0x88000,
604 .rx_dc_base = 0x68000,
605 .offload_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM,
606 .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT,
607 };