drivers/scsi/hpsa_cmd.h

   1 /*
   2  *    Disk Array driver for HP Smart Array SAS controllers
   3  *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
   4  *
   5  *    This program is free software; you can redistribute it and/or modify
   6  *    it under the terms of the GNU General Public License as published by
   7  *    the Free Software Foundation; version 2 of the License.
   8  *
   9  *    This program is distributed in the hope that it will be useful,
  10  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
  13  *
  14  *    You should have received a copy of the GNU General Public License
  15  *    along with this program; if not, write to the Free Software
  16  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  *
  18  *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19  *
  20  */
  21 #ifndef HPSA_CMD_H
  22 #define HPSA_CMD_H
  23
  24 /* general boundary defintions */
  25 #define SENSEINFOBYTES          32 /* may vary between hbas */
  26 #define MAXSGENTRIES            32
  27 #define HPSA_SG_CHAIN           0x80000000
  28 #define MAXREPLYQS              256
  29
  30 /* Command Status value */
  31 #define CMD_SUCCESS             0x0000
  32 #define CMD_TARGET_STATUS       0x0001
  33 #define CMD_DATA_UNDERRUN       0x0002
  34 #define CMD_DATA_OVERRUN        0x0003
  35 #define CMD_INVALID             0x0004
  36 #define CMD_PROTOCOL_ERR        0x0005
  37 #define CMD_HARDWARE_ERR        0x0006
  38 #define CMD_CONNECTION_LOST     0x0007
  39 #define CMD_ABORTED             0x0008
  40 #define CMD_ABORT_FAILED        0x0009
  41 #define CMD_UNSOLICITED_ABORT   0x000A
  42 #define CMD_TIMEOUT             0x000B
  43 #define CMD_UNABORTABLE         0x000C
  44
  45 /* Unit Attentions ASC's as defined for the MSA2012sa */
  46 #define POWER_OR_RESET                  0x29
  47 #define STATE_CHANGED                   0x2a
  48 #define UNIT_ATTENTION_CLEARED          0x2f
  49 #define LUN_FAILED                      0x3e
  50 #define REPORT_LUNS_CHANGED             0x3f
  51
  52 /* Unit Attentions ASCQ's as defined for the MSA2012sa */
  53
  54         /* These ASCQ's defined for ASC = POWER_OR_RESET */
  55 #define POWER_ON_RESET                  0x00
  56 #define POWER_ON_REBOOT                 0x01
  57 #define SCSI_BUS_RESET                  0x02
  58 #define MSA_TARGET_RESET                0x03
  59 #define CONTROLLER_FAILOVER             0x04
  60 #define TRANSCEIVER_SE                  0x05
  61 #define TRANSCEIVER_LVD                 0x06
  62
  63         /* These ASCQ's defined for ASC = STATE_CHANGED */
  64 #define RESERVATION_PREEMPTED           0x03
  65 #define ASYM_ACCESS_CHANGED             0x06
  66 #define LUN_CAPACITY_CHANGED            0x09
  67
  68 /* transfer direction */
  69 #define XFER_NONE               0x00
  70 #define XFER_WRITE              0x01
  71 #define XFER_READ               0x02
  72 #define XFER_RSVD               0x03
  73
  74 /* task attribute */
  75 #define ATTR_UNTAGGED           0x00
  76 #define ATTR_SIMPLE             0x04
  77 #define ATTR_HEADOFQUEUE        0x05
  78 #define ATTR_ORDERED            0x06
  79 #define ATTR_ACA                0x07
  80
  81 /* cdb type */
  82 #define TYPE_CMD                                0x00
  83 #define TYPE_MSG                                0x01
  84
  85 /* config space register offsets */
  86 #define CFG_VENDORID            0x00
  87 #define CFG_DEVICEID            0x02
  88 #define CFG_I2OBAR              0x10
  89 #define CFG_MEM1BAR             0x14
  90
  91 /* i2o space register offsets */
  92 #define I2O_IBDB_SET            0x20
  93 #define I2O_IBDB_CLEAR          0x70
  94 #define I2O_INT_STATUS          0x30
  95 #define I2O_INT_MASK            0x34
  96 #define I2O_IBPOST_Q            0x40
  97 #define I2O_OBPOST_Q            0x44
  98 #define I2O_DMA1_CFG            0x214
  99
 100 /* Configuration Table */
 101 #define CFGTBL_ChangeReq        0x00000001l
 102 #define CFGTBL_AccCmds          0x00000001l
 103
 104 #define CFGTBL_Trans_Simple     0x00000002l
 105 #define CFGTBL_Trans_Performant 0x00000004l
 106
 107 #define CFGTBL_BusType_Ultra2   0x00000001l
 108 #define CFGTBL_BusType_Ultra3   0x00000002l
 109 #define CFGTBL_BusType_Fibre1G  0x00000100l
 110 #define CFGTBL_BusType_Fibre2G  0x00000200l
 111 struct vals32 {
 112         u32   lower;
 113         u32   upper;
 114 };
 115
 116 union u64bit {
 117         struct vals32 val32;
 118         u64 val;
 119 };
 120
 121 /* FIXME this is a per controller value (barf!) */
 122 #define HPSA_MAX_TARGETS_PER_CTLR 16
 123 #define HPSA_MAX_LUN 256
 124 #define HPSA_MAX_PHYS_LUN 1024
 125
 126 /* SCSI-3 Commands */
 127 #pragma pack(1)
 128
 129 #define HPSA_INQUIRY 0x12
 130 struct InquiryData {
 131         u8 data_byte[36];
 132 };
 133
 134 #define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
 135 #define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
 136 struct ReportLUNdata {
 137         u8 LUNListLength[4];
 138         u32 reserved;
 139         u8 LUN[HPSA_MAX_LUN][8];
 140 };
 141
 142 struct ReportExtendedLUNdata {
 143         u8 LUNListLength[4];
 144         u8 extended_response_flag;
 145         u8 reserved[3];
 146         u8 LUN[HPSA_MAX_LUN][24];
 147 };
 148
 149 struct SenseSubsystem_info {
 150         u8 reserved[36];
 151         u8 portname[8];
 152         u8 reserved1[1108];
 153 };
 154
 155 #define HPSA_READ_CAPACITY 0x25 /* Read Capacity */
 156 struct ReadCapdata {
 157         u8 total_size[4];       /* Total size in blocks */
 158         u8 block_size[4];       /* Size of blocks in bytes */
 159 };
 160
 161 #if 0
 162 /* 12 byte commands not implemented in firmware yet. */
 163 #define HPSA_READ       0xa8
 164 #define HPSA_WRITE      0xaa
 165 #endif
 166
 167 #define HPSA_READ   0x28    /* Read(10) */
 168 #define HPSA_WRITE  0x2a    /* Write(10) */
 169
 170 /* BMIC commands */
 171 #define BMIC_READ 0x26
 172 #define BMIC_WRITE 0x27
 173 #define BMIC_CACHE_FLUSH 0xc2
 174 #define HPSA_CACHE_FLUSH 0x01   /* C2 was already being used by HPSA */
 175
 176 /* Command List Structure */
 177 union SCSI3Addr {
 178         struct {
 179                 u8 Dev;
 180                 u8 Bus:6;
 181                 u8 Mode:2;        /* b00 */
 182         } PeripDev;
 183         struct {
 184                 u8 DevLSB;
 185                 u8 DevMSB:6;
 186                 u8 Mode:2;        /* b01 */
 187         } LogDev;
 188         struct {
 189                 u8 Dev:5;
 190                 u8 Bus:3;
 191                 u8 Targ:6;
 192                 u8 Mode:2;        /* b10 */
 193         } LogUnit;
 194 };
 195
 196 struct PhysDevAddr {
 197         u32             TargetId:24;
 198         u32             Bus:6;
 199         u32             Mode:2;
 200         /* 2 level target device addr */
 201         union SCSI3Addr  Target[2];
 202 };
 203
 204 struct LogDevAddr {
 205         u32            VolId:30;
 206         u32            Mode:2;
 207         u8             reserved[4];
 208 };
 209
 210 union LUNAddr {
 211         u8               LunAddrBytes[8];
 212         union SCSI3Addr    SCSI3Lun[4];
 213         struct PhysDevAddr PhysDev;
 214         struct LogDevAddr  LogDev;
 215 };
 216
 217 struct CommandListHeader {
 218         u8              ReplyQueue;
 219         u8              SGList;
 220         u16             SGTotal;
 221         struct vals32     Tag;
 222         union LUNAddr     LUN;
 223 };
 224
 225 struct RequestBlock {
 226         u8   CDBLen;
 227         struct {
 228                 u8 Type:3;
 229                 u8 Attribute:3;
 230                 u8 Direction:2;
 231         } Type;
 232         u16  Timeout;
 233         u8   CDB[16];
 234 };
 235
 236 struct ErrDescriptor {
 237         struct vals32 Addr;
 238         u32  Len;
 239 };
 240
 241 struct SGDescriptor {
 242         struct vals32 Addr;
 243         u32  Len;
 244         u32  Ext;
 245 };
 246
 247 union MoreErrInfo {
 248         struct {
 249                 u8  Reserved[3];
 250                 u8  Type;
 251                 u32 ErrorInfo;
 252         } Common_Info;
 253         struct {
 254                 u8  Reserved[2];
 255                 u8  offense_size; /* size of offending entry */
 256                 u8  offense_num;  /* byte # of offense 0-base */
 257                 u32 offense_value;
 258         } Invalid_Cmd;
 259 };
 260 struct ErrorInfo {
 261         u8               ScsiStatus;
 262         u8               SenseLen;
 263         u16              CommandStatus;
 264         u32              ResidualCnt;
 265         union MoreErrInfo  MoreErrInfo;
 266         u8               SenseInfo[SENSEINFOBYTES];
 267 };
 268 /* Command types */
 269 #define CMD_IOCTL_PEND  0x01
 270 #define CMD_SCSI        0x03
 271
 272 /* This structure needs to be divisible by 32 for new
 273  * indexing method and performant mode.
 274  */
 275 #define PAD32 32
 276 #define PAD64DIFF 0
 277 #define USEEXTRA ((sizeof(void *) - 4)/4)
 278 #define PADSIZE (PAD32 + PAD64DIFF * USEEXTRA)
 279
 280 #define DIRECT_LOOKUP_SHIFT 5
 281 #define DIRECT_LOOKUP_BIT 0x10
 282
 283 #define HPSA_ERROR_BIT          0x02
 284 struct ctlr_info; /* defined in hpsa.h */
 285 /* The size of this structure needs to be divisible by 32
 286  * on all architectures because low 5 bits of the addresses
 287  * are used as follows:
 288  *
 289  * bit 0: to device, used to indicate "performant mode" command
 290  *        from device, indidcates error status.
 291  * bit 1-3: to device, indicates block fetch table entry for
 292  *          reducing DMA in fetching commands from host memory.
 293  * bit 4: used to indicate whether tag is "direct lookup" (index),
 294  *        or a bus address.
 295  */
 296
 297 struct CommandList {
 298         struct CommandListHeader Header;
 299         struct RequestBlock      Request;
 300         struct ErrDescriptor     ErrDesc;
 301         struct SGDescriptor      SG[MAXSGENTRIES];
 302         /* information associated with the command */
 303         u32                        busaddr; /* physical addr of this record */
 304         struct ErrorInfo *err_info; /* pointer to the allocated mem */
 305         struct ctlr_info           *h;
 306         int                        cmd_type;
 307         long                       cmdindex;
 308         struct hlist_node list;
 309         struct request *rq;
 310         struct completion *waiting;
 311         void   *scsi_cmd;
 312
 313 /* on 64 bit architectures, to get this to be 32-byte-aligned
 314  * it so happens we need PAD_64 bytes of padding, on 32 bit systems,
 315  * we need PAD_32 bytes of padding (see below).   This does that.
 316  * If it happens that 64 bit and 32 bit systems need different
 317  * padding, PAD_32 and PAD_64 can be set independently, and.
 318  * the code below will do the right thing.
 319  */
 320 #define IS_32_BIT ((8 - sizeof(long))/4)
 321 #define IS_64_BIT (!IS_32_BIT)
 322 #define PAD_32 (4)
 323 #define PAD_64 (4)
 324 #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
 325         u8 pad[COMMANDLIST_PAD];
 326 };
 327
 328 /* Configuration Table Structure */
 329 struct HostWrite {
 330         u32 TransportRequest;
 331         u32 Reserved;
 332         u32 CoalIntDelay;
 333         u32 CoalIntCount;
 334 };
 335
 336 #define SIMPLE_MODE     0x02
 337 #define PERFORMANT_MODE 0x04
 338 #define MEMQ_MODE       0x08
 339
 340 struct CfgTable {
 341         u8            Signature[4];
 342         u32             SpecValence;
 343         u32           TransportSupport;
 344         u32           TransportActive;
 345         struct          HostWrite HostWrite;
 346         u32           CmdsOutMax;
 347         u32           BusTypes;
 348         u32           TransMethodOffset;
 349         u8            ServerName[16];
 350         u32           HeartBeat;
 351         u32           SCSI_Prefetch;
 352         u32             MaxScatterGatherElements;
 353         u32             MaxLogicalUnits;
 354         u32             MaxPhysicalDevices;
 355         u32             MaxPhysicalDrivesPerLogicalUnit;
 356         u32             MaxPerformantModeCommands;
 357 };
 358
 359 #define NUM_BLOCKFETCH_ENTRIES 8
 360 struct TransTable_struct {
 361         u32            BlockFetch[NUM_BLOCKFETCH_ENTRIES];
 362         u32            RepQSize;
 363         u32            RepQCount;
 364         u32            RepQCtrAddrLow32;
 365         u32            RepQCtrAddrHigh32;
 366         u32            RepQAddr0Low32;
 367         u32            RepQAddr0High32;
 368 };
 369
 370 struct hpsa_pci_info {
 371         unsigned char   bus;
 372         unsigned char   dev_fn;
 373         unsigned short  domain;
 374         u32             board_id;
 375 };
 376
 377 #pragma pack()
 378 #endif /* HPSA_CMD_H */