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Linux 2.6.34-rc3
[pohmelfs.git] / drivers / serial / sh-sci.c
blob309de6be8204bcc9fc880c6c9ae39884f460c8b3
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/list.h>
51 #include <linux/dmaengine.h>
52 #include <linux/scatterlist.h>
53
54 #ifdef CONFIG_SUPERH
55 #include <asm/sh_bios.h>
56 #endif
57
58 #ifdef CONFIG_H8300
59 #include <asm/gpio.h>
60 #endif
61
62 #include "sh-sci.h"
63
64 struct sci_port {
65 struct uart_port port;
66
67 /* Port type */
68 unsigned int type;
69
70 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
71 unsigned int irqs[SCIx_NR_IRQS];
72
73 /* Port enable callback */
74 void (*enable)(struct uart_port *port);
75
76 /* Port disable callback */
77 void (*disable)(struct uart_port *port);
78
79 /* Break timer */
80 struct timer_list break_timer;
81 int break_flag;
82
83 /* Interface clock */
84 struct clk *iclk;
85 /* Data clock */
86 struct clk *dclk;
87
88 struct list_head node;
89 struct dma_chan *chan_tx;
90 struct dma_chan *chan_rx;
91 #ifdef CONFIG_SERIAL_SH_SCI_DMA
92 struct device *dma_dev;
93 enum sh_dmae_slave_chan_id slave_tx;
94 enum sh_dmae_slave_chan_id slave_rx;
95 struct dma_async_tx_descriptor *desc_tx;
96 struct dma_async_tx_descriptor *desc_rx[2];
97 dma_cookie_t cookie_tx;
98 dma_cookie_t cookie_rx[2];
99 dma_cookie_t active_rx;
100 struct scatterlist sg_tx;
101 unsigned int sg_len_tx;
102 struct scatterlist sg_rx[2];
103 size_t buf_len_rx;
104 struct sh_dmae_slave param_tx;
105 struct sh_dmae_slave param_rx;
106 struct work_struct work_tx;
107 struct work_struct work_rx;
108 struct timer_list rx_timer;
109 #endif
110 };
111
112 struct sh_sci_priv {
113 spinlock_t lock;
114 struct list_head ports;
115 struct notifier_block clk_nb;
116 };
117
118 /* Function prototypes */
119 static void sci_stop_tx(struct uart_port *port);
120
121 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
122
123 static struct sci_port sci_ports[SCI_NPORTS];
124 static struct uart_driver sci_uart_driver;
125
126 static inline struct sci_port *
127 to_sci_port(struct uart_port *uart)
128 {
129 return container_of(uart, struct sci_port, port);
130 }
131
132 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
133
134 #ifdef CONFIG_CONSOLE_POLL
135 static inline void handle_error(struct uart_port *port)
136 {
137 /* Clear error flags */
138 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
139 }
140
141 static int sci_poll_get_char(struct uart_port *port)
142 {
143 unsigned short status;
144 int c;
145
146 do {
147 status = sci_in(port, SCxSR);
148 if (status & SCxSR_ERRORS(port)) {
149 handle_error(port);
150 continue;
151 }
152 } while (!(status & SCxSR_RDxF(port)));
153
154 c = sci_in(port, SCxRDR);
155
156 /* Dummy read */
157 sci_in(port, SCxSR);
158 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
159
160 return c;
161 }
162 #endif
163
164 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
165 {
166 unsigned short status;
167
168 do {
169 status = sci_in(port, SCxSR);
170 } while (!(status & SCxSR_TDxE(port)));
171
172 sci_out(port, SCxTDR, c);
173 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
174 }
175 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
176
177 #if defined(__H8300H__) || defined(__H8300S__)
178 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
179 {
180 int ch = (port->mapbase - SMR0) >> 3;
181
182 /* set DDR regs */
183 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
184 h8300_sci_pins[ch].rx,
185 H8300_GPIO_INPUT);
186 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
187 h8300_sci_pins[ch].tx,
188 H8300_GPIO_OUTPUT);
189
190 /* tx mark output*/
191 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
192 }
193 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
194 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
195 {
196 if (port->mapbase == 0xA4400000) {
197 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
198 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
199 } else if (port->mapbase == 0xA4410000)
200 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
201 }
202 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
203 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
204 {
205 unsigned short data;
206
207 if (cflag & CRTSCTS) {
208 /* enable RTS/CTS */
209 if (port->mapbase == 0xa4430000) { /* SCIF0 */
210 /* Clear PTCR bit 9-2; enable all scif pins but sck */
211 data = __raw_readw(PORT_PTCR);
212 __raw_writew((data & 0xfc03), PORT_PTCR);
213 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
214 /* Clear PVCR bit 9-2 */
215 data = __raw_readw(PORT_PVCR);
216 __raw_writew((data & 0xfc03), PORT_PVCR);
217 }
218 } else {
219 if (port->mapbase == 0xa4430000) { /* SCIF0 */
220 /* Clear PTCR bit 5-2; enable only tx and rx */
221 data = __raw_readw(PORT_PTCR);
222 __raw_writew((data & 0xffc3), PORT_PTCR);
223 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
224 /* Clear PVCR bit 5-2 */
225 data = __raw_readw(PORT_PVCR);
226 __raw_writew((data & 0xffc3), PORT_PVCR);
227 }
228 }
229 }
230 #elif defined(CONFIG_CPU_SH3)
231 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
232 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
233 {
234 unsigned short data;
235
236 /* We need to set SCPCR to enable RTS/CTS */
237 data = __raw_readw(SCPCR);
238 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
239 __raw_writew(data & 0x0fcf, SCPCR);
240
241 if (!(cflag & CRTSCTS)) {
242 /* We need to set SCPCR to enable RTS/CTS */
243 data = __raw_readw(SCPCR);
244 /* Clear out SCP7MD1,0, SCP4MD1,0,
245 Set SCP6MD1,0 = {01} (output) */
246 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
247
248 data = __raw_readb(SCPDR);
249 /* Set /RTS2 (bit6) = 0 */
250 __raw_writeb(data & 0xbf, SCPDR);
251 }
252 }
253 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
254 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
255 {
256 unsigned short data;
257
258 if (port->mapbase == 0xffe00000) {
259 data = __raw_readw(PSCR);
260 data &= ~0x03cf;
261 if (!(cflag & CRTSCTS))
262 data |= 0x0340;
263
264 __raw_writew(data, PSCR);
265 }
266 }
267 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
268 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
269 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
270 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
271 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
272 defined(CONFIG_CPU_SUBTYPE_SHX3)
273 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
274 {
275 if (!(cflag & CRTSCTS))
276 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
277 }
278 #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
279 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
280 {
281 if (!(cflag & CRTSCTS))
282 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
283 }
284 #else
285 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
286 {
287 /* Nothing to do */
288 }
289 #endif
290
291 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
292 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
293 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
294 defined(CONFIG_CPU_SUBTYPE_SH7786)
295 static int scif_txfill(struct uart_port *port)
296 {
297 return sci_in(port, SCTFDR) & 0xff;
298 }
299
300 static int scif_txroom(struct uart_port *port)
301 {
302 return SCIF_TXROOM_MAX - scif_txfill(port);
303 }
304
305 static int scif_rxfill(struct uart_port *port)
306 {
307 return sci_in(port, SCRFDR) & 0xff;
308 }
309 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
310 static int scif_txfill(struct uart_port *port)
311 {
312 if (port->mapbase == 0xffe00000 ||
313 port->mapbase == 0xffe08000)
314 /* SCIF0/1*/
315 return sci_in(port, SCTFDR) & 0xff;
316 else
317 /* SCIF2 */
318 return sci_in(port, SCFDR) >> 8;
319 }
320
321 static int scif_txroom(struct uart_port *port)
322 {
323 if (port->mapbase == 0xffe00000 ||
324 port->mapbase == 0xffe08000)
325 /* SCIF0/1*/
326 return SCIF_TXROOM_MAX - scif_txfill(port);
327 else
328 /* SCIF2 */
329 return SCIF2_TXROOM_MAX - scif_txfill(port);
330 }
331
332 static int scif_rxfill(struct uart_port *port)
333 {
334 if ((port->mapbase == 0xffe00000) ||
335 (port->mapbase == 0xffe08000)) {
336 /* SCIF0/1*/
337 return sci_in(port, SCRFDR) & 0xff;
338 } else {
339 /* SCIF2 */
340 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
341 }
342 }
343 #else
344 static int scif_txfill(struct uart_port *port)
345 {
346 return sci_in(port, SCFDR) >> 8;
347 }
348
349 static int scif_txroom(struct uart_port *port)
350 {
351 return SCIF_TXROOM_MAX - scif_txfill(port);
352 }
353
354 static int scif_rxfill(struct uart_port *port)
355 {
356 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
357 }
358 #endif
359
360 static int sci_txfill(struct uart_port *port)
361 {
362 return !(sci_in(port, SCxSR) & SCI_TDRE);
363 }
364
365 static int sci_txroom(struct uart_port *port)
366 {
367 return !sci_txfill(port);
368 }
369
370 static int sci_rxfill(struct uart_port *port)
371 {
372 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
373 }
374
375 /* ********************************************************************** *
376 * the interrupt related routines *
377 * ********************************************************************** */
378
379 static void sci_transmit_chars(struct uart_port *port)
380 {
381 struct circ_buf *xmit = &port->state->xmit;
382 unsigned int stopped = uart_tx_stopped(port);
383 unsigned short status;
384 unsigned short ctrl;
385 int count;
386
387 status = sci_in(port, SCxSR);
388 if (!(status & SCxSR_TDxE(port))) {
389 ctrl = sci_in(port, SCSCR);
390 if (uart_circ_empty(xmit))
391 ctrl &= ~SCI_CTRL_FLAGS_TIE;
392 else
393 ctrl |= SCI_CTRL_FLAGS_TIE;
394 sci_out(port, SCSCR, ctrl);
395 return;
396 }
397
398 if (port->type == PORT_SCI)
399 count = sci_txroom(port);
400 else
401 count = scif_txroom(port);
402
403 do {
404 unsigned char c;
405
406 if (port->x_char) {
407 c = port->x_char;
408 port->x_char = 0;
409 } else if (!uart_circ_empty(xmit) && !stopped) {
410 c = xmit->buf[xmit->tail];
411 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
412 } else {
413 break;
414 }
415
416 sci_out(port, SCxTDR, c);
417
418 port->icount.tx++;
419 } while (--count > 0);
420
421 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
422
423 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
424 uart_write_wakeup(port);
425 if (uart_circ_empty(xmit)) {
426 sci_stop_tx(port);
427 } else {
428 ctrl = sci_in(port, SCSCR);
429
430 if (port->type != PORT_SCI) {
431 sci_in(port, SCxSR); /* Dummy read */
432 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
433 }
434
435 ctrl |= SCI_CTRL_FLAGS_TIE;
436 sci_out(port, SCSCR, ctrl);
437 }
438 }
439
440 /* On SH3, SCIF may read end-of-break as a space->mark char */
441 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
442
443 static inline void sci_receive_chars(struct uart_port *port)
444 {
445 struct sci_port *sci_port = to_sci_port(port);
446 struct tty_struct *tty = port->state->port.tty;
447 int i, count, copied = 0;
448 unsigned short status;
449 unsigned char flag;
450
451 status = sci_in(port, SCxSR);
452 if (!(status & SCxSR_RDxF(port)))
453 return;
454
455 while (1) {
456 if (port->type == PORT_SCI)
457 count = sci_rxfill(port);
458 else
459 count = scif_rxfill(port);
460
461 /* Don't copy more bytes than there is room for in the buffer */
462 count = tty_buffer_request_room(tty, count);
463
464 /* If for any reason we can't copy more data, we're done! */
465 if (count == 0)
466 break;
467
468 if (port->type == PORT_SCI) {
469 char c = sci_in(port, SCxRDR);
470 if (uart_handle_sysrq_char(port, c) ||
471 sci_port->break_flag)
472 count = 0;
473 else
474 tty_insert_flip_char(tty, c, TTY_NORMAL);
475 } else {
476 for (i = 0; i < count; i++) {
477 char c = sci_in(port, SCxRDR);
478 status = sci_in(port, SCxSR);
479 #if defined(CONFIG_CPU_SH3)
480 /* Skip "chars" during break */
481 if (sci_port->break_flag) {
482 if ((c == 0) &&
483 (status & SCxSR_FER(port))) {
484 count--; i--;
485 continue;
486 }
487
488 /* Nonzero => end-of-break */
489 dev_dbg(port->dev, "debounce<%02x>\n", c);
490 sci_port->break_flag = 0;
491
492 if (STEPFN(c)) {
493 count--; i--;
494 continue;
495 }
496 }
497 #endif /* CONFIG_CPU_SH3 */
498 if (uart_handle_sysrq_char(port, c)) {
499 count--; i--;
500 continue;
501 }
502
503 /* Store data and status */
504 if (status & SCxSR_FER(port)) {
505 flag = TTY_FRAME;
506 dev_notice(port->dev, "frame error\n");
507 } else if (status & SCxSR_PER(port)) {
508 flag = TTY_PARITY;
509 dev_notice(port->dev, "parity error\n");
510 } else
511 flag = TTY_NORMAL;
512
513 tty_insert_flip_char(tty, c, flag);
514 }
515 }
516
517 sci_in(port, SCxSR); /* dummy read */
518 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
519
520 copied += count;
521 port->icount.rx += count;
522 }
523
524 if (copied) {
525 /* Tell the rest of the system the news. New characters! */
526 tty_flip_buffer_push(tty);
527 } else {
528 sci_in(port, SCxSR); /* dummy read */
529 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
530 }
531 }
532
533 #define SCI_BREAK_JIFFIES (HZ/20)
534 /* The sci generates interrupts during the break,
535 * 1 per millisecond or so during the break period, for 9600 baud.
536 * So dont bother disabling interrupts.
537 * But dont want more than 1 break event.
538 * Use a kernel timer to periodically poll the rx line until
539 * the break is finished.
540 */
541 static void sci_schedule_break_timer(struct sci_port *port)
542 {
543 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
544 add_timer(&port->break_timer);
545 }
546 /* Ensure that two consecutive samples find the break over. */
547 static void sci_break_timer(unsigned long data)
548 {
549 struct sci_port *port = (struct sci_port *)data;
550
551 if (sci_rxd_in(&port->port) == 0) {
552 port->break_flag = 1;
553 sci_schedule_break_timer(port);
554 } else if (port->break_flag == 1) {
555 /* break is over. */
556 port->break_flag = 2;
557 sci_schedule_break_timer(port);
558 } else
559 port->break_flag = 0;
560 }
561
562 static inline int sci_handle_errors(struct uart_port *port)
563 {
564 int copied = 0;
565 unsigned short status = sci_in(port, SCxSR);
566 struct tty_struct *tty = port->state->port.tty;
567
568 if (status & SCxSR_ORER(port)) {
569 /* overrun error */
570 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
571 copied++;
572
573 dev_notice(port->dev, "overrun error");
574 }
575
576 if (status & SCxSR_FER(port)) {
577 if (sci_rxd_in(port) == 0) {
578 /* Notify of BREAK */
579 struct sci_port *sci_port = to_sci_port(port);
580
581 if (!sci_port->break_flag) {
582 sci_port->break_flag = 1;
583 sci_schedule_break_timer(sci_port);
584
585 /* Do sysrq handling. */
586 if (uart_handle_break(port))
587 return 0;
588
589 dev_dbg(port->dev, "BREAK detected\n");
590
591 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
592 copied++;
593 }
594
595 } else {
596 /* frame error */
597 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
598 copied++;
599
600 dev_notice(port->dev, "frame error\n");
601 }
602 }
603
604 if (status & SCxSR_PER(port)) {
605 /* parity error */
606 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
607 copied++;
608
609 dev_notice(port->dev, "parity error");
610 }
611
612 if (copied)
613 tty_flip_buffer_push(tty);
614
615 return copied;
616 }
617
618 static inline int sci_handle_fifo_overrun(struct uart_port *port)
619 {
620 struct tty_struct *tty = port->state->port.tty;
621 int copied = 0;
622
623 if (port->type != PORT_SCIF)
624 return 0;
625
626 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
627 sci_out(port, SCLSR, 0);
628
629 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
630 tty_flip_buffer_push(tty);
631
632 dev_notice(port->dev, "overrun error\n");
633 copied++;
634 }
635
636 return copied;
637 }
638
639 static inline int sci_handle_breaks(struct uart_port *port)
640 {
641 int copied = 0;
642 unsigned short status = sci_in(port, SCxSR);
643 struct tty_struct *tty = port->state->port.tty;
644 struct sci_port *s = to_sci_port(port);
645
646 if (uart_handle_break(port))
647 return 0;
648
649 if (!s->break_flag && status & SCxSR_BRK(port)) {
650 #if defined(CONFIG_CPU_SH3)
651 /* Debounce break */
652 s->break_flag = 1;
653 #endif
654 /* Notify of BREAK */
655 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
656 copied++;
657
658 dev_dbg(port->dev, "BREAK detected\n");
659 }
660
661 if (copied)
662 tty_flip_buffer_push(tty);
663
664 copied += sci_handle_fifo_overrun(port);
665
666 return copied;
667 }
668
669 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
670 {
671 #ifdef CONFIG_SERIAL_SH_SCI_DMA
672 struct uart_port *port = ptr;
673 struct sci_port *s = to_sci_port(port);
674
675 if (s->chan_rx) {
676 unsigned long tout;
677 u16 scr = sci_in(port, SCSCR);
678 u16 ssr = sci_in(port, SCxSR);
679
680 /* Disable future Rx interrupts */
681 sci_out(port, SCSCR, scr & ~SCI_CTRL_FLAGS_RIE);
682 /* Clear current interrupt */
683 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
684 /* Calculate delay for 1.5 DMA buffers */
685 tout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
686 port->fifosize / 2;
687 dev_dbg(port->dev, "Rx IRQ: setup timeout in %lu ms\n",
688 tout * 1000 / HZ);
689 if (tout < 2)
690 tout = 2;
691 mod_timer(&s->rx_timer, jiffies + tout);
692
693 return IRQ_HANDLED;
694 }
695 #endif
696
697 /* I think sci_receive_chars has to be called irrespective
698 * of whether the I_IXOFF is set, otherwise, how is the interrupt
699 * to be disabled?
700 */
701 sci_receive_chars(ptr);
702
703 return IRQ_HANDLED;
704 }
705
706 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
707 {
708 struct uart_port *port = ptr;
709 unsigned long flags;
710
711 spin_lock_irqsave(&port->lock, flags);
712 sci_transmit_chars(port);
713 spin_unlock_irqrestore(&port->lock, flags);
714
715 return IRQ_HANDLED;
716 }
717
718 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
719 {
720 struct uart_port *port = ptr;
721
722 /* Handle errors */
723 if (port->type == PORT_SCI) {
724 if (sci_handle_errors(port)) {
725 /* discard character in rx buffer */
726 sci_in(port, SCxSR);
727 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
728 }
729 } else {
730 sci_handle_fifo_overrun(port);
731 sci_rx_interrupt(irq, ptr);
732 }
733
734 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
735
736 /* Kick the transmission */
737 sci_tx_interrupt(irq, ptr);
738
739 return IRQ_HANDLED;
740 }
741
742 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
743 {
744 struct uart_port *port = ptr;
745
746 /* Handle BREAKs */
747 sci_handle_breaks(port);
748 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
749
750 return IRQ_HANDLED;
751 }
752
753 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
754 {
755 unsigned short ssr_status, scr_status, err_enabled;
756 struct uart_port *port = ptr;
757 struct sci_port *s = to_sci_port(port);
758 irqreturn_t ret = IRQ_NONE;
759
760 ssr_status = sci_in(port, SCxSR);
761 scr_status = sci_in(port, SCSCR);
762 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
763
764 /* Tx Interrupt */
765 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) &&
766 !s->chan_tx)
767 ret = sci_tx_interrupt(irq, ptr);
768 /*
769 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
770 * DR flags
771 */
772 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
773 (scr_status & SCI_CTRL_FLAGS_RIE))
774 ret = sci_rx_interrupt(irq, ptr);
775 /* Error Interrupt */
776 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
777 ret = sci_er_interrupt(irq, ptr);
778 /* Break Interrupt */
779 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
780 ret = sci_br_interrupt(irq, ptr);
781
782 return ret;
783 }
784
785 /*
786 * Here we define a transistion notifier so that we can update all of our
787 * ports' baud rate when the peripheral clock changes.
788 */
789 static int sci_notifier(struct notifier_block *self,
790 unsigned long phase, void *p)
791 {
792 struct sh_sci_priv *priv = container_of(self,
793 struct sh_sci_priv, clk_nb);
794 struct sci_port *sci_port;
795 unsigned long flags;
796
797 if ((phase == CPUFREQ_POSTCHANGE) ||
798 (phase == CPUFREQ_RESUMECHANGE)) {
799 spin_lock_irqsave(&priv->lock, flags);
800 list_for_each_entry(sci_port, &priv->ports, node)
801 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
802 spin_unlock_irqrestore(&priv->lock, flags);
803 }
804
805 return NOTIFY_OK;
806 }
807
808 static void sci_clk_enable(struct uart_port *port)
809 {
810 struct sci_port *sci_port = to_sci_port(port);
811
812 clk_enable(sci_port->dclk);
813 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
814
815 if (sci_port->iclk)
816 clk_enable(sci_port->iclk);
817 }
818
819 static void sci_clk_disable(struct uart_port *port)
820 {
821 struct sci_port *sci_port = to_sci_port(port);
822
823 if (sci_port->iclk)
824 clk_disable(sci_port->iclk);
825
826 clk_disable(sci_port->dclk);
827 }
828
829 static int sci_request_irq(struct sci_port *port)
830 {
831 int i;
832 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
833 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
834 sci_br_interrupt,
835 };
836 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
837 "SCI Transmit Data Empty", "SCI Break" };
838
839 if (port->irqs[0] == port->irqs[1]) {
840 if (unlikely(!port->irqs[0]))
841 return -ENODEV;
842
843 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
844 IRQF_DISABLED, "sci", port)) {
845 dev_err(port->port.dev, "Can't allocate IRQ\n");
846 return -ENODEV;
847 }
848 } else {
849 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
850 if (unlikely(!port->irqs[i]))
851 continue;
852
853 if (request_irq(port->irqs[i], handlers[i],
854 IRQF_DISABLED, desc[i], port)) {
855 dev_err(port->port.dev, "Can't allocate IRQ\n");
856 return -ENODEV;
857 }
858 }
859 }
860
861 return 0;
862 }
863
864 static void sci_free_irq(struct sci_port *port)
865 {
866 int i;
867
868 if (port->irqs[0] == port->irqs[1])
869 free_irq(port->irqs[0], port);
870 else {
871 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
872 if (!port->irqs[i])
873 continue;
874
875 free_irq(port->irqs[i], port);
876 }
877 }
878 }
879
880 static unsigned int sci_tx_empty(struct uart_port *port)
881 {
882 unsigned short status = sci_in(port, SCxSR);
883 unsigned short in_tx_fifo = scif_txfill(port);
884
885 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
886 }
887
888 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
889 {
890 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
891 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
892 /* If you have signals for DTR and DCD, please implement here. */
893 }
894
895 static unsigned int sci_get_mctrl(struct uart_port *port)
896 {
897 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
898 and CTS/RTS */
899
900 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
901 }
902
903 #ifdef CONFIG_SERIAL_SH_SCI_DMA
904 static void sci_dma_tx_complete(void *arg)
905 {
906 struct sci_port *s = arg;
907 struct uart_port *port = &s->port;
908 struct circ_buf *xmit = &port->state->xmit;
909 unsigned long flags;
910
911 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
912
913 spin_lock_irqsave(&port->lock, flags);
914
915 xmit->tail += s->sg_tx.length;
916 xmit->tail &= UART_XMIT_SIZE - 1;
917
918 port->icount.tx += s->sg_tx.length;
919
920 async_tx_ack(s->desc_tx);
921 s->cookie_tx = -EINVAL;
922 s->desc_tx = NULL;
923
924 spin_unlock_irqrestore(&port->lock, flags);
925
926 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
927 uart_write_wakeup(port);
928
929 if (uart_circ_chars_pending(xmit))
930 schedule_work(&s->work_tx);
931 }
932
933 /* Locking: called with port lock held */
934 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
935 size_t count)
936 {
937 struct uart_port *port = &s->port;
938 int i, active, room;
939
940 room = tty_buffer_request_room(tty, count);
941
942 if (s->active_rx == s->cookie_rx[0]) {
943 active = 0;
944 } else if (s->active_rx == s->cookie_rx[1]) {
945 active = 1;
946 } else {
947 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
948 return 0;
949 }
950
951 if (room < count)
952 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
953 count - room);
954 if (!room)
955 return room;
956
957 for (i = 0; i < room; i++)
958 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
959 TTY_NORMAL);
960
961 port->icount.rx += room;
962
963 return room;
964 }
965
966 static void sci_dma_rx_complete(void *arg)
967 {
968 struct sci_port *s = arg;
969 struct uart_port *port = &s->port;
970 struct tty_struct *tty = port->state->port.tty;
971 unsigned long flags;
972 int count;
973
974 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
975
976 spin_lock_irqsave(&port->lock, flags);
977
978 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
979
980 mod_timer(&s->rx_timer, jiffies + msecs_to_jiffies(5));
981
982 spin_unlock_irqrestore(&port->lock, flags);
983
984 if (count)
985 tty_flip_buffer_push(tty);
986
987 schedule_work(&s->work_rx);
988 }
989
990 static void sci_start_rx(struct uart_port *port);
991 static void sci_start_tx(struct uart_port *port);
992
993 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
994 {
995 struct dma_chan *chan = s->chan_rx;
996 struct uart_port *port = &s->port;
997
998 s->chan_rx = NULL;
999 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1000 dma_release_channel(chan);
1001 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1002 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1003 if (enable_pio)
1004 sci_start_rx(port);
1005 }
1006
1007 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1008 {
1009 struct dma_chan *chan = s->chan_tx;
1010 struct uart_port *port = &s->port;
1011
1012 s->chan_tx = NULL;
1013 s->cookie_tx = -EINVAL;
1014 dma_release_channel(chan);
1015 if (enable_pio)
1016 sci_start_tx(port);
1017 }
1018
1019 static void sci_submit_rx(struct sci_port *s)
1020 {
1021 struct dma_chan *chan = s->chan_rx;
1022 int i;
1023
1024 for (i = 0; i < 2; i++) {
1025 struct scatterlist *sg = &s->sg_rx[i];
1026 struct dma_async_tx_descriptor *desc;
1027
1028 desc = chan->device->device_prep_slave_sg(chan,
1029 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1030
1031 if (desc) {
1032 s->desc_rx[i] = desc;
1033 desc->callback = sci_dma_rx_complete;
1034 desc->callback_param = s;
1035 s->cookie_rx[i] = desc->tx_submit(desc);
1036 }
1037
1038 if (!desc || s->cookie_rx[i] < 0) {
1039 if (i) {
1040 async_tx_ack(s->desc_rx[0]);
1041 s->cookie_rx[0] = -EINVAL;
1042 }
1043 if (desc) {
1044 async_tx_ack(desc);
1045 s->cookie_rx[i] = -EINVAL;
1046 }
1047 dev_warn(s->port.dev,
1048 "failed to re-start DMA, using PIO\n");
1049 sci_rx_dma_release(s, true);
1050 return;
1051 }
1052 }
1053
1054 s->active_rx = s->cookie_rx[0];
1055
1056 dma_async_issue_pending(chan);
1057 }
1058
1059 static void work_fn_rx(struct work_struct *work)
1060 {
1061 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1062 struct uart_port *port = &s->port;
1063 struct dma_async_tx_descriptor *desc;
1064 int new;
1065
1066 if (s->active_rx == s->cookie_rx[0]) {
1067 new = 0;
1068 } else if (s->active_rx == s->cookie_rx[1]) {
1069 new = 1;
1070 } else {
1071 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1072 return;
1073 }
1074 desc = s->desc_rx[new];
1075
1076 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1077 DMA_SUCCESS) {
1078 /* Handle incomplete DMA receive */
1079 struct tty_struct *tty = port->state->port.tty;
1080 struct dma_chan *chan = s->chan_rx;
1081 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1082 async_tx);
1083 unsigned long flags;
1084 int count;
1085
1086 chan->device->device_terminate_all(chan);
1087 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1088 sh_desc->partial, sh_desc->cookie);
1089
1090 spin_lock_irqsave(&port->lock, flags);
1091 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1092 spin_unlock_irqrestore(&port->lock, flags);
1093
1094 if (count)
1095 tty_flip_buffer_push(tty);
1096
1097 sci_submit_rx(s);
1098
1099 return;
1100 }
1101
1102 s->cookie_rx[new] = desc->tx_submit(desc);
1103 if (s->cookie_rx[new] < 0) {
1104 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1105 sci_rx_dma_release(s, true);
1106 return;
1107 }
1108
1109 dev_dbg(port->dev, "%s: cookie %d #%d\n", __func__,
1110 s->cookie_rx[new], new);
1111
1112 s->active_rx = s->cookie_rx[!new];
1113 }
1114
1115 static void work_fn_tx(struct work_struct *work)
1116 {
1117 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1118 struct dma_async_tx_descriptor *desc;
1119 struct dma_chan *chan = s->chan_tx;
1120 struct uart_port *port = &s->port;
1121 struct circ_buf *xmit = &port->state->xmit;
1122 struct scatterlist *sg = &s->sg_tx;
1123
1124 /*
1125 * DMA is idle now.
1126 * Port xmit buffer is already mapped, and it is one page... Just adjust
1127 * offsets and lengths. Since it is a circular buffer, we have to
1128 * transmit till the end, and then the rest. Take the port lock to get a
1129 * consistent xmit buffer state.
1130 */
1131 spin_lock_irq(&port->lock);
1132 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1133 sg->dma_address = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1134 sg->offset;
1135 sg->length = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1136 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1137 sg->dma_length = sg->length;
1138 spin_unlock_irq(&port->lock);
1139
1140 BUG_ON(!sg->length);
1141
1142 desc = chan->device->device_prep_slave_sg(chan,
1143 sg, s->sg_len_tx, DMA_TO_DEVICE,
1144 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1145 if (!desc) {
1146 /* switch to PIO */
1147 sci_tx_dma_release(s, true);
1148 return;
1149 }
1150
1151 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1152
1153 spin_lock_irq(&port->lock);
1154 s->desc_tx = desc;
1155 desc->callback = sci_dma_tx_complete;
1156 desc->callback_param = s;
1157 spin_unlock_irq(&port->lock);
1158 s->cookie_tx = desc->tx_submit(desc);
1159 if (s->cookie_tx < 0) {
1160 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1161 /* switch to PIO */
1162 sci_tx_dma_release(s, true);
1163 return;
1164 }
1165
1166 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1167 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1168
1169 dma_async_issue_pending(chan);
1170 }
1171 #endif
1172
1173 static void sci_start_tx(struct uart_port *port)
1174 {
1175 unsigned short ctrl;
1176
1177 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1178 struct sci_port *s = to_sci_port(port);
1179
1180 if (s->chan_tx) {
1181 if (!uart_circ_empty(&s->port.state->xmit) && s->cookie_tx < 0)
1182 schedule_work(&s->work_tx);
1183
1184 return;
1185 }
1186 #endif
1187
1188 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1189 ctrl = sci_in(port, SCSCR);
1190 ctrl |= SCI_CTRL_FLAGS_TIE;
1191 sci_out(port, SCSCR, ctrl);
1192 }
1193
1194 static void sci_stop_tx(struct uart_port *port)
1195 {
1196 unsigned short ctrl;
1197
1198 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1199 ctrl = sci_in(port, SCSCR);
1200 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1201 sci_out(port, SCSCR, ctrl);
1202 }
1203
1204 static void sci_start_rx(struct uart_port *port)
1205 {
1206 unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
1207
1208 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1209 ctrl |= sci_in(port, SCSCR);
1210 sci_out(port, SCSCR, ctrl);
1211 }
1212
1213 static void sci_stop_rx(struct uart_port *port)
1214 {
1215 unsigned short ctrl;
1216
1217 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1218 ctrl = sci_in(port, SCSCR);
1219 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1220 sci_out(port, SCSCR, ctrl);
1221 }
1222
1223 static void sci_enable_ms(struct uart_port *port)
1224 {
1225 /* Nothing here yet .. */
1226 }
1227
1228 static void sci_break_ctl(struct uart_port *port, int break_state)
1229 {
1230 /* Nothing here yet .. */
1231 }
1232
1233 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1234 static bool filter(struct dma_chan *chan, void *slave)
1235 {
1236 struct sh_dmae_slave *param = slave;
1237
1238 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1239 param->slave_id);
1240
1241 if (param->dma_dev == chan->device->dev) {
1242 chan->private = param;
1243 return true;
1244 } else {
1245 return false;
1246 }
1247 }
1248
1249 static void rx_timer_fn(unsigned long arg)
1250 {
1251 struct sci_port *s = (struct sci_port *)arg;
1252 struct uart_port *port = &s->port;
1253
1254 u16 scr = sci_in(port, SCSCR);
1255 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
1256 dev_dbg(port->dev, "DMA Rx timed out\n");
1257 schedule_work(&s->work_rx);
1258 }
1259
1260 static void sci_request_dma(struct uart_port *port)
1261 {
1262 struct sci_port *s = to_sci_port(port);
1263 struct sh_dmae_slave *param;
1264 struct dma_chan *chan;
1265 dma_cap_mask_t mask;
1266 int nent;
1267
1268 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1269 port->line, s->dma_dev);
1270
1271 if (!s->dma_dev)
1272 return;
1273
1274 dma_cap_zero(mask);
1275 dma_cap_set(DMA_SLAVE, mask);
1276
1277 param = &s->param_tx;
1278
1279 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1280 param->slave_id = s->slave_tx;
1281 param->dma_dev = s->dma_dev;
1282
1283 s->cookie_tx = -EINVAL;
1284 chan = dma_request_channel(mask, filter, param);
1285 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1286 if (chan) {
1287 s->chan_tx = chan;
1288 sg_init_table(&s->sg_tx, 1);
1289 /* UART circular tx buffer is an aligned page. */
1290 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1291 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1292 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1293 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1294 if (!nent)
1295 sci_tx_dma_release(s, false);
1296 else
1297 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1298 sg_dma_len(&s->sg_tx),
1299 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1300
1301 s->sg_len_tx = nent;
1302
1303 INIT_WORK(&s->work_tx, work_fn_tx);
1304 }
1305
1306 param = &s->param_rx;
1307
1308 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1309 param->slave_id = s->slave_rx;
1310 param->dma_dev = s->dma_dev;
1311
1312 chan = dma_request_channel(mask, filter, param);
1313 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1314 if (chan) {
1315 dma_addr_t dma[2];
1316 void *buf[2];
1317 int i;
1318
1319 s->chan_rx = chan;
1320
1321 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1322 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1323 &dma[0], GFP_KERNEL);
1324
1325 if (!buf[0]) {
1326 dev_warn(port->dev,
1327 "failed to allocate dma buffer, using PIO\n");
1328 sci_rx_dma_release(s, true);
1329 return;
1330 }
1331
1332 buf[1] = buf[0] + s->buf_len_rx;
1333 dma[1] = dma[0] + s->buf_len_rx;
1334
1335 for (i = 0; i < 2; i++) {
1336 struct scatterlist *sg = &s->sg_rx[i];
1337
1338 sg_init_table(sg, 1);
1339 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1340 (int)buf[i] & ~PAGE_MASK);
1341 sg->dma_address = dma[i];
1342 sg->dma_length = sg->length;
1343 }
1344
1345 INIT_WORK(&s->work_rx, work_fn_rx);
1346 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1347
1348 sci_submit_rx(s);
1349 }
1350 }
1351
1352 static void sci_free_dma(struct uart_port *port)
1353 {
1354 struct sci_port *s = to_sci_port(port);
1355
1356 if (!s->dma_dev)
1357 return;
1358
1359 if (s->chan_tx)
1360 sci_tx_dma_release(s, false);
1361 if (s->chan_rx)
1362 sci_rx_dma_release(s, false);
1363 }
1364 #endif
1365
1366 static int sci_startup(struct uart_port *port)
1367 {
1368 struct sci_port *s = to_sci_port(port);
1369
1370 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1371
1372 if (s->enable)
1373 s->enable(port);
1374
1375 sci_request_irq(s);
1376 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1377 sci_request_dma(port);
1378 #endif
1379 sci_start_tx(port);
1380 sci_start_rx(port);
1381
1382 return 0;
1383 }
1384
1385 static void sci_shutdown(struct uart_port *port)
1386 {
1387 struct sci_port *s = to_sci_port(port);
1388
1389 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1390
1391 sci_stop_rx(port);
1392 sci_stop_tx(port);
1393 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1394 sci_free_dma(port);
1395 #endif
1396 sci_free_irq(s);
1397
1398 if (s->disable)
1399 s->disable(port);
1400 }
1401
1402 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1403 struct ktermios *old)
1404 {
1405 unsigned int status, baud, smr_val, max_baud;
1406 int t = -1;
1407
1408 /*
1409 * earlyprintk comes here early on with port->uartclk set to zero.
1410 * the clock framework is not up and running at this point so here
1411 * we assume that 115200 is the maximum baud rate. please note that
1412 * the baud rate is not programmed during earlyprintk - it is assumed
1413 * that the previous boot loader has enabled required clocks and
1414 * setup the baud rate generator hardware for us already.
1415 */
1416 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1417
1418 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1419 if (likely(baud && port->uartclk))
1420 t = SCBRR_VALUE(baud, port->uartclk);
1421
1422 do {
1423 status = sci_in(port, SCxSR);
1424 } while (!(status & SCxSR_TEND(port)));
1425
1426 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1427
1428 if (port->type != PORT_SCI)
1429 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1430
1431 smr_val = sci_in(port, SCSMR) & 3;
1432 if ((termios->c_cflag & CSIZE) == CS7)
1433 smr_val |= 0x40;
1434 if (termios->c_cflag & PARENB)
1435 smr_val |= 0x20;
1436 if (termios->c_cflag & PARODD)
1437 smr_val |= 0x30;
1438 if (termios->c_cflag & CSTOPB)
1439 smr_val |= 0x08;
1440
1441 uart_update_timeout(port, termios->c_cflag, baud);
1442
1443 sci_out(port, SCSMR, smr_val);
1444
1445 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1446 SCSCR_INIT(port));
1447
1448 if (t > 0) {
1449 if (t >= 256) {
1450 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1451 t >>= 2;
1452 } else
1453 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1454
1455 sci_out(port, SCBRR, t);
1456 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1457 }
1458
1459 sci_init_pins(port, termios->c_cflag);
1460 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
1461
1462 sci_out(port, SCSCR, SCSCR_INIT(port));
1463
1464 if ((termios->c_cflag & CREAD) != 0)
1465 sci_start_rx(port);
1466 }
1467
1468 static const char *sci_type(struct uart_port *port)
1469 {
1470 switch (port->type) {
1471 case PORT_IRDA:
1472 return "irda";
1473 case PORT_SCI:
1474 return "sci";
1475 case PORT_SCIF:
1476 return "scif";
1477 case PORT_SCIFA:
1478 return "scifa";
1479 }
1480
1481 return NULL;
1482 }
1483
1484 static void sci_release_port(struct uart_port *port)
1485 {
1486 /* Nothing here yet .. */
1487 }
1488
1489 static int sci_request_port(struct uart_port *port)
1490 {
1491 /* Nothing here yet .. */
1492 return 0;
1493 }
1494
1495 static void sci_config_port(struct uart_port *port, int flags)
1496 {
1497 struct sci_port *s = to_sci_port(port);
1498
1499 port->type = s->type;
1500
1501 if (port->membase)
1502 return;
1503
1504 if (port->flags & UPF_IOREMAP) {
1505 port->membase = ioremap_nocache(port->mapbase, 0x40);
1506
1507 if (IS_ERR(port->membase))
1508 dev_err(port->dev, "can't remap port#%d\n", port->line);
1509 } else {
1510 /*
1511 * For the simple (and majority of) cases where we don't
1512 * need to do any remapping, just cast the cookie
1513 * directly.
1514 */
1515 port->membase = (void __iomem *)port->mapbase;
1516 }
1517 }
1518
1519 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1520 {
1521 struct sci_port *s = to_sci_port(port);
1522
1523 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1524 return -EINVAL;
1525 if (ser->baud_base < 2400)
1526 /* No paper tape reader for Mitch.. */
1527 return -EINVAL;
1528
1529 return 0;
1530 }
1531
1532 static struct uart_ops sci_uart_ops = {
1533 .tx_empty = sci_tx_empty,
1534 .set_mctrl = sci_set_mctrl,
1535 .get_mctrl = sci_get_mctrl,
1536 .start_tx = sci_start_tx,
1537 .stop_tx = sci_stop_tx,
1538 .stop_rx = sci_stop_rx,
1539 .enable_ms = sci_enable_ms,
1540 .break_ctl = sci_break_ctl,
1541 .startup = sci_startup,
1542 .shutdown = sci_shutdown,
1543 .set_termios = sci_set_termios,
1544 .type = sci_type,
1545 .release_port = sci_release_port,
1546 .request_port = sci_request_port,
1547 .config_port = sci_config_port,
1548 .verify_port = sci_verify_port,
1549 #ifdef CONFIG_CONSOLE_POLL
1550 .poll_get_char = sci_poll_get_char,
1551 .poll_put_char = sci_poll_put_char,
1552 #endif
1553 };
1554
1555 static void __devinit sci_init_single(struct platform_device *dev,
1556 struct sci_port *sci_port,
1557 unsigned int index,
1558 struct plat_sci_port *p)
1559 {
1560 struct uart_port *port = &sci_port->port;
1561
1562 port->ops = &sci_uart_ops;
1563 port->iotype = UPIO_MEM;
1564 port->line = index;
1565
1566 switch (p->type) {
1567 case PORT_SCIFA:
1568 port->fifosize = 64;
1569 break;
1570 case PORT_SCIF:
1571 port->fifosize = 16;
1572 break;
1573 default:
1574 port->fifosize = 1;
1575 break;
1576 }
1577
1578 if (dev) {
1579 sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
1580 sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
1581 sci_port->enable = sci_clk_enable;
1582 sci_port->disable = sci_clk_disable;
1583 port->dev = &dev->dev;
1584 }
1585
1586 sci_port->break_timer.data = (unsigned long)sci_port;
1587 sci_port->break_timer.function = sci_break_timer;
1588 init_timer(&sci_port->break_timer);
1589
1590 port->mapbase = p->mapbase;
1591 port->membase = p->membase;
1592
1593 port->irq = p->irqs[SCIx_TXI_IRQ];
1594 port->flags = p->flags;
1595 sci_port->type = port->type = p->type;
1596
1597 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1598 sci_port->dma_dev = p->dma_dev;
1599 sci_port->slave_tx = p->dma_slave_tx;
1600 sci_port->slave_rx = p->dma_slave_rx;
1601
1602 dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__,
1603 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1604 #endif
1605
1606 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
1607 }
1608
1609 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1610 static struct tty_driver *serial_console_device(struct console *co, int *index)
1611 {
1612 struct uart_driver *p = &sci_uart_driver;
1613 *index = co->index;
1614 return p->tty_driver;
1615 }
1616
1617 static void serial_console_putchar(struct uart_port *port, int ch)
1618 {
1619 sci_poll_put_char(port, ch);
1620 }
1621
1622 /*
1623 * Print a string to the serial port trying not to disturb
1624 * any possible real use of the port...
1625 */
1626 static void serial_console_write(struct console *co, const char *s,
1627 unsigned count)
1628 {
1629 struct uart_port *port = co->data;
1630 struct sci_port *sci_port = to_sci_port(port);
1631 unsigned short bits;
1632
1633 if (sci_port->enable)
1634 sci_port->enable(port);
1635
1636 uart_console_write(port, s, count, serial_console_putchar);
1637
1638 /* wait until fifo is empty and last bit has been transmitted */
1639 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1640 while ((sci_in(port, SCxSR) & bits) != bits)
1641 cpu_relax();
1642
1643 if (sci_port->disable)
1644 sci_port->disable(port);
1645 }
1646
1647 static int __devinit serial_console_setup(struct console *co, char *options)
1648 {
1649 struct sci_port *sci_port;
1650 struct uart_port *port;
1651 int baud = 115200;
1652 int bits = 8;
1653 int parity = 'n';
1654 int flow = 'n';
1655 int ret;
1656
1657 /*
1658 * Check whether an invalid uart number has been specified, and
1659 * if so, search for the first available port that does have
1660 * console support.
1661 */
1662 if (co->index >= SCI_NPORTS)
1663 co->index = 0;
1664
1665 if (co->data) {
1666 port = co->data;
1667 sci_port = to_sci_port(port);
1668 } else {
1669 sci_port = &sci_ports[co->index];
1670 port = &sci_port->port;
1671 co->data = port;
1672 }
1673
1674 /*
1675 * Also need to check port->type, we don't actually have any
1676 * UPIO_PORT ports, but uart_report_port() handily misreports
1677 * it anyways if we don't have a port available by the time this is
1678 * called.
1679 */
1680 if (!port->type)
1681 return -ENODEV;
1682
1683 sci_config_port(port, 0);
1684
1685 if (sci_port->enable)
1686 sci_port->enable(port);
1687
1688 if (options)
1689 uart_parse_options(options, &baud, &parity, &bits, &flow);
1690
1691 ret = uart_set_options(port, co, baud, parity, bits, flow);
1692 #if defined(__H8300H__) || defined(__H8300S__)
1693 /* disable rx interrupt */
1694 if (ret == 0)
1695 sci_stop_rx(port);
1696 #endif
1697 /* TODO: disable clock */
1698 return ret;
1699 }
1700
1701 static struct console serial_console = {
1702 .name = "ttySC",
1703 .device = serial_console_device,
1704 .write = serial_console_write,
1705 .setup = serial_console_setup,
1706 .flags = CON_PRINTBUFFER,
1707 .index = -1,
1708 };
1709
1710 static int __init sci_console_init(void)
1711 {
1712 register_console(&serial_console);
1713 return 0;
1714 }
1715 console_initcall(sci_console_init);
1716
1717 static struct sci_port early_serial_port;
1718 static struct console early_serial_console = {
1719 .name = "early_ttySC",
1720 .write = serial_console_write,
1721 .flags = CON_PRINTBUFFER,
1722 };
1723 static char early_serial_buf[32];
1724
1725 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1726
1727 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1728 #define SCI_CONSOLE (&serial_console)
1729 #else
1730 #define SCI_CONSOLE 0
1731 #endif
1732
1733 static char banner[] __initdata =
1734 KERN_INFO "SuperH SCI(F) driver initialized\n";
1735
1736 static struct uart_driver sci_uart_driver = {
1737 .owner = THIS_MODULE,
1738 .driver_name = "sci",
1739 .dev_name = "ttySC",
1740 .major = SCI_MAJOR,
1741 .minor = SCI_MINOR_START,
1742 .nr = SCI_NPORTS,
1743 .cons = SCI_CONSOLE,
1744 };
1745
1746
1747 static int sci_remove(struct platform_device *dev)
1748 {
1749 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1750 struct sci_port *p;
1751 unsigned long flags;
1752
1753 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1754
1755 spin_lock_irqsave(&priv->lock, flags);
1756 list_for_each_entry(p, &priv->ports, node)
1757 uart_remove_one_port(&sci_uart_driver, &p->port);
1758 spin_unlock_irqrestore(&priv->lock, flags);
1759
1760 kfree(priv);
1761 return 0;
1762 }
1763
1764 static int __devinit sci_probe_single(struct platform_device *dev,
1765 unsigned int index,
1766 struct plat_sci_port *p,
1767 struct sci_port *sciport)
1768 {
1769 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1770 unsigned long flags;
1771 int ret;
1772
1773 /* Sanity check */
1774 if (unlikely(index >= SCI_NPORTS)) {
1775 dev_notice(&dev->dev, "Attempting to register port "
1776 "%d when only %d are available.\n",
1777 index+1, SCI_NPORTS);
1778 dev_notice(&dev->dev, "Consider bumping "
1779 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1780 return 0;
1781 }
1782
1783 sci_init_single(dev, sciport, index, p);
1784
1785 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
1786 if (ret)
1787 return ret;
1788
1789 INIT_LIST_HEAD(&sciport->node);
1790
1791 spin_lock_irqsave(&priv->lock, flags);
1792 list_add(&sciport->node, &priv->ports);
1793 spin_unlock_irqrestore(&priv->lock, flags);
1794
1795 return 0;
1796 }
1797
1798 /*
1799 * Register a set of serial devices attached to a platform device. The
1800 * list is terminated with a zero flags entry, which means we expect
1801 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1802 * remapping (such as sh64) should also set UPF_IOREMAP.
1803 */
1804 static int __devinit sci_probe(struct platform_device *dev)
1805 {
1806 struct plat_sci_port *p = dev->dev.platform_data;
1807 struct sh_sci_priv *priv;
1808 int i, ret = -EINVAL;
1809
1810 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1811 if (is_early_platform_device(dev)) {
1812 if (dev->id == -1)
1813 return -ENOTSUPP;
1814 early_serial_console.index = dev->id;
1815 early_serial_console.data = &early_serial_port.port;
1816 sci_init_single(NULL, &early_serial_port, dev->id, p);
1817 serial_console_setup(&early_serial_console, early_serial_buf);
1818 if (!strstr(early_serial_buf, "keep"))
1819 early_serial_console.flags |= CON_BOOT;
1820 register_console(&early_serial_console);
1821 return 0;
1822 }
1823 #endif
1824
1825 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1826 if (!priv)
1827 return -ENOMEM;
1828
1829 INIT_LIST_HEAD(&priv->ports);
1830 spin_lock_init(&priv->lock);
1831 platform_set_drvdata(dev, priv);
1832
1833 priv->clk_nb.notifier_call = sci_notifier;
1834 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1835
1836 if (dev->id != -1) {
1837 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1838 if (ret)
1839 goto err_unreg;
1840 } else {
1841 for (i = 0; p && p->flags != 0; p++, i++) {
1842 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1843 if (ret)
1844 goto err_unreg;
1845 }
1846 }
1847
1848 #ifdef CONFIG_SH_STANDARD_BIOS
1849 sh_bios_gdb_detach();
1850 #endif
1851
1852 return 0;
1853
1854 err_unreg:
1855 sci_remove(dev);
1856 return ret;
1857 }
1858
1859 static int sci_suspend(struct device *dev)
1860 {
1861 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1862 struct sci_port *p;
1863 unsigned long flags;
1864
1865 spin_lock_irqsave(&priv->lock, flags);
1866 list_for_each_entry(p, &priv->ports, node)
1867 uart_suspend_port(&sci_uart_driver, &p->port);
1868 spin_unlock_irqrestore(&priv->lock, flags);
1869
1870 return 0;
1871 }
1872
1873 static int sci_resume(struct device *dev)
1874 {
1875 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1876 struct sci_port *p;
1877 unsigned long flags;
1878
1879 spin_lock_irqsave(&priv->lock, flags);
1880 list_for_each_entry(p, &priv->ports, node)
1881 uart_resume_port(&sci_uart_driver, &p->port);
1882 spin_unlock_irqrestore(&priv->lock, flags);
1883
1884 return 0;
1885 }
1886
1887 static const struct dev_pm_ops sci_dev_pm_ops = {
1888 .suspend = sci_suspend,
1889 .resume = sci_resume,
1890 };
1891
1892 static struct platform_driver sci_driver = {
1893 .probe = sci_probe,
1894 .remove = sci_remove,
1895 .driver = {
1896 .name = "sh-sci",
1897 .owner = THIS_MODULE,
1898 .pm = &sci_dev_pm_ops,
1899 },
1900 };
1901
1902 static int __init sci_init(void)
1903 {
1904 int ret;
1905
1906 printk(banner);
1907
1908 ret = uart_register_driver(&sci_uart_driver);
1909 if (likely(ret == 0)) {
1910 ret = platform_driver_register(&sci_driver);
1911 if (unlikely(ret))
1912 uart_unregister_driver(&sci_uart_driver);
1913 }
1914
1915 return ret;
1916 }
1917
1918 static void __exit sci_exit(void)
1919 {
1920 platform_driver_unregister(&sci_driver);
1921 uart_unregister_driver(&sci_uart_driver);
1922 }
1923
1924 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1925 early_platform_init_buffer("earlyprintk", &sci_driver,
1926 early_serial_buf, ARRAY_SIZE(early_serial_buf));
1927 #endif
1928 module_init(sci_init);
1929 module_exit(sci_exit);
1930
1931 MODULE_LICENSE("GPL");
1932 MODULE_ALIAS("platform:sh-sci");