2 * drivers/mb862xx/mb862xxfb.c
4 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
6 * (C) 2008 Anatolij Gustschin <agust@denx.de>
7 * DENX Software Engineering
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
18 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #if defined(CONFIG_OF)
23 #include <linux/of_platform.h>
25 #include "mb862xxfb.h"
26 #include "mb862xx_reg.h"
28 #define NR_PALETTE 256
29 #define MB862XX_MEM_SIZE 0x1000000
30 #define CORALP_MEM_SIZE 0x4000000
31 #define CARMINE_MEM_SIZE 0x8000000
32 #define DRV_NAME "mb862xxfb"
34 #if defined(CONFIG_SOCRATES)
35 static struct mb862xx_gc_mode socrates_gc_mode
= {
36 /* Mode for Prime View PM070WL4 TFT LCD Panel */
37 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
38 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
39 16, 0x1000000, GC_CCF_COT_133
, 0x4157ba63
44 static inline int h_total(struct fb_var_screeninfo
*var
)
46 return var
->xres
+ var
->left_margin
+
47 var
->right_margin
+ var
->hsync_len
;
50 static inline int v_total(struct fb_var_screeninfo
*var
)
52 return var
->yres
+ var
->upper_margin
+
53 var
->lower_margin
+ var
->vsync_len
;
56 static inline int hsp(struct fb_var_screeninfo
*var
)
58 return var
->xres
+ var
->right_margin
- 1;
61 static inline int vsp(struct fb_var_screeninfo
*var
)
63 return var
->yres
+ var
->lower_margin
- 1;
66 static inline int d_pitch(struct fb_var_screeninfo
*var
)
68 return var
->xres
* var
->bits_per_pixel
/ 8;
71 static inline unsigned int chan_to_field(unsigned int chan
,
72 struct fb_bitfield
*bf
)
75 chan
>>= 16 - bf
->length
;
76 return chan
<< bf
->offset
;
79 static int mb862xxfb_setcolreg(unsigned regno
,
80 unsigned red
, unsigned green
, unsigned blue
,
81 unsigned transp
, struct fb_info
*info
)
83 struct mb862xxfb_par
*par
= info
->par
;
86 switch (info
->fix
.visual
) {
87 case FB_VISUAL_TRUECOLOR
:
89 val
= chan_to_field(red
, &info
->var
.red
);
90 val
|= chan_to_field(green
, &info
->var
.green
);
91 val
|= chan_to_field(blue
, &info
->var
.blue
);
92 par
->pseudo_palette
[regno
] = val
;
95 case FB_VISUAL_PSEUDOCOLOR
:
97 val
= (red
>> 8) << 16;
98 val
|= (green
>> 8) << 8;
100 outreg(disp
, GC_L0PAL0
+ (regno
* 4), val
);
104 return 1; /* unsupported type */
109 static int mb862xxfb_check_var(struct fb_var_screeninfo
*var
,
115 dev_dbg(fbi
->dev
, "%s\n", __func__
);
117 /* check if these values fit into the registers */
118 if (var
->hsync_len
> 255 || var
->vsync_len
> 255)
121 if ((var
->xres
+ var
->right_margin
) >= 4096)
124 if ((var
->yres
+ var
->lower_margin
) > 4096)
127 if (h_total(var
) > 4096 || v_total(var
) > 4096)
130 if (var
->xres_virtual
> 4096 || var
->yres_virtual
> 4096)
133 if (var
->bits_per_pixel
<= 8)
134 var
->bits_per_pixel
= 8;
135 else if (var
->bits_per_pixel
<= 16)
136 var
->bits_per_pixel
= 16;
137 else if (var
->bits_per_pixel
<= 32)
138 var
->bits_per_pixel
= 32;
141 * can cope with 8,16 or 24/32bpp if resulting
142 * pitch is divisible by 64 without remainder
144 if (d_pitch(&fbi
->var
) % GC_L0M_L0W_UNIT
) {
147 var
->bits_per_pixel
= 0;
149 var
->bits_per_pixel
+= 8;
150 r
= d_pitch(&fbi
->var
) % GC_L0M_L0W_UNIT
;
151 } while (r
&& var
->bits_per_pixel
<= 32);
153 if (d_pitch(&fbi
->var
) % GC_L0M_L0W_UNIT
)
157 /* line length is going to be 128 bit aligned */
158 tmp
= (var
->xres
* var
->bits_per_pixel
) / 8;
162 /* set r/g/b positions and validate bpp */
163 switch (var
->bits_per_pixel
) {
165 var
->red
.length
= var
->bits_per_pixel
;
166 var
->green
.length
= var
->bits_per_pixel
;
167 var
->blue
.length
= var
->bits_per_pixel
;
169 var
->green
.offset
= 0;
170 var
->blue
.offset
= 0;
171 var
->transp
.length
= 0;
175 var
->green
.length
= 5;
176 var
->blue
.length
= 5;
177 var
->red
.offset
= 10;
178 var
->green
.offset
= 5;
179 var
->blue
.offset
= 0;
180 var
->transp
.length
= 0;
184 var
->transp
.length
= 8;
186 var
->green
.length
= 8;
187 var
->blue
.length
= 8;
188 var
->transp
.offset
= 24;
189 var
->red
.offset
= 16;
190 var
->green
.offset
= 8;
191 var
->blue
.offset
= 0;
200 * set display parameters
202 static int mb862xxfb_set_par(struct fb_info
*fbi
)
204 struct mb862xxfb_par
*par
= fbi
->par
;
205 unsigned long reg
, sc
;
207 dev_dbg(par
->dev
, "%s\n", __func__
);
208 if (par
->type
== BT_CORALP
)
209 mb862xxfb_init_accel(fbi
, fbi
->var
.xres
);
215 reg
= inreg(disp
, GC_DCM1
);
216 reg
&= ~GC_DCM01_DEN
;
217 outreg(disp
, GC_DCM1
, reg
);
219 /* set display reference clock div. */
220 sc
= par
->refclk
/ (1000000 / fbi
->var
.pixclock
) - 1;
221 reg
= inreg(disp
, GC_DCM1
);
222 reg
&= ~(GC_DCM01_CKS
| GC_DCM01_RESV
| GC_DCM01_SC
);
224 outreg(disp
, GC_DCM1
, reg
);
225 dev_dbg(par
->dev
, "SC 0x%lx\n", sc
);
227 /* disp dimension, format */
228 reg
= pack(d_pitch(&fbi
->var
) / GC_L0M_L0W_UNIT
,
229 (fbi
->var
.yres
- 1));
230 if (fbi
->var
.bits_per_pixel
== 16)
231 reg
|= GC_L0M_L0C_16
;
232 outreg(disp
, GC_L0M
, reg
);
234 if (fbi
->var
.bits_per_pixel
== 32) {
235 reg
= inreg(disp
, GC_L0EM
);
236 outreg(disp
, GC_L0EM
, reg
| GC_L0EM_L0EC_24
);
238 outreg(disp
, GC_WY_WX
, 0);
239 reg
= pack(fbi
->var
.yres
- 1, fbi
->var
.xres
);
240 outreg(disp
, GC_WH_WW
, reg
);
241 outreg(disp
, GC_L0OA0
, 0);
242 outreg(disp
, GC_L0DA0
, 0);
243 outreg(disp
, GC_L0DY_L0DX
, 0);
244 outreg(disp
, GC_L0WY_L0WX
, 0);
245 outreg(disp
, GC_L0WH_L0WW
, reg
);
247 /* both HW-cursors off */
248 reg
= inreg(disp
, GC_CPM_CUTC
);
249 reg
&= ~(GC_CPM_CEN0
| GC_CPM_CEN1
);
250 outreg(disp
, GC_CPM_CUTC
, reg
);
253 reg
= pack(fbi
->var
.xres
- 1, fbi
->var
.xres
- 1);
254 outreg(disp
, GC_HDB_HDP
, reg
);
255 reg
= pack((fbi
->var
.yres
- 1), vsp(&fbi
->var
));
256 outreg(disp
, GC_VDP_VSP
, reg
);
257 reg
= ((fbi
->var
.vsync_len
- 1) << 24) |
258 pack((fbi
->var
.hsync_len
- 1), hsp(&fbi
->var
));
259 outreg(disp
, GC_VSW_HSW_HSP
, reg
);
260 outreg(disp
, GC_HTP
, pack(h_total(&fbi
->var
) - 1, 0));
261 outreg(disp
, GC_VTR
, pack(v_total(&fbi
->var
) - 1, 0));
264 reg
= inreg(disp
, GC_DCM1
);
265 reg
|= GC_DCM01_DEN
| GC_DCM01_L0E
;
266 reg
&= ~GC_DCM01_ESY
;
267 outreg(disp
, GC_DCM1
, reg
);
271 static int mb862xxfb_pan(struct fb_var_screeninfo
*var
,
272 struct fb_info
*info
)
274 struct mb862xxfb_par
*par
= info
->par
;
277 reg
= pack(var
->yoffset
, var
->xoffset
);
278 outreg(disp
, GC_L0WY_L0WX
, reg
);
280 reg
= pack(var
->yres_virtual
, var
->xres_virtual
);
281 outreg(disp
, GC_L0WH_L0WW
, reg
);
285 static int mb862xxfb_blank(int mode
, struct fb_info
*fbi
)
287 struct mb862xxfb_par
*par
= fbi
->par
;
290 dev_dbg(fbi
->dev
, "blank mode=%d\n", mode
);
293 case FB_BLANK_POWERDOWN
:
294 reg
= inreg(disp
, GC_DCM1
);
295 reg
&= ~GC_DCM01_DEN
;
296 outreg(disp
, GC_DCM1
, reg
);
298 case FB_BLANK_UNBLANK
:
299 reg
= inreg(disp
, GC_DCM1
);
301 outreg(disp
, GC_DCM1
, reg
);
303 case FB_BLANK_NORMAL
:
304 case FB_BLANK_VSYNC_SUSPEND
:
305 case FB_BLANK_HSYNC_SUSPEND
:
312 /* framebuffer ops */
313 static struct fb_ops mb862xxfb_ops
= {
314 .owner
= THIS_MODULE
,
315 .fb_check_var
= mb862xxfb_check_var
,
316 .fb_set_par
= mb862xxfb_set_par
,
317 .fb_setcolreg
= mb862xxfb_setcolreg
,
318 .fb_blank
= mb862xxfb_blank
,
319 .fb_pan_display
= mb862xxfb_pan
,
320 .fb_fillrect
= cfb_fillrect
,
321 .fb_copyarea
= cfb_copyarea
,
322 .fb_imageblit
= cfb_imageblit
,
325 /* initialize fb_info data */
326 static int mb862xxfb_init_fbinfo(struct fb_info
*fbi
)
328 struct mb862xxfb_par
*par
= fbi
->par
;
329 struct mb862xx_gc_mode
*mode
= par
->gc_mode
;
332 fbi
->fbops
= &mb862xxfb_ops
;
333 fbi
->pseudo_palette
= par
->pseudo_palette
;
334 fbi
->screen_base
= par
->fb_base
;
335 fbi
->screen_size
= par
->mapped_vram
;
337 strcpy(fbi
->fix
.id
, DRV_NAME
);
338 fbi
->fix
.smem_start
= (unsigned long)par
->fb_base_phys
;
339 fbi
->fix
.smem_len
= par
->mapped_vram
;
340 fbi
->fix
.mmio_start
= (unsigned long)par
->mmio_base_phys
;
341 fbi
->fix
.mmio_len
= par
->mmio_len
;
342 fbi
->fix
.accel
= FB_ACCEL_NONE
;
343 fbi
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
344 fbi
->fix
.type_aux
= 0;
345 fbi
->fix
.xpanstep
= 1;
346 fbi
->fix
.ypanstep
= 1;
347 fbi
->fix
.ywrapstep
= 0;
349 reg
= inreg(disp
, GC_DCM1
);
350 if (reg
& GC_DCM01_DEN
&& reg
& GC_DCM01_L0E
) {
351 /* get the disp mode from active display cfg */
352 unsigned long sc
= ((reg
& GC_DCM01_SC
) >> 8) + 1;
353 unsigned long hsp
, vsp
, ht
, vt
;
355 dev_dbg(par
->dev
, "using bootloader's disp. mode\n");
356 fbi
->var
.pixclock
= (sc
* 1000000) / par
->refclk
;
357 fbi
->var
.xres
= (inreg(disp
, GC_HDB_HDP
) & 0x0fff) + 1;
358 reg
= inreg(disp
, GC_VDP_VSP
);
359 fbi
->var
.yres
= ((reg
>> 16) & 0x0fff) + 1;
360 vsp
= (reg
& 0x0fff) + 1;
361 fbi
->var
.xres_virtual
= fbi
->var
.xres
;
362 fbi
->var
.yres_virtual
= fbi
->var
.yres
;
363 reg
= inreg(disp
, GC_L0EM
);
364 if (reg
& GC_L0EM_L0EC_24
) {
365 fbi
->var
.bits_per_pixel
= 32;
367 reg
= inreg(disp
, GC_L0M
);
368 if (reg
& GC_L0M_L0C_16
)
369 fbi
->var
.bits_per_pixel
= 16;
371 fbi
->var
.bits_per_pixel
= 8;
373 reg
= inreg(disp
, GC_VSW_HSW_HSP
);
374 fbi
->var
.hsync_len
= ((reg
& 0xff0000) >> 16) + 1;
375 fbi
->var
.vsync_len
= ((reg
& 0x3f000000) >> 24) + 1;
376 hsp
= (reg
& 0xffff) + 1;
377 ht
= ((inreg(disp
, GC_HTP
) & 0xfff0000) >> 16) + 1;
378 fbi
->var
.right_margin
= hsp
- fbi
->var
.xres
;
379 fbi
->var
.left_margin
= ht
- hsp
- fbi
->var
.hsync_len
;
380 vt
= ((inreg(disp
, GC_VTR
) & 0xfff0000) >> 16) + 1;
381 fbi
->var
.lower_margin
= vsp
- fbi
->var
.yres
;
382 fbi
->var
.upper_margin
= vt
- vsp
- fbi
->var
.vsync_len
;
384 dev_dbg(par
->dev
, "using supplied mode\n");
385 fb_videomode_to_var(&fbi
->var
, (struct fb_videomode
*)mode
);
386 fbi
->var
.bits_per_pixel
= mode
->def_bpp
? mode
->def_bpp
: 8;
390 ret
= fb_find_mode(&fbi
->var
, fbi
, "640x480-16@60",
392 if (ret
== 0 || ret
== 4) {
394 "failed to get initial mode\n");
399 fbi
->var
.xoffset
= 0;
400 fbi
->var
.yoffset
= 0;
401 fbi
->var
.grayscale
= 0;
403 fbi
->var
.height
= -1;
405 fbi
->var
.accel_flags
= 0;
406 fbi
->var
.vmode
= FB_VMODE_NONINTERLACED
;
407 fbi
->var
.activate
= FB_ACTIVATE_NOW
;
408 fbi
->flags
= FBINFO_DEFAULT
|
410 FBINFO_FOREIGN_ENDIAN
|
412 FBINFO_HWACCEL_XPAN
|
415 /* check and possibly fix bpp */
416 if ((fbi
->fbops
->fb_check_var
)(&fbi
->var
, fbi
))
417 dev_err(par
->dev
, "check_var() failed on initial setup?\n");
419 fbi
->fix
.visual
= fbi
->var
.bits_per_pixel
== 8 ?
420 FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_TRUECOLOR
;
421 fbi
->fix
.line_length
= (fbi
->var
.xres_virtual
*
422 fbi
->var
.bits_per_pixel
) / 8;
427 * show some display controller and cursor registers
429 static ssize_t
mb862xxfb_show_dispregs(struct device
*dev
,
430 struct device_attribute
*attr
, char *buf
)
432 struct fb_info
*fbi
= dev_get_drvdata(dev
);
433 struct mb862xxfb_par
*par
= fbi
->par
;
437 for (reg
= GC_DCM0
; reg
<= GC_L0DY_L0DX
; reg
+= 4)
438 ptr
+= sprintf(ptr
, "%08x = %08x\n",
439 reg
, inreg(disp
, reg
));
441 for (reg
= GC_CPM_CUTC
; reg
<= GC_CUY1_CUX1
; reg
+= 4)
442 ptr
+= sprintf(ptr
, "%08x = %08x\n",
443 reg
, inreg(disp
, reg
));
445 for (reg
= GC_DCM1
; reg
<= GC_L0WH_L0WW
; reg
+= 4)
446 ptr
+= sprintf(ptr
, "%08x = %08x\n",
447 reg
, inreg(disp
, reg
));
449 for (reg
= 0x400; reg
<= 0x410; reg
+= 4)
450 ptr
+= sprintf(ptr
, "geo %08x = %08x\n",
451 reg
, inreg(geo
, reg
));
453 for (reg
= 0x400; reg
<= 0x410; reg
+= 4)
454 ptr
+= sprintf(ptr
, "draw %08x = %08x\n",
455 reg
, inreg(draw
, reg
));
457 for (reg
= 0x440; reg
<= 0x450; reg
+= 4)
458 ptr
+= sprintf(ptr
, "draw %08x = %08x\n",
459 reg
, inreg(draw
, reg
));
464 static DEVICE_ATTR(dispregs
, 0444, mb862xxfb_show_dispregs
, NULL
);
466 irqreturn_t
mb862xx_intr(int irq
, void *dev_id
)
468 struct mb862xxfb_par
*par
= (struct mb862xxfb_par
*) dev_id
;
469 unsigned long reg_ist
, mask
;
474 if (par
->type
== BT_CARMINE
) {
475 /* Get Interrupt Status */
476 reg_ist
= inreg(ctrl
, GC_CTRL_STATUS
);
477 mask
= inreg(ctrl
, GC_CTRL_INT_MASK
);
485 /* Clear interrupt status */
486 outreg(ctrl
, 0x0, reg_ist
);
489 reg_ist
= inreg(host
, GC_IST
);
490 mask
= inreg(host
, GC_IMASK
);
497 outreg(host
, GC_IST
, ~reg_ist
);
502 #if defined(CONFIG_FB_MB862XX_LIME)
504 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
506 static int mb862xx_gdc_init(struct mb862xxfb_par
*par
)
508 unsigned long ccf
, mmr
;
509 unsigned long ver
, rev
;
514 #if defined(CONFIG_FB_PRE_INIT_FB)
517 par
->host
= par
->mmio_base
;
518 par
->i2c
= par
->mmio_base
+ MB862XX_I2C_BASE
;
519 par
->disp
= par
->mmio_base
+ MB862XX_DISP_BASE
;
520 par
->cap
= par
->mmio_base
+ MB862XX_CAP_BASE
;
521 par
->draw
= par
->mmio_base
+ MB862XX_DRAW_BASE
;
522 par
->geo
= par
->mmio_base
+ MB862XX_GEO_BASE
;
523 par
->pio
= par
->mmio_base
+ MB862XX_PIO_BASE
;
525 par
->refclk
= GC_DISP_REFCLK_400
;
527 ver
= inreg(host
, GC_CID
);
528 rev
= inreg(pio
, GC_REVISION
);
529 if ((ver
== 0x303) && (rev
& 0xffffff00) == 0x20050100) {
530 dev_info(par
->dev
, "Fujitsu Lime v1.%d found\n",
533 ccf
= par
->gc_mode
? par
->gc_mode
->ccf
: GC_CCF_COT_100
;
534 mmr
= par
->gc_mode
? par
->gc_mode
->mmr
: 0x414fb7f2;
536 dev_info(par
->dev
, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver
, rev
);
540 if (!par
->pre_init
) {
541 outreg(host
, GC_CCF
, ccf
);
543 outreg(host
, GC_MMR
, mmr
);
547 /* interrupt status */
548 outreg(host
, GC_IST
, 0);
549 outreg(host
, GC_IMASK
, GC_INT_EN
);
553 static int __devinit
of_platform_mb862xx_probe(struct of_device
*ofdev
,
554 const struct of_device_id
*id
)
556 struct device_node
*np
= ofdev
->node
;
557 struct device
*dev
= &ofdev
->dev
;
558 struct mb862xxfb_par
*par
;
559 struct fb_info
*info
;
561 resource_size_t res_size
;
562 unsigned long ret
= -ENODEV
;
564 if (of_address_to_resource(np
, 0, &res
)) {
565 dev_err(dev
, "Invalid address\n");
569 info
= framebuffer_alloc(sizeof(struct mb862xxfb_par
), dev
);
571 dev_err(dev
, "cannot allocate framebuffer\n");
579 par
->irq
= irq_of_parse_and_map(np
, 0);
580 if (par
->irq
== NO_IRQ
) {
581 dev_err(dev
, "failed to map irq\n");
586 res_size
= 1 + res
.end
- res
.start
;
587 par
->res
= request_mem_region(res
.start
, res_size
, DRV_NAME
);
588 if (par
->res
== NULL
) {
589 dev_err(dev
, "Cannot claim framebuffer/mmio\n");
594 #if defined(CONFIG_SOCRATES)
595 par
->gc_mode
= &socrates_gc_mode
;
598 par
->fb_base_phys
= res
.start
;
599 par
->mmio_base_phys
= res
.start
+ MB862XX_MMIO_BASE
;
600 par
->mmio_len
= MB862XX_MMIO_SIZE
;
602 par
->mapped_vram
= par
->gc_mode
->max_vram
;
604 par
->mapped_vram
= MB862XX_MEM_SIZE
;
606 par
->fb_base
= ioremap(par
->fb_base_phys
, par
->mapped_vram
);
607 if (par
->fb_base
== NULL
) {
608 dev_err(dev
, "Cannot map framebuffer\n");
612 par
->mmio_base
= ioremap(par
->mmio_base_phys
, par
->mmio_len
);
613 if (par
->mmio_base
== NULL
) {
614 dev_err(dev
, "Cannot map registers\n");
618 dev_dbg(dev
, "fb phys 0x%llx 0x%lx\n",
619 (u64
)par
->fb_base_phys
, (ulong
)par
->mapped_vram
);
620 dev_dbg(dev
, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
621 (u64
)par
->mmio_base_phys
, (ulong
)par
->mmio_len
, par
->irq
);
623 if (mb862xx_gdc_init(par
))
626 if (request_irq(par
->irq
, mb862xx_intr
, IRQF_DISABLED
,
627 DRV_NAME
, (void *)par
)) {
628 dev_err(dev
, "Cannot request irq\n");
632 mb862xxfb_init_fbinfo(info
);
634 if (fb_alloc_cmap(&info
->cmap
, NR_PALETTE
, 0) < 0) {
635 dev_err(dev
, "Could not allocate cmap for fb_info.\n");
639 if ((info
->fbops
->fb_set_par
)(info
))
640 dev_err(dev
, "set_var() failed on initial setup?\n");
642 if (register_framebuffer(info
)) {
643 dev_err(dev
, "failed to register framebuffer\n");
647 dev_set_drvdata(dev
, info
);
649 if (device_create_file(dev
, &dev_attr_dispregs
))
650 dev_err(dev
, "Can't create sysfs regdump file\n");
654 fb_dealloc_cmap(&info
->cmap
);
656 outreg(host
, GC_IMASK
, 0);
657 free_irq(par
->irq
, (void *)par
);
659 iounmap(par
->mmio_base
);
661 iounmap(par
->fb_base
);
663 release_mem_region(res
.start
, res_size
);
665 irq_dispose_mapping(par
->irq
);
667 dev_set_drvdata(dev
, NULL
);
668 framebuffer_release(info
);
672 static int __devexit
of_platform_mb862xx_remove(struct of_device
*ofdev
)
674 struct fb_info
*fbi
= dev_get_drvdata(&ofdev
->dev
);
675 struct mb862xxfb_par
*par
= fbi
->par
;
676 resource_size_t res_size
= 1 + par
->res
->end
- par
->res
->start
;
679 dev_dbg(fbi
->dev
, "%s release\n", fbi
->fix
.id
);
682 reg
= inreg(disp
, GC_DCM1
);
683 reg
&= ~(GC_DCM01_DEN
| GC_DCM01_L0E
);
684 outreg(disp
, GC_DCM1
, reg
);
686 /* disable interrupts */
687 outreg(host
, GC_IMASK
, 0);
689 free_irq(par
->irq
, (void *)par
);
690 irq_dispose_mapping(par
->irq
);
692 device_remove_file(&ofdev
->dev
, &dev_attr_dispregs
);
694 unregister_framebuffer(fbi
);
695 fb_dealloc_cmap(&fbi
->cmap
);
697 iounmap(par
->mmio_base
);
698 iounmap(par
->fb_base
);
700 dev_set_drvdata(&ofdev
->dev
, NULL
);
701 release_mem_region(par
->res
->start
, res_size
);
702 framebuffer_release(fbi
);
709 static struct of_device_id __devinitdata of_platform_mb862xx_tbl
[] = {
710 { .compatible
= "fujitsu,MB86276", },
711 { .compatible
= "fujitsu,lime", },
712 { .compatible
= "fujitsu,MB86277", },
713 { .compatible
= "fujitsu,mint", },
714 { .compatible
= "fujitsu,MB86293", },
715 { .compatible
= "fujitsu,MB86294", },
716 { .compatible
= "fujitsu,coral", },
720 static struct of_platform_driver of_platform_mb862xxfb_driver
= {
721 .owner
= THIS_MODULE
,
723 .match_table
= of_platform_mb862xx_tbl
,
724 .probe
= of_platform_mb862xx_probe
,
725 .remove
= __devexit_p(of_platform_mb862xx_remove
),
729 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
730 static int coralp_init(struct mb862xxfb_par
*par
)
734 par
->host
= par
->mmio_base
;
735 par
->i2c
= par
->mmio_base
+ MB862XX_I2C_BASE
;
736 par
->disp
= par
->mmio_base
+ MB862XX_DISP_BASE
;
737 par
->cap
= par
->mmio_base
+ MB862XX_CAP_BASE
;
738 par
->draw
= par
->mmio_base
+ MB862XX_DRAW_BASE
;
739 par
->geo
= par
->mmio_base
+ MB862XX_GEO_BASE
;
740 par
->pio
= par
->mmio_base
+ MB862XX_PIO_BASE
;
742 par
->refclk
= GC_DISP_REFCLK_400
;
744 ver
= inreg(host
, GC_CID
);
745 cn
= (ver
& GC_CID_CNAME_MSK
) >> 8;
746 ver
= ver
& GC_CID_VERSION_MSK
;
748 dev_info(par
->dev
, "Fujitsu Coral-%s GDC Rev.%d found\n",\
749 (ver
== 6) ? "P" : (ver
== 8) ? "PA" : "?",
750 par
->pdev
->revision
);
751 outreg(host
, GC_CCF
, GC_CCF_CGE_166
| GC_CCF_COT_133
);
753 outreg(host
, GC_MMR
, GC_MMR_CORALP_EVB_VAL
);
755 /* Clear interrupt status */
756 outreg(host
, GC_IST
, 0);
763 static int init_dram_ctrl(struct mb862xxfb_par
*par
)
768 * Set io mode first! Spec. says IC may be destroyed
769 * if not set to SSTL2/LVCMOS before init.
771 outreg(dram_ctrl
, GC_DCTL_IOCONT1_IOCONT0
, GC_EVB_DCTL_IOCONT1_IOCONT0
);
774 outreg(dram_ctrl
, GC_DCTL_MODE_ADD
, GC_EVB_DCTL_MODE_ADD
);
775 outreg(dram_ctrl
, GC_DCTL_SETTIME1_EMODE
, GC_EVB_DCTL_SETTIME1_EMODE
);
776 outreg(dram_ctrl
, GC_DCTL_REFRESH_SETTIME2
,
777 GC_EVB_DCTL_REFRESH_SETTIME2
);
778 outreg(dram_ctrl
, GC_DCTL_RSV2_RSV1
, GC_EVB_DCTL_RSV2_RSV1
);
779 outreg(dram_ctrl
, GC_DCTL_DDRIF2_DDRIF1
, GC_EVB_DCTL_DDRIF2_DDRIF1
);
780 outreg(dram_ctrl
, GC_DCTL_RSV0_STATES
, GC_EVB_DCTL_RSV0_STATES
);
782 /* DLL reset done? */
783 while ((inreg(dram_ctrl
, GC_DCTL_RSV0_STATES
) & GC_DCTL_STATES_MSK
)) {
784 udelay(GC_DCTL_INIT_WAIT_INTERVAL
);
785 if (i
++ > GC_DCTL_INIT_WAIT_CNT
) {
786 dev_err(par
->dev
, "VRAM init failed.\n");
790 outreg(dram_ctrl
, GC_DCTL_MODE_ADD
, GC_EVB_DCTL_MODE_ADD_AFT_RST
);
791 outreg(dram_ctrl
, GC_DCTL_RSV0_STATES
, GC_EVB_DCTL_RSV0_STATES_AFT_RST
);
795 static int carmine_init(struct mb862xxfb_par
*par
)
799 par
->ctrl
= par
->mmio_base
+ MB86297_CTRL_BASE
;
800 par
->i2c
= par
->mmio_base
+ MB86297_I2C_BASE
;
801 par
->disp
= par
->mmio_base
+ MB86297_DISP0_BASE
;
802 par
->disp1
= par
->mmio_base
+ MB86297_DISP1_BASE
;
803 par
->cap
= par
->mmio_base
+ MB86297_CAP0_BASE
;
804 par
->cap1
= par
->mmio_base
+ MB86297_CAP1_BASE
;
805 par
->draw
= par
->mmio_base
+ MB86297_DRAW_BASE
;
806 par
->dram_ctrl
= par
->mmio_base
+ MB86297_DRAMCTRL_BASE
;
807 par
->wrback
= par
->mmio_base
+ MB86297_WRBACK_BASE
;
809 par
->refclk
= GC_DISP_REFCLK_533
;
812 reg
= GC_CTRL_CLK_EN_DRAM
| GC_CTRL_CLK_EN_2D3D
| GC_CTRL_CLK_EN_DISP0
;
813 outreg(ctrl
, GC_CTRL_CLK_ENABLE
, reg
);
815 /* check for engine module revision */
816 if (inreg(draw
, GC_2D3D_REV
) == GC_RE_REVISION
)
817 dev_info(par
->dev
, "Fujitsu Carmine GDC Rev.%d found\n",
818 par
->pdev
->revision
);
822 reg
&= ~GC_CTRL_CLK_EN_2D3D
;
823 outreg(ctrl
, GC_CTRL_CLK_ENABLE
, reg
);
826 if (init_dram_ctrl(par
) < 0)
829 outreg(ctrl
, GC_CTRL_INT_MASK
, 0);
833 outreg(ctrl
, GC_CTRL_CLK_ENABLE
, 0);
837 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par
*par
)
841 return coralp_init(par
);
843 return carmine_init(par
);
849 #define CHIP_ID(id) \
850 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
852 static struct pci_device_id mb862xx_pci_tbl
[] __devinitdata
= {
853 /* MB86295/MB86296 */
854 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP
),
855 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA
),
857 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE
),
861 MODULE_DEVICE_TABLE(pci
, mb862xx_pci_tbl
);
863 static int __devinit
mb862xx_pci_probe(struct pci_dev
*pdev
,
864 const struct pci_device_id
*ent
)
866 struct mb862xxfb_par
*par
;
867 struct fb_info
*info
;
868 struct device
*dev
= &pdev
->dev
;
871 ret
= pci_enable_device(pdev
);
873 dev_err(dev
, "Cannot enable PCI device\n");
877 info
= framebuffer_alloc(sizeof(struct mb862xxfb_par
), dev
);
879 dev_err(dev
, "framebuffer alloc failed\n");
888 par
->irq
= pdev
->irq
;
890 ret
= pci_request_regions(pdev
, DRV_NAME
);
892 dev_err(dev
, "Cannot reserve region(s) for PCI device\n");
896 switch (pdev
->device
) {
897 case PCI_DEVICE_ID_FUJITSU_CORALP
:
898 case PCI_DEVICE_ID_FUJITSU_CORALPA
:
899 par
->fb_base_phys
= pci_resource_start(par
->pdev
, 0);
900 par
->mapped_vram
= CORALP_MEM_SIZE
;
901 par
->mmio_base_phys
= par
->fb_base_phys
+ MB862XX_MMIO_BASE
;
902 par
->mmio_len
= MB862XX_MMIO_SIZE
;
903 par
->type
= BT_CORALP
;
905 case PCI_DEVICE_ID_FUJITSU_CARMINE
:
906 par
->fb_base_phys
= pci_resource_start(par
->pdev
, 2);
907 par
->mmio_base_phys
= pci_resource_start(par
->pdev
, 3);
908 par
->mmio_len
= pci_resource_len(par
->pdev
, 3);
909 par
->mapped_vram
= CARMINE_MEM_SIZE
;
910 par
->type
= BT_CARMINE
;
913 /* should never occur */
917 par
->fb_base
= ioremap(par
->fb_base_phys
, par
->mapped_vram
);
918 if (par
->fb_base
== NULL
) {
919 dev_err(dev
, "Cannot map framebuffer\n");
923 par
->mmio_base
= ioremap(par
->mmio_base_phys
, par
->mmio_len
);
924 if (par
->mmio_base
== NULL
) {
925 dev_err(dev
, "Cannot map registers\n");
930 dev_dbg(dev
, "fb phys 0x%llx 0x%lx\n",
931 (unsigned long long)par
->fb_base_phys
, (ulong
)par
->mapped_vram
);
932 dev_dbg(dev
, "mmio phys 0x%llx 0x%lx\n",
933 (unsigned long long)par
->mmio_base_phys
, (ulong
)par
->mmio_len
);
935 if (mb862xx_pci_gdc_init(par
))
938 if (request_irq(par
->irq
, mb862xx_intr
, IRQF_DISABLED
| IRQF_SHARED
,
939 DRV_NAME
, (void *)par
)) {
940 dev_err(dev
, "Cannot request irq\n");
944 mb862xxfb_init_fbinfo(info
);
946 if (fb_alloc_cmap(&info
->cmap
, NR_PALETTE
, 0) < 0) {
947 dev_err(dev
, "Could not allocate cmap for fb_info.\n");
952 if ((info
->fbops
->fb_set_par
)(info
))
953 dev_err(dev
, "set_var() failed on initial setup?\n");
955 ret
= register_framebuffer(info
);
957 dev_err(dev
, "failed to register framebuffer\n");
961 pci_set_drvdata(pdev
, info
);
963 if (device_create_file(dev
, &dev_attr_dispregs
))
964 dev_err(dev
, "Can't create sysfs regdump file\n");
966 if (par
->type
== BT_CARMINE
)
967 outreg(ctrl
, GC_CTRL_INT_MASK
, GC_CARMINE_INT_EN
);
969 outreg(host
, GC_IMASK
, GC_INT_EN
);
974 fb_dealloc_cmap(&info
->cmap
);
976 free_irq(par
->irq
, (void *)par
);
978 iounmap(par
->mmio_base
);
980 iounmap(par
->fb_base
);
982 pci_release_regions(pdev
);
984 framebuffer_release(info
);
986 pci_disable_device(pdev
);
991 static void __devexit
mb862xx_pci_remove(struct pci_dev
*pdev
)
993 struct fb_info
*fbi
= pci_get_drvdata(pdev
);
994 struct mb862xxfb_par
*par
= fbi
->par
;
997 dev_dbg(fbi
->dev
, "%s release\n", fbi
->fix
.id
);
1000 reg
= inreg(disp
, GC_DCM1
);
1001 reg
&= ~(GC_DCM01_DEN
| GC_DCM01_L0E
);
1002 outreg(disp
, GC_DCM1
, reg
);
1004 if (par
->type
== BT_CARMINE
) {
1005 outreg(ctrl
, GC_CTRL_INT_MASK
, 0);
1006 outreg(ctrl
, GC_CTRL_CLK_ENABLE
, 0);
1008 outreg(host
, GC_IMASK
, 0);
1011 device_remove_file(&pdev
->dev
, &dev_attr_dispregs
);
1013 pci_set_drvdata(pdev
, NULL
);
1014 unregister_framebuffer(fbi
);
1015 fb_dealloc_cmap(&fbi
->cmap
);
1017 free_irq(par
->irq
, (void *)par
);
1018 iounmap(par
->mmio_base
);
1019 iounmap(par
->fb_base
);
1021 pci_release_regions(pdev
);
1022 framebuffer_release(fbi
);
1023 pci_disable_device(pdev
);
1026 static struct pci_driver mb862xxfb_pci_driver
= {
1028 .id_table
= mb862xx_pci_tbl
,
1029 .probe
= mb862xx_pci_probe
,
1030 .remove
= __devexit_p(mb862xx_pci_remove
),
1034 static int __devinit
mb862xxfb_init(void)
1038 #if defined(CONFIG_FB_MB862XX_LIME)
1039 ret
= of_register_platform_driver(&of_platform_mb862xxfb_driver
);
1041 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1042 ret
= pci_register_driver(&mb862xxfb_pci_driver
);
1047 static void __exit
mb862xxfb_exit(void)
1049 #if defined(CONFIG_FB_MB862XX_LIME)
1050 of_unregister_platform_driver(&of_platform_mb862xxfb_driver
);
1052 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1053 pci_unregister_driver(&mb862xxfb_pci_driver
);
1057 module_init(mb862xxfb_init
);
1058 module_exit(mb862xxfb_exit
);
1060 MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1061 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1062 MODULE_LICENSE("GPL v2");