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Linux 2.6.34-rc3
[pohmelfs.git] / drivers / video / mx3fb.c
blob772ba3f45e6f511d78bf2035046dd7829244277b
1 /*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
20 #include <linux/fb.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/console.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29
30 #include <mach/hardware.h>
31 #include <mach/ipu.h>
32 #include <mach/mx3fb.h>
33
34 #include <asm/io.h>
35 #include <asm/uaccess.h>
36
37 #define MX3FB_NAME "mx3_sdc_fb"
38
39 #define MX3FB_REG_OFFSET 0xB4
40
41 /* SDC Registers */
42 #define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET)
43 #define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET)
44 #define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET)
45 #define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET)
46 #define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET)
47 #define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET)
48 #define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET)
49 #define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET)
50 #define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET)
51 #define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET)
52 #define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET)
53
54 /* Register bits */
55 #define SDC_COM_TFT_COLOR 0x00000001UL
56 #define SDC_COM_FG_EN 0x00000010UL
57 #define SDC_COM_GWSEL 0x00000020UL
58 #define SDC_COM_GLB_A 0x00000040UL
59 #define SDC_COM_KEY_COLOR_G 0x00000080UL
60 #define SDC_COM_BG_EN 0x00000200UL
61 #define SDC_COM_SHARP 0x00001000UL
62
63 #define SDC_V_SYNC_WIDTH_L 0x00000001UL
64
65 /* Display Interface registers */
66 #define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET)
67 #define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET)
68 #define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET)
69 #define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET)
70 #define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET)
71 #define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET)
72 #define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET)
73 #define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET)
74 #define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET)
75 #define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET)
76 #define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET)
77 #define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET)
78 #define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET)
79 #define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET)
80 #define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET)
81 #define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET)
82 #define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET)
83 #define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET)
84 #define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET)
85 #define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET)
86 #define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET)
87 #define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET)
88 #define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET)
89 #define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET)
90 #define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET)
91 #define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET)
92 #define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET)
93 #define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET)
94 #define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET)
95 #define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET)
96 #define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET)
97 #define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET)
98 #define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET)
99 #define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET)
100 #define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET)
101 #define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET)
102 #define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET)
103 #define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET)
104 #define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET)
105
106 /* DI_DISP_SIG_POL bits */
107 #define DI_D3_VSYNC_POL_SHIFT 28
108 #define DI_D3_HSYNC_POL_SHIFT 27
109 #define DI_D3_DRDY_SHARP_POL_SHIFT 26
110 #define DI_D3_CLK_POL_SHIFT 25
111 #define DI_D3_DATA_POL_SHIFT 24
112
113 /* DI_DISP_IF_CONF bits */
114 #define DI_D3_CLK_IDLE_SHIFT 26
115 #define DI_D3_CLK_SEL_SHIFT 25
116 #define DI_D3_DATAMSK_SHIFT 24
117
118 enum ipu_panel {
119 IPU_PANEL_SHARP_TFT,
120 IPU_PANEL_TFT,
121 };
122
123 struct ipu_di_signal_cfg {
124 unsigned datamask_en:1;
125 unsigned clksel_en:1;
126 unsigned clkidle_en:1;
127 unsigned data_pol:1; /* true = inverted */
128 unsigned clk_pol:1; /* true = rising edge */
129 unsigned enable_pol:1;
130 unsigned Hsync_pol:1; /* true = active high */
131 unsigned Vsync_pol:1;
132 };
133
134 static const struct fb_videomode mx3fb_modedb[] = {
135 {
136 /* 240x320 @ 60 Hz */
137 .name = "Sharp-QVGA",
138 .refresh = 60,
139 .xres = 240,
140 .yres = 320,
141 .pixclock = 185925,
142 .left_margin = 9,
143 .right_margin = 16,
144 .upper_margin = 7,
145 .lower_margin = 9,
146 .hsync_len = 1,
147 .vsync_len = 1,
148 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
149 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
150 FB_SYNC_CLK_IDLE_EN,
151 .vmode = FB_VMODE_NONINTERLACED,
152 .flag = 0,
153 }, {
154 /* 240x33 @ 60 Hz */
155 .name = "Sharp-CLI",
156 .refresh = 60,
157 .xres = 240,
158 .yres = 33,
159 .pixclock = 185925,
160 .left_margin = 9,
161 .right_margin = 16,
162 .upper_margin = 7,
163 .lower_margin = 9 + 287,
164 .hsync_len = 1,
165 .vsync_len = 1,
166 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
167 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
168 FB_SYNC_CLK_IDLE_EN,
169 .vmode = FB_VMODE_NONINTERLACED,
170 .flag = 0,
171 }, {
172 /* 640x480 @ 60 Hz */
173 .name = "NEC-VGA",
174 .refresh = 60,
175 .xres = 640,
176 .yres = 480,
177 .pixclock = 38255,
178 .left_margin = 144,
179 .right_margin = 0,
180 .upper_margin = 34,
181 .lower_margin = 40,
182 .hsync_len = 1,
183 .vsync_len = 1,
184 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
185 .vmode = FB_VMODE_NONINTERLACED,
186 .flag = 0,
187 }, {
188 /* NTSC TV output */
189 .name = "TV-NTSC",
190 .refresh = 60,
191 .xres = 640,
192 .yres = 480,
193 .pixclock = 37538,
194 .left_margin = 38,
195 .right_margin = 858 - 640 - 38 - 3,
196 .upper_margin = 36,
197 .lower_margin = 518 - 480 - 36 - 1,
198 .hsync_len = 3,
199 .vsync_len = 1,
200 .sync = 0,
201 .vmode = FB_VMODE_NONINTERLACED,
202 .flag = 0,
203 }, {
204 /* PAL TV output */
205 .name = "TV-PAL",
206 .refresh = 50,
207 .xres = 640,
208 .yres = 480,
209 .pixclock = 37538,
210 .left_margin = 38,
211 .right_margin = 960 - 640 - 38 - 32,
212 .upper_margin = 32,
213 .lower_margin = 555 - 480 - 32 - 3,
214 .hsync_len = 32,
215 .vsync_len = 3,
216 .sync = 0,
217 .vmode = FB_VMODE_NONINTERLACED,
218 .flag = 0,
219 }, {
220 /* TV output VGA mode, 640x480 @ 65 Hz */
221 .name = "TV-VGA",
222 .refresh = 60,
223 .xres = 640,
224 .yres = 480,
225 .pixclock = 40574,
226 .left_margin = 35,
227 .right_margin = 45,
228 .upper_margin = 9,
229 .lower_margin = 1,
230 .hsync_len = 46,
231 .vsync_len = 5,
232 .sync = 0,
233 .vmode = FB_VMODE_NONINTERLACED,
234 .flag = 0,
235 },
236 };
237
238 struct mx3fb_data {
239 struct fb_info *fbi;
240 int backlight_level;
241 void __iomem *reg_base;
242 spinlock_t lock;
243 struct device *dev;
244
245 uint32_t h_start_width;
246 uint32_t v_start_width;
247 };
248
249 struct dma_chan_request {
250 struct mx3fb_data *mx3fb;
251 enum ipu_channel id;
252 };
253
254 /* MX3 specific framebuffer information. */
255 struct mx3fb_info {
256 int blank;
257 enum ipu_channel ipu_ch;
258 uint32_t cur_ipu_buf;
259
260 u32 pseudo_palette[16];
261
262 struct completion flip_cmpl;
263 struct mutex mutex; /* Protects fb-ops */
264 struct mx3fb_data *mx3fb;
265 struct idmac_channel *idmac_channel;
266 struct dma_async_tx_descriptor *txd;
267 dma_cookie_t cookie;
268 struct scatterlist sg[2];
269
270 u32 sync; /* preserve var->sync flags */
271 };
272
273 static void mx3fb_dma_done(void *);
274
275 /* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
276 static const char *fb_mode;
277 static unsigned long default_bpp = 16;
278
279 static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
280 {
281 return __raw_readl(mx3fb->reg_base + reg);
282 }
283
284 static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
285 {
286 __raw_writel(value, mx3fb->reg_base + reg);
287 }
288
289 static const uint32_t di_mappings[] = {
290 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */
291 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */
292 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */
293 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */
294 };
295
296 static void sdc_fb_init(struct mx3fb_info *fbi)
297 {
298 struct mx3fb_data *mx3fb = fbi->mx3fb;
299 uint32_t reg;
300
301 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
302
303 mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
304 }
305
306 /* Returns enabled flag before uninit */
307 static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi)
308 {
309 struct mx3fb_data *mx3fb = fbi->mx3fb;
310 uint32_t reg;
311
312 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
313
314 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
315
316 return reg & SDC_COM_BG_EN;
317 }
318
319 static void sdc_enable_channel(struct mx3fb_info *mx3_fbi)
320 {
321 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
322 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
323 struct dma_chan *dma_chan = &ichan->dma_chan;
324 unsigned long flags;
325 dma_cookie_t cookie;
326
327 if (mx3_fbi->txd)
328 dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
329 to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg);
330 else
331 dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi);
332
333 /* This enables the channel */
334 if (mx3_fbi->cookie < 0) {
335 mx3_fbi->txd = dma_chan->device->device_prep_slave_sg(dma_chan,
336 &mx3_fbi->sg[0], 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT);
337 if (!mx3_fbi->txd) {
338 dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
339 dma_chan->chan_id);
340 return;
341 }
342
343 mx3_fbi->txd->callback_param = mx3_fbi->txd;
344 mx3_fbi->txd->callback = mx3fb_dma_done;
345
346 cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd);
347 dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
348 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
349 } else {
350 if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) {
351 dev_err(mx3fb->dev, "Cannot enable channel %d\n",
352 dma_chan->chan_id);
353 return;
354 }
355
356 /* Just re-activate the same buffer */
357 dma_async_issue_pending(dma_chan);
358 cookie = mx3_fbi->cookie;
359 dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
360 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
361 }
362
363 if (cookie >= 0) {
364 spin_lock_irqsave(&mx3fb->lock, flags);
365 sdc_fb_init(mx3_fbi);
366 mx3_fbi->cookie = cookie;
367 spin_unlock_irqrestore(&mx3fb->lock, flags);
368 }
369
370 /*
371 * Attention! Without this msleep the channel keeps generating
372 * interrupts. Next sdc_set_brightness() is going to be called
373 * from mx3fb_blank().
374 */
375 msleep(2);
376 }
377
378 static void sdc_disable_channel(struct mx3fb_info *mx3_fbi)
379 {
380 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
381 uint32_t enabled;
382 unsigned long flags;
383
384 spin_lock_irqsave(&mx3fb->lock, flags);
385
386 enabled = sdc_fb_uninit(mx3_fbi);
387
388 spin_unlock_irqrestore(&mx3fb->lock, flags);
389
390 mx3_fbi->txd->chan->device->device_terminate_all(mx3_fbi->txd->chan);
391 mx3_fbi->txd = NULL;
392 mx3_fbi->cookie = -EINVAL;
393 }
394
395 /**
396 * sdc_set_window_pos() - set window position of the respective plane.
397 * @mx3fb: mx3fb context.
398 * @channel: IPU DMAC channel ID.
399 * @x_pos: X coordinate relative to the top left corner to place window at.
400 * @y_pos: Y coordinate relative to the top left corner to place window at.
401 * @return: 0 on success or negative error code on failure.
402 */
403 static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
404 int16_t x_pos, int16_t y_pos)
405 {
406 if (channel != IDMAC_SDC_0)
407 return -EINVAL;
408
409 x_pos += mx3fb->h_start_width;
410 y_pos += mx3fb->v_start_width;
411
412 mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
413 return 0;
414 }
415
416 /**
417 * sdc_init_panel() - initialize a synchronous LCD panel.
418 * @mx3fb: mx3fb context.
419 * @panel: panel type.
420 * @pixel_clk: desired pixel clock frequency in Hz.
421 * @width: width of panel in pixels.
422 * @height: height of panel in pixels.
423 * @pixel_fmt: pixel format of buffer as FOURCC ASCII code.
424 * @h_start_width: number of pixel clocks between the HSYNC signal pulse
425 * and the start of valid data.
426 * @h_sync_width: width of the HSYNC signal in units of pixel clocks.
427 * @h_end_width: number of pixel clocks between the end of valid data
428 * and the HSYNC signal for next line.
429 * @v_start_width: number of lines between the VSYNC signal pulse and the
430 * start of valid data.
431 * @v_sync_width: width of the VSYNC signal in units of lines
432 * @v_end_width: number of lines between the end of valid data and the
433 * VSYNC signal for next frame.
434 * @sig: bitfield of signal polarities for LCD interface.
435 * @return: 0 on success or negative error code on failure.
436 */
437 static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
438 uint32_t pixel_clk,
439 uint16_t width, uint16_t height,
440 enum pixel_fmt pixel_fmt,
441 uint16_t h_start_width, uint16_t h_sync_width,
442 uint16_t h_end_width, uint16_t v_start_width,
443 uint16_t v_sync_width, uint16_t v_end_width,
444 struct ipu_di_signal_cfg sig)
445 {
446 unsigned long lock_flags;
447 uint32_t reg;
448 uint32_t old_conf;
449 uint32_t div;
450 struct clk *ipu_clk;
451
452 dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
453
454 if (v_sync_width == 0 || h_sync_width == 0)
455 return -EINVAL;
456
457 /* Init panel size and blanking periods */
458 reg = ((uint32_t) (h_sync_width - 1) << 26) |
459 ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
460 mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
461
462 #ifdef DEBUG
463 printk(KERN_CONT " hor_conf %x,", reg);
464 #endif
465
466 reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
467 ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
468 mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
469
470 #ifdef DEBUG
471 printk(KERN_CONT " ver_conf %x\n", reg);
472 #endif
473
474 mx3fb->h_start_width = h_start_width;
475 mx3fb->v_start_width = v_start_width;
476
477 switch (panel) {
478 case IPU_PANEL_SHARP_TFT:
479 mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
480 mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
481 mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
482 break;
483 case IPU_PANEL_TFT:
484 mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
485 break;
486 default:
487 return -EINVAL;
488 }
489
490 /* Init clocking */
491
492 /*
493 * Calculate divider: fractional part is 4 bits so simply multiple by
494 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
495 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
496 */
497 ipu_clk = clk_get(mx3fb->dev, NULL);
498 if (!IS_ERR(ipu_clk)) {
499 div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
500 clk_put(ipu_clk);
501 } else {
502 div = 0;
503 }
504
505 if (div < 0x40) { /* Divider less than 4 */
506 dev_dbg(mx3fb->dev,
507 "InitPanel() - Pixel clock divider less than 4\n");
508 div = 0x40;
509 }
510
511 dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
512 pixel_clk, div >> 4, (div & 7) * 125);
513
514 spin_lock_irqsave(&mx3fb->lock, lock_flags);
515
516 /*
517 * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
518 * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
519 * debug. DISP3_IF_CLK_UP_WR is 0
520 */
521 mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
522
523 /* DI settings */
524 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
525 old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
526 sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
527 sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
528 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
529
530 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
531 old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
532 sig.clk_pol << DI_D3_CLK_POL_SHIFT |
533 sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
534 sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
535 sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
536 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
537
538 switch (pixel_fmt) {
539 case IPU_PIX_FMT_RGB24:
540 mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP);
541 mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP);
542 mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP);
543 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
544 ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC);
545 break;
546 case IPU_PIX_FMT_RGB666:
547 mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP);
548 mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP);
549 mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP);
550 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
551 ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC);
552 break;
553 case IPU_PIX_FMT_BGR666:
554 mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP);
555 mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP);
556 mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP);
557 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
558 ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC);
559 break;
560 default:
561 mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP);
562 mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP);
563 mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP);
564 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
565 ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC);
566 break;
567 }
568
569 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
570
571 dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
572 mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
573 dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
574 mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
575 dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
576 mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
577
578 return 0;
579 }
580
581 /**
582 * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
583 * @mx3fb: mx3fb context.
584 * @channel: IPU DMAC channel ID.
585 * @enable: boolean to enable or disable color keyl.
586 * @color_key: 24-bit RGB color to use as transparent color key.
587 * @return: 0 on success or negative error code on failure.
588 */
589 static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
590 bool enable, uint32_t color_key)
591 {
592 uint32_t reg, sdc_conf;
593 unsigned long lock_flags;
594
595 spin_lock_irqsave(&mx3fb->lock, lock_flags);
596
597 sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
598 if (channel == IDMAC_SDC_0)
599 sdc_conf &= ~SDC_COM_GWSEL;
600 else
601 sdc_conf |= SDC_COM_GWSEL;
602
603 if (enable) {
604 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
605 mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
606 SDC_GW_CTRL);
607
608 sdc_conf |= SDC_COM_KEY_COLOR_G;
609 } else {
610 sdc_conf &= ~SDC_COM_KEY_COLOR_G;
611 }
612 mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
613
614 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
615
616 return 0;
617 }
618
619 /**
620 * sdc_set_global_alpha() - set global alpha blending modes.
621 * @mx3fb: mx3fb context.
622 * @enable: boolean to enable or disable global alpha blending. If disabled,
623 * per pixel blending is used.
624 * @alpha: global alpha value.
625 * @return: 0 on success or negative error code on failure.
626 */
627 static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
628 {
629 uint32_t reg;
630 unsigned long lock_flags;
631
632 spin_lock_irqsave(&mx3fb->lock, lock_flags);
633
634 if (enable) {
635 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
636 mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
637
638 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
639 mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
640 } else {
641 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
642 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
643 }
644
645 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
646
647 return 0;
648 }
649
650 static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
651 {
652 dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value);
653 /* This might be board-specific */
654 mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
655 return;
656 }
657
658 static uint32_t bpp_to_pixfmt(int bpp)
659 {
660 uint32_t pixfmt = 0;
661 switch (bpp) {
662 case 24:
663 pixfmt = IPU_PIX_FMT_BGR24;
664 break;
665 case 32:
666 pixfmt = IPU_PIX_FMT_BGR32;
667 break;
668 case 16:
669 pixfmt = IPU_PIX_FMT_RGB565;
670 break;
671 }
672 return pixfmt;
673 }
674
675 static int mx3fb_blank(int blank, struct fb_info *fbi);
676 static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
677 bool lock);
678 static int mx3fb_unmap_video_memory(struct fb_info *fbi);
679
680 /**
681 * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
682 * @info: framebuffer information pointer
683 * @return: 0 on success or negative error code on failure.
684 */
685 static int mx3fb_set_fix(struct fb_info *fbi)
686 {
687 struct fb_fix_screeninfo *fix = &fbi->fix;
688 struct fb_var_screeninfo *var = &fbi->var;
689
690 strncpy(fix->id, "DISP3 BG", 8);
691
692 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
693
694 fix->type = FB_TYPE_PACKED_PIXELS;
695 fix->accel = FB_ACCEL_NONE;
696 fix->visual = FB_VISUAL_TRUECOLOR;
697 fix->xpanstep = 1;
698 fix->ypanstep = 1;
699
700 return 0;
701 }
702
703 static void mx3fb_dma_done(void *arg)
704 {
705 struct idmac_tx_desc *tx_desc = to_tx_desc(arg);
706 struct dma_chan *chan = tx_desc->txd.chan;
707 struct idmac_channel *ichannel = to_idmac_chan(chan);
708 struct mx3fb_data *mx3fb = ichannel->client;
709 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
710
711 dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
712
713 /* We only need one interrupt, it will be re-enabled as needed */
714 disable_irq_nosync(ichannel->eof_irq);
715
716 complete(&mx3_fbi->flip_cmpl);
717 }
718
719 static int __set_par(struct fb_info *fbi, bool lock)
720 {
721 u32 mem_len;
722 struct ipu_di_signal_cfg sig_cfg;
723 enum ipu_panel mode = IPU_PANEL_TFT;
724 struct mx3fb_info *mx3_fbi = fbi->par;
725 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
726 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
727 struct idmac_video_param *video = &ichan->params.video;
728 struct scatterlist *sg = mx3_fbi->sg;
729
730 /* Total cleanup */
731 if (mx3_fbi->txd)
732 sdc_disable_channel(mx3_fbi);
733
734 mx3fb_set_fix(fbi);
735
736 mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
737 if (mem_len > fbi->fix.smem_len) {
738 if (fbi->fix.smem_start)
739 mx3fb_unmap_video_memory(fbi);
740
741 if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
742 return -ENOMEM;
743 }
744
745 sg_init_table(&sg[0], 1);
746 sg_init_table(&sg[1], 1);
747
748 sg_dma_address(&sg[0]) = fbi->fix.smem_start;
749 sg_set_page(&sg[0], virt_to_page(fbi->screen_base),
750 fbi->fix.smem_len,
751 offset_in_page(fbi->screen_base));
752
753 if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
754 memset(&sig_cfg, 0, sizeof(sig_cfg));
755 if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
756 sig_cfg.Hsync_pol = true;
757 if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
758 sig_cfg.Vsync_pol = true;
759 if (fbi->var.sync & FB_SYNC_CLK_INVERT)
760 sig_cfg.clk_pol = true;
761 if (fbi->var.sync & FB_SYNC_DATA_INVERT)
762 sig_cfg.data_pol = true;
763 if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH)
764 sig_cfg.enable_pol = true;
765 if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
766 sig_cfg.clkidle_en = true;
767 if (fbi->var.sync & FB_SYNC_CLK_SEL_EN)
768 sig_cfg.clksel_en = true;
769 if (fbi->var.sync & FB_SYNC_SHARP_MODE)
770 mode = IPU_PANEL_SHARP_TFT;
771
772 dev_dbg(fbi->device, "pixclock = %ul Hz\n",
773 (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
774
775 if (sdc_init_panel(mx3fb, mode,
776 (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
777 fbi->var.xres, fbi->var.yres,
778 (fbi->var.sync & FB_SYNC_SWAP_RGB) ?
779 IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666,
780 fbi->var.left_margin,
781 fbi->var.hsync_len,
782 fbi->var.right_margin +
783 fbi->var.hsync_len,
784 fbi->var.upper_margin,
785 fbi->var.vsync_len,
786 fbi->var.lower_margin +
787 fbi->var.vsync_len, sig_cfg) != 0) {
788 dev_err(fbi->device,
789 "mx3fb: Error initializing panel.\n");
790 return -EINVAL;
791 }
792 }
793
794 sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
795
796 mx3_fbi->cur_ipu_buf = 0;
797
798 video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel);
799 video->out_width = fbi->var.xres;
800 video->out_height = fbi->var.yres;
801 video->out_stride = fbi->var.xres_virtual;
802
803 if (mx3_fbi->blank == FB_BLANK_UNBLANK)
804 sdc_enable_channel(mx3_fbi);
805
806 return 0;
807 }
808
809 /**
810 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
811 * @fbi: framebuffer information pointer.
812 * @return: 0 on success or negative error code on failure.
813 */
814 static int mx3fb_set_par(struct fb_info *fbi)
815 {
816 struct mx3fb_info *mx3_fbi = fbi->par;
817 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
818 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
819 int ret;
820
821 dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
822
823 mutex_lock(&mx3_fbi->mutex);
824
825 ret = __set_par(fbi, true);
826
827 mutex_unlock(&mx3_fbi->mutex);
828
829 return ret;
830 }
831
832 /**
833 * mx3fb_check_var() - check and adjust framebuffer variable parameters.
834 * @var: framebuffer variable parameters
835 * @fbi: framebuffer information pointer
836 */
837 static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
838 {
839 struct mx3fb_info *mx3_fbi = fbi->par;
840 u32 vtotal;
841 u32 htotal;
842
843 dev_dbg(fbi->device, "%s\n", __func__);
844
845 if (var->xres_virtual < var->xres)
846 var->xres_virtual = var->xres;
847 if (var->yres_virtual < var->yres)
848 var->yres_virtual = var->yres;
849
850 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
851 (var->bits_per_pixel != 16))
852 var->bits_per_pixel = default_bpp;
853
854 switch (var->bits_per_pixel) {
855 case 16:
856 var->red.length = 5;
857 var->red.offset = 11;
858 var->red.msb_right = 0;
859
860 var->green.length = 6;
861 var->green.offset = 5;
862 var->green.msb_right = 0;
863
864 var->blue.length = 5;
865 var->blue.offset = 0;
866 var->blue.msb_right = 0;
867
868 var->transp.length = 0;
869 var->transp.offset = 0;
870 var->transp.msb_right = 0;
871 break;
872 case 24:
873 var->red.length = 8;
874 var->red.offset = 16;
875 var->red.msb_right = 0;
876
877 var->green.length = 8;
878 var->green.offset = 8;
879 var->green.msb_right = 0;
880
881 var->blue.length = 8;
882 var->blue.offset = 0;
883 var->blue.msb_right = 0;
884
885 var->transp.length = 0;
886 var->transp.offset = 0;
887 var->transp.msb_right = 0;
888 break;
889 case 32:
890 var->red.length = 8;
891 var->red.offset = 16;
892 var->red.msb_right = 0;
893
894 var->green.length = 8;
895 var->green.offset = 8;
896 var->green.msb_right = 0;
897
898 var->blue.length = 8;
899 var->blue.offset = 0;
900 var->blue.msb_right = 0;
901
902 var->transp.length = 8;
903 var->transp.offset = 24;
904 var->transp.msb_right = 0;
905 break;
906 }
907
908 if (var->pixclock < 1000) {
909 htotal = var->xres + var->right_margin + var->hsync_len +
910 var->left_margin;
911 vtotal = var->yres + var->lower_margin + var->vsync_len +
912 var->upper_margin;
913 var->pixclock = (vtotal * htotal * 6UL) / 100UL;
914 var->pixclock = KHZ2PICOS(var->pixclock);
915 dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n",
916 var->pixclock);
917 }
918
919 var->height = -1;
920 var->width = -1;
921 var->grayscale = 0;
922
923 /* Preserve sync flags */
924 var->sync |= mx3_fbi->sync;
925 mx3_fbi->sync |= var->sync;
926
927 return 0;
928 }
929
930 static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf)
931 {
932 chan &= 0xffff;
933 chan >>= 16 - bf->length;
934 return chan << bf->offset;
935 }
936
937 static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
938 unsigned int green, unsigned int blue,
939 unsigned int trans, struct fb_info *fbi)
940 {
941 struct mx3fb_info *mx3_fbi = fbi->par;
942 u32 val;
943 int ret = 1;
944
945 dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno);
946
947 mutex_lock(&mx3_fbi->mutex);
948 /*
949 * If greyscale is true, then we convert the RGB value
950 * to greyscale no matter what visual we are using.
951 */
952 if (fbi->var.grayscale)
953 red = green = blue = (19595 * red + 38470 * green +
954 7471 * blue) >> 16;
955 switch (fbi->fix.visual) {
956 case FB_VISUAL_TRUECOLOR:
957 /*
958 * 16-bit True Colour. We encode the RGB value
959 * according to the RGB bitfield information.
960 */
961 if (regno < 16) {
962 u32 *pal = fbi->pseudo_palette;
963
964 val = chan_to_field(red, &fbi->var.red);
965 val |= chan_to_field(green, &fbi->var.green);
966 val |= chan_to_field(blue, &fbi->var.blue);
967
968 pal[regno] = val;
969
970 ret = 0;
971 }
972 break;
973
974 case FB_VISUAL_STATIC_PSEUDOCOLOR:
975 case FB_VISUAL_PSEUDOCOLOR:
976 break;
977 }
978 mutex_unlock(&mx3_fbi->mutex);
979
980 return ret;
981 }
982
983 static void __blank(int blank, struct fb_info *fbi)
984 {
985 struct mx3fb_info *mx3_fbi = fbi->par;
986 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
987
988 mx3_fbi->blank = blank;
989
990 switch (blank) {
991 case FB_BLANK_POWERDOWN:
992 case FB_BLANK_VSYNC_SUSPEND:
993 case FB_BLANK_HSYNC_SUSPEND:
994 case FB_BLANK_NORMAL:
995 sdc_set_brightness(mx3fb, 0);
996 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
997 /* Give LCD time to update - enough for 50 and 60 Hz */
998 msleep(25);
999 sdc_disable_channel(mx3_fbi);
1000 break;
1001 case FB_BLANK_UNBLANK:
1002 sdc_enable_channel(mx3_fbi);
1003 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1004 break;
1005 }
1006 }
1007
1008 /**
1009 * mx3fb_blank() - blank the display.
1010 */
1011 static int mx3fb_blank(int blank, struct fb_info *fbi)
1012 {
1013 struct mx3fb_info *mx3_fbi = fbi->par;
1014
1015 dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
1016 blank, fbi->screen_base, fbi->fix.smem_len);
1017
1018 if (mx3_fbi->blank == blank)
1019 return 0;
1020
1021 mutex_lock(&mx3_fbi->mutex);
1022 __blank(blank, fbi);
1023 mutex_unlock(&mx3_fbi->mutex);
1024
1025 return 0;
1026 }
1027
1028 /**
1029 * mx3fb_pan_display() - pan or wrap the display
1030 * @var: variable screen buffer information.
1031 * @info: framebuffer information pointer.
1032 *
1033 * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1034 */
1035 static int mx3fb_pan_display(struct fb_var_screeninfo *var,
1036 struct fb_info *fbi)
1037 {
1038 struct mx3fb_info *mx3_fbi = fbi->par;
1039 u32 y_bottom;
1040 unsigned long base;
1041 off_t offset;
1042 dma_cookie_t cookie;
1043 struct scatterlist *sg = mx3_fbi->sg;
1044 struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan;
1045 struct dma_async_tx_descriptor *txd;
1046 int ret;
1047
1048 dev_dbg(fbi->device, "%s [%c]\n", __func__,
1049 list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+');
1050
1051 if (var->xoffset > 0) {
1052 dev_dbg(fbi->device, "x panning not supported\n");
1053 return -EINVAL;
1054 }
1055
1056 if (fbi->var.xoffset == var->xoffset &&
1057 fbi->var.yoffset == var->yoffset)
1058 return 0; /* No change, do nothing */
1059
1060 y_bottom = var->yoffset;
1061
1062 if (!(var->vmode & FB_VMODE_YWRAP))
1063 y_bottom += var->yres;
1064
1065 if (y_bottom > fbi->var.yres_virtual)
1066 return -EINVAL;
1067
1068 mutex_lock(&mx3_fbi->mutex);
1069
1070 offset = (var->yoffset * var->xres_virtual + var->xoffset) *
1071 (var->bits_per_pixel / 8);
1072 base = fbi->fix.smem_start + offset;
1073
1074 dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n",
1075 mx3_fbi->cur_ipu_buf, base);
1076
1077 /*
1078 * We enable the End of Frame interrupt, which will free a tx-descriptor,
1079 * which we will need for the next device_prep_slave_sg(). The
1080 * IRQ-handler will disable the IRQ again.
1081 */
1082 init_completion(&mx3_fbi->flip_cmpl);
1083 enable_irq(mx3_fbi->idmac_channel->eof_irq);
1084
1085 ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10);
1086 if (ret <= 0) {
1087 mutex_unlock(&mx3_fbi->mutex);
1088 dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ?
1089 "user interrupt" : "timeout");
1090 disable_irq(mx3_fbi->idmac_channel->eof_irq);
1091 return ret ? : -ETIMEDOUT;
1092 }
1093
1094 mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf;
1095
1096 sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base;
1097 sg_set_page(&sg[mx3_fbi->cur_ipu_buf],
1098 virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len,
1099 offset_in_page(fbi->screen_base + offset));
1100
1101 if (mx3_fbi->txd)
1102 async_tx_ack(mx3_fbi->txd);
1103
1104 txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg +
1105 mx3_fbi->cur_ipu_buf, 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT);
1106 if (!txd) {
1107 dev_err(fbi->device,
1108 "Error preparing a DMA transaction descriptor.\n");
1109 mutex_unlock(&mx3_fbi->mutex);
1110 return -EIO;
1111 }
1112
1113 txd->callback_param = txd;
1114 txd->callback = mx3fb_dma_done;
1115
1116 /*
1117 * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1118 * should switch to another buffer
1119 */
1120 cookie = txd->tx_submit(txd);
1121 dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie);
1122 if (cookie < 0) {
1123 dev_err(fbi->device,
1124 "Error updating SDC buf %d to address=0x%08lX\n",
1125 mx3_fbi->cur_ipu_buf, base);
1126 mutex_unlock(&mx3_fbi->mutex);
1127 return -EIO;
1128 }
1129
1130 mx3_fbi->txd = txd;
1131
1132 fbi->var.xoffset = var->xoffset;
1133 fbi->var.yoffset = var->yoffset;
1134
1135 if (var->vmode & FB_VMODE_YWRAP)
1136 fbi->var.vmode |= FB_VMODE_YWRAP;
1137 else
1138 fbi->var.vmode &= ~FB_VMODE_YWRAP;
1139
1140 mutex_unlock(&mx3_fbi->mutex);
1141
1142 dev_dbg(fbi->device, "Update complete\n");
1143
1144 return 0;
1145 }
1146
1147 /*
1148 * This structure contains the pointers to the control functions that are
1149 * invoked by the core framebuffer driver to perform operations like
1150 * blitting, rectangle filling, copy regions and cursor definition.
1151 */
1152 static struct fb_ops mx3fb_ops = {
1153 .owner = THIS_MODULE,
1154 .fb_set_par = mx3fb_set_par,
1155 .fb_check_var = mx3fb_check_var,
1156 .fb_setcolreg = mx3fb_setcolreg,
1157 .fb_pan_display = mx3fb_pan_display,
1158 .fb_fillrect = cfb_fillrect,
1159 .fb_copyarea = cfb_copyarea,
1160 .fb_imageblit = cfb_imageblit,
1161 .fb_blank = mx3fb_blank,
1162 };
1163
1164 #ifdef CONFIG_PM
1165 /*
1166 * Power management hooks. Note that we won't be called from IRQ context,
1167 * unlike the blank functions above, so we may sleep.
1168 */
1169
1170 /*
1171 * Suspends the framebuffer and blanks the screen. Power management support
1172 */
1173 static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state)
1174 {
1175 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1176 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1177
1178 acquire_console_sem();
1179 fb_set_suspend(mx3fb->fbi, 1);
1180 release_console_sem();
1181
1182 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1183 sdc_disable_channel(mx3_fbi);
1184 sdc_set_brightness(mx3fb, 0);
1185
1186 }
1187 return 0;
1188 }
1189
1190 /*
1191 * Resumes the framebuffer and unblanks the screen. Power management support
1192 */
1193 static int mx3fb_resume(struct platform_device *pdev)
1194 {
1195 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1196 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1197
1198 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1199 sdc_enable_channel(mx3_fbi);
1200 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1201 }
1202
1203 acquire_console_sem();
1204 fb_set_suspend(mx3fb->fbi, 0);
1205 release_console_sem();
1206
1207 return 0;
1208 }
1209 #else
1210 #define mx3fb_suspend NULL
1211 #define mx3fb_resume NULL
1212 #endif
1213
1214 /*
1215 * Main framebuffer functions
1216 */
1217
1218 /**
1219 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
1220 * @fbi: framebuffer information pointer
1221 * @mem_len: length of mapped memory
1222 * @lock: do not lock during initialisation
1223 * @return: Error code indicating success or failure
1224 *
1225 * This buffer is remapped into a non-cached, non-buffered, memory region to
1226 * allow palette and pixel writes to occur without flushing the cache. Once this
1227 * area is remapped, all virtual memory access to the video memory should occur
1228 * at the new region.
1229 */
1230 static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
1231 bool lock)
1232 {
1233 int retval = 0;
1234 dma_addr_t addr;
1235
1236 fbi->screen_base = dma_alloc_writecombine(fbi->device,
1237 mem_len,
1238 &addr, GFP_DMA);
1239
1240 if (!fbi->screen_base) {
1241 dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n",
1242 mem_len);
1243 retval = -EBUSY;
1244 goto err0;
1245 }
1246
1247 if (lock)
1248 mutex_lock(&fbi->mm_lock);
1249 fbi->fix.smem_start = addr;
1250 fbi->fix.smem_len = mem_len;
1251 if (lock)
1252 mutex_unlock(&fbi->mm_lock);
1253
1254 dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1255 (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
1256
1257 fbi->screen_size = fbi->fix.smem_len;
1258
1259 /* Clear the screen */
1260 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
1261
1262 return 0;
1263
1264 err0:
1265 fbi->fix.smem_len = 0;
1266 fbi->fix.smem_start = 0;
1267 fbi->screen_base = NULL;
1268 return retval;
1269 }
1270
1271 /**
1272 * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
1273 * @fbi: framebuffer information pointer
1274 * @return: error code indicating success or failure
1275 */
1276 static int mx3fb_unmap_video_memory(struct fb_info *fbi)
1277 {
1278 dma_free_writecombine(fbi->device, fbi->fix.smem_len,
1279 fbi->screen_base, fbi->fix.smem_start);
1280
1281 fbi->screen_base = 0;
1282 mutex_lock(&fbi->mm_lock);
1283 fbi->fix.smem_start = 0;
1284 fbi->fix.smem_len = 0;
1285 mutex_unlock(&fbi->mm_lock);
1286 return 0;
1287 }
1288
1289 /**
1290 * mx3fb_init_fbinfo() - initialize framebuffer information object.
1291 * @return: initialized framebuffer structure.
1292 */
1293 static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops)
1294 {
1295 struct fb_info *fbi;
1296 struct mx3fb_info *mx3fbi;
1297 int ret;
1298
1299 /* Allocate sufficient memory for the fb structure */
1300 fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev);
1301 if (!fbi)
1302 return NULL;
1303
1304 mx3fbi = fbi->par;
1305 mx3fbi->cookie = -EINVAL;
1306 mx3fbi->cur_ipu_buf = 0;
1307
1308 fbi->var.activate = FB_ACTIVATE_NOW;
1309
1310 fbi->fbops = ops;
1311 fbi->flags = FBINFO_FLAG_DEFAULT;
1312 fbi->pseudo_palette = mx3fbi->pseudo_palette;
1313
1314 mutex_init(&mx3fbi->mutex);
1315
1316 /* Allocate colormap */
1317 ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
1318 if (ret < 0) {
1319 framebuffer_release(fbi);
1320 return NULL;
1321 }
1322
1323 return fbi;
1324 }
1325
1326 static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1327 {
1328 struct device *dev = mx3fb->dev;
1329 struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data;
1330 const char *name = mx3fb_pdata->name;
1331 unsigned int irq;
1332 struct fb_info *fbi;
1333 struct mx3fb_info *mx3fbi;
1334 const struct fb_videomode *mode;
1335 int ret, num_modes;
1336
1337 ichan->client = mx3fb;
1338 irq = ichan->eof_irq;
1339
1340 if (ichan->dma_chan.chan_id != IDMAC_SDC_0)
1341 return -EINVAL;
1342
1343 fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops);
1344 if (!fbi)
1345 return -ENOMEM;
1346
1347 if (!fb_mode)
1348 fb_mode = name;
1349
1350 if (!fb_mode) {
1351 ret = -EINVAL;
1352 goto emode;
1353 }
1354
1355 if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) {
1356 mode = mx3fb_pdata->mode;
1357 num_modes = mx3fb_pdata->num_modes;
1358 } else {
1359 mode = mx3fb_modedb;
1360 num_modes = ARRAY_SIZE(mx3fb_modedb);
1361 }
1362
1363 if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode,
1364 num_modes, NULL, default_bpp)) {
1365 ret = -EBUSY;
1366 goto emode;
1367 }
1368
1369 fb_videomode_to_modelist(mode, num_modes, &fbi->modelist);
1370
1371 /* Default Y virtual size is 2x panel size */
1372 fbi->var.yres_virtual = fbi->var.yres * 2;
1373
1374 mx3fb->fbi = fbi;
1375
1376 /* set Display Interface clock period */
1377 mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
1378 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
1379
1380 sdc_set_brightness(mx3fb, 255);
1381 sdc_set_global_alpha(mx3fb, true, 0xFF);
1382 sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
1383
1384 mx3fbi = fbi->par;
1385 mx3fbi->idmac_channel = ichan;
1386 mx3fbi->ipu_ch = ichan->dma_chan.chan_id;
1387 mx3fbi->mx3fb = mx3fb;
1388 mx3fbi->blank = FB_BLANK_NORMAL;
1389
1390 init_completion(&mx3fbi->flip_cmpl);
1391 disable_irq(ichan->eof_irq);
1392 dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
1393 ret = __set_par(fbi, false);
1394 if (ret < 0)
1395 goto esetpar;
1396
1397 __blank(FB_BLANK_UNBLANK, fbi);
1398
1399 dev_info(dev, "registered, using mode %s\n", fb_mode);
1400
1401 ret = register_framebuffer(fbi);
1402 if (ret < 0)
1403 goto erfb;
1404
1405 return 0;
1406
1407 erfb:
1408 esetpar:
1409 emode:
1410 fb_dealloc_cmap(&fbi->cmap);
1411 framebuffer_release(fbi);
1412
1413 return ret;
1414 }
1415
1416 static bool chan_filter(struct dma_chan *chan, void *arg)
1417 {
1418 struct dma_chan_request *rq = arg;
1419 struct device *dev;
1420 struct mx3fb_platform_data *mx3fb_pdata;
1421
1422 if (!rq)
1423 return false;
1424
1425 dev = rq->mx3fb->dev;
1426 mx3fb_pdata = dev->platform_data;
1427
1428 return rq->id == chan->chan_id &&
1429 mx3fb_pdata->dma_dev == chan->device->dev;
1430 }
1431
1432 static void release_fbi(struct fb_info *fbi)
1433 {
1434 mx3fb_unmap_video_memory(fbi);
1435
1436 fb_dealloc_cmap(&fbi->cmap);
1437
1438 unregister_framebuffer(fbi);
1439 framebuffer_release(fbi);
1440 }
1441
1442 static int mx3fb_probe(struct platform_device *pdev)
1443 {
1444 struct device *dev = &pdev->dev;
1445 int ret;
1446 struct resource *sdc_reg;
1447 struct mx3fb_data *mx3fb;
1448 dma_cap_mask_t mask;
1449 struct dma_chan *chan;
1450 struct dma_chan_request rq;
1451
1452 /*
1453 * Display Interface (DI) and Synchronous Display Controller (SDC)
1454 * registers
1455 */
1456 sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1457 if (!sdc_reg)
1458 return -EINVAL;
1459
1460 mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL);
1461 if (!mx3fb)
1462 return -ENOMEM;
1463
1464 spin_lock_init(&mx3fb->lock);
1465
1466 mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1467 if (!mx3fb->reg_base) {
1468 ret = -ENOMEM;
1469 goto eremap;
1470 }
1471
1472 pr_debug("Remapped %x to %x at %p\n", sdc_reg->start, sdc_reg->end,
1473 mx3fb->reg_base);
1474
1475 /* IDMAC interface */
1476 dmaengine_get();
1477
1478 mx3fb->dev = dev;
1479 platform_set_drvdata(pdev, mx3fb);
1480
1481 rq.mx3fb = mx3fb;
1482
1483 dma_cap_zero(mask);
1484 dma_cap_set(DMA_SLAVE, mask);
1485 dma_cap_set(DMA_PRIVATE, mask);
1486 rq.id = IDMAC_SDC_0;
1487 chan = dma_request_channel(mask, chan_filter, &rq);
1488 if (!chan) {
1489 ret = -EBUSY;
1490 goto ersdc0;
1491 }
1492
1493 mx3fb->backlight_level = 255;
1494
1495 ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
1496 if (ret < 0)
1497 goto eisdc0;
1498
1499 return 0;
1500
1501 eisdc0:
1502 dma_release_channel(chan);
1503 ersdc0:
1504 dmaengine_put();
1505 iounmap(mx3fb->reg_base);
1506 eremap:
1507 kfree(mx3fb);
1508 dev_err(dev, "mx3fb: failed to register fb\n");
1509 return ret;
1510 }
1511
1512 static int mx3fb_remove(struct platform_device *dev)
1513 {
1514 struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
1515 struct fb_info *fbi = mx3fb->fbi;
1516 struct mx3fb_info *mx3_fbi = fbi->par;
1517 struct dma_chan *chan;
1518
1519 chan = &mx3_fbi->idmac_channel->dma_chan;
1520 release_fbi(fbi);
1521
1522 dma_release_channel(chan);
1523 dmaengine_put();
1524
1525 iounmap(mx3fb->reg_base);
1526 kfree(mx3fb);
1527 return 0;
1528 }
1529
1530 static struct platform_driver mx3fb_driver = {
1531 .driver = {
1532 .name = MX3FB_NAME,
1533 },
1534 .probe = mx3fb_probe,
1535 .remove = mx3fb_remove,
1536 .suspend = mx3fb_suspend,
1537 .resume = mx3fb_resume,
1538 };
1539
1540 /*
1541 * Parse user specified options (`video=mx3fb:')
1542 * example:
1543 * video=mx3fb:bpp=16
1544 */
1545 static int __init mx3fb_setup(void)
1546 {
1547 #ifndef MODULE
1548 char *opt, *options = NULL;
1549
1550 if (fb_get_options("mx3fb", &options))
1551 return -ENODEV;
1552
1553 if (!options || !*options)
1554 return 0;
1555
1556 while ((opt = strsep(&options, ",")) != NULL) {
1557 if (!*opt)
1558 continue;
1559 if (!strncmp(opt, "bpp=", 4))
1560 default_bpp = simple_strtoul(opt + 4, NULL, 0);
1561 else
1562 fb_mode = opt;
1563 }
1564 #endif
1565
1566 return 0;
1567 }
1568
1569 static int __init mx3fb_init(void)
1570 {
1571 int ret = mx3fb_setup();
1572
1573 if (ret < 0)
1574 return ret;
1575
1576 ret = platform_driver_register(&mx3fb_driver);
1577 return ret;
1578 }
1579
1580 static void __exit mx3fb_exit(void)
1581 {
1582 platform_driver_unregister(&mx3fb_driver);
1583 }
1584
1585 module_init(mx3fb_init);
1586 module_exit(mx3fb_exit);
1587
1588 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1589 MODULE_DESCRIPTION("MX3 framebuffer driver");
1590 MODULE_ALIAS("platform:" MX3FB_NAME);
1591 MODULE_LICENSE("GPL v2");