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Linux 2.6.34-rc3
[pohmelfs.git] / drivers / video / omap / dispc.c
blobe192b058a6888002ddecbcfed4413ec85269da58
1 /*
2 * OMAP2 display controller support
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Author: Imre Deak <imre.deak@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21 #include <linux/kernel.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mm.h>
24 #include <linux/vmalloc.h>
25 #include <linux/clk.h>
26 #include <linux/io.h>
27 #include <linux/platform_device.h>
28
29 #include <plat/sram.h>
30 #include <plat/board.h>
31
32 #include "omapfb.h"
33 #include "dispc.h"
34
35 #define MODULE_NAME "dispc"
36
37 #define DSS_BASE 0x48050000
38 #define DSS_SYSCONFIG 0x0010
39
40 #define DISPC_BASE 0x48050400
41
42 /* DISPC common */
43 #define DISPC_REVISION 0x0000
44 #define DISPC_SYSCONFIG 0x0010
45 #define DISPC_SYSSTATUS 0x0014
46 #define DISPC_IRQSTATUS 0x0018
47 #define DISPC_IRQENABLE 0x001C
48 #define DISPC_CONTROL 0x0040
49 #define DISPC_CONFIG 0x0044
50 #define DISPC_CAPABLE 0x0048
51 #define DISPC_DEFAULT_COLOR0 0x004C
52 #define DISPC_DEFAULT_COLOR1 0x0050
53 #define DISPC_TRANS_COLOR0 0x0054
54 #define DISPC_TRANS_COLOR1 0x0058
55 #define DISPC_LINE_STATUS 0x005C
56 #define DISPC_LINE_NUMBER 0x0060
57 #define DISPC_TIMING_H 0x0064
58 #define DISPC_TIMING_V 0x0068
59 #define DISPC_POL_FREQ 0x006C
60 #define DISPC_DIVISOR 0x0070
61 #define DISPC_SIZE_DIG 0x0078
62 #define DISPC_SIZE_LCD 0x007C
63
64 #define DISPC_DATA_CYCLE1 0x01D4
65 #define DISPC_DATA_CYCLE2 0x01D8
66 #define DISPC_DATA_CYCLE3 0x01DC
67
68 /* DISPC GFX plane */
69 #define DISPC_GFX_BA0 0x0080
70 #define DISPC_GFX_BA1 0x0084
71 #define DISPC_GFX_POSITION 0x0088
72 #define DISPC_GFX_SIZE 0x008C
73 #define DISPC_GFX_ATTRIBUTES 0x00A0
74 #define DISPC_GFX_FIFO_THRESHOLD 0x00A4
75 #define DISPC_GFX_FIFO_SIZE_STATUS 0x00A8
76 #define DISPC_GFX_ROW_INC 0x00AC
77 #define DISPC_GFX_PIXEL_INC 0x00B0
78 #define DISPC_GFX_WINDOW_SKIP 0x00B4
79 #define DISPC_GFX_TABLE_BA 0x00B8
80
81 /* DISPC Video plane 1/2 */
82 #define DISPC_VID1_BASE 0x00BC
83 #define DISPC_VID2_BASE 0x014C
84
85 /* Offsets into DISPC_VID1/2_BASE */
86 #define DISPC_VID_BA0 0x0000
87 #define DISPC_VID_BA1 0x0004
88 #define DISPC_VID_POSITION 0x0008
89 #define DISPC_VID_SIZE 0x000C
90 #define DISPC_VID_ATTRIBUTES 0x0010
91 #define DISPC_VID_FIFO_THRESHOLD 0x0014
92 #define DISPC_VID_FIFO_SIZE_STATUS 0x0018
93 #define DISPC_VID_ROW_INC 0x001C
94 #define DISPC_VID_PIXEL_INC 0x0020
95 #define DISPC_VID_FIR 0x0024
96 #define DISPC_VID_PICTURE_SIZE 0x0028
97 #define DISPC_VID_ACCU0 0x002C
98 #define DISPC_VID_ACCU1 0x0030
99
100 /* 8 elements in 8 byte increments */
101 #define DISPC_VID_FIR_COEF_H0 0x0034
102 /* 8 elements in 8 byte increments */
103 #define DISPC_VID_FIR_COEF_HV0 0x0038
104 /* 5 elements in 4 byte increments */
105 #define DISPC_VID_CONV_COEF0 0x0074
106
107 #define DISPC_IRQ_FRAMEMASK 0x0001
108 #define DISPC_IRQ_VSYNC 0x0002
109 #define DISPC_IRQ_EVSYNC_EVEN 0x0004
110 #define DISPC_IRQ_EVSYNC_ODD 0x0008
111 #define DISPC_IRQ_ACBIAS_COUNT_STAT 0x0010
112 #define DISPC_IRQ_PROG_LINE_NUM 0x0020
113 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW 0x0040
114 #define DISPC_IRQ_GFX_END_WIN 0x0080
115 #define DISPC_IRQ_PAL_GAMMA_MASK 0x0100
116 #define DISPC_IRQ_OCP_ERR 0x0200
117 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW 0x0400
118 #define DISPC_IRQ_VID1_END_WIN 0x0800
119 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW 0x1000
120 #define DISPC_IRQ_VID2_END_WIN 0x2000
121 #define DISPC_IRQ_SYNC_LOST 0x4000
122
123 #define DISPC_IRQ_MASK_ALL 0x7fff
124
125 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
126 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
127 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
128 DISPC_IRQ_SYNC_LOST)
129
130 #define RFBI_CONTROL 0x48050040
131
132 #define MAX_PALETTE_SIZE (256 * 16)
133
134 #define FLD_MASK(pos, len) (((1 << len) - 1) << pos)
135
136 #define MOD_REG_FLD(reg, mask, val) \
137 dispc_write_reg((reg), (dispc_read_reg(reg) & ~(mask)) | (val));
138
139 #define OMAP2_SRAM_START 0x40200000
140 /* Maximum size, in reality this is smaller if SRAM is partially locked. */
141 #define OMAP2_SRAM_SIZE 0xa0000 /* 640k */
142
143 /* We support the SDRAM / SRAM types. See OMAPFB_PLANE_MEMTYPE_* in omapfb.h */
144 #define DISPC_MEMTYPE_NUM 2
145
146 #define RESMAP_SIZE(_page_cnt) \
147 ((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
148 #define RESMAP_PTR(_res_map, _page_nr) \
149 (((_res_map)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
150 #define RESMAP_MASK(_page_nr) \
151 (1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
152
153 struct resmap {
154 unsigned long start;
155 unsigned page_cnt;
156 unsigned long *map;
157 };
158
159 #define MAX_IRQ_HANDLERS 4
160
161 static struct {
162 void __iomem *base;
163
164 struct omapfb_mem_desc mem_desc;
165 struct resmap *res_map[DISPC_MEMTYPE_NUM];
166 atomic_t map_count[OMAPFB_PLANE_NUM];
167
168 dma_addr_t palette_paddr;
169 void *palette_vaddr;
170
171 int ext_mode;
172
173 struct {
174 u32 irq_mask;
175 void (*callback)(void *);
176 void *data;
177 } irq_handlers[MAX_IRQ_HANDLERS];
178 struct completion frame_done;
179
180 int fir_hinc[OMAPFB_PLANE_NUM];
181 int fir_vinc[OMAPFB_PLANE_NUM];
182
183 struct clk *dss_ick, *dss1_fck;
184 struct clk *dss_54m_fck;
185
186 enum omapfb_update_mode update_mode;
187 struct omapfb_device *fbdev;
188
189 struct omapfb_color_key color_key;
190 } dispc;
191
192 static void enable_lcd_clocks(int enable);
193
194 static void inline dispc_write_reg(int idx, u32 val)
195 {
196 __raw_writel(val, dispc.base + idx);
197 }
198
199 static u32 inline dispc_read_reg(int idx)
200 {
201 u32 l = __raw_readl(dispc.base + idx);
202 return l;
203 }
204
205 /* Select RFBI or bypass mode */
206 static void enable_rfbi_mode(int enable)
207 {
208 void __iomem *rfbi_control;
209 u32 l;
210
211 l = dispc_read_reg(DISPC_CONTROL);
212 /* Enable RFBI, GPIO0/1 */
213 l &= ~((1 << 11) | (1 << 15) | (1 << 16));
214 l |= enable ? (1 << 11) : 0;
215 /* RFBI En: GPIO0/1=10 RFBI Dis: GPIO0/1=11 */
216 l |= 1 << 15;
217 l |= enable ? 0 : (1 << 16);
218 dispc_write_reg(DISPC_CONTROL, l);
219
220 /* Set bypass mode in RFBI module */
221 rfbi_control = ioremap(RFBI_CONTROL, SZ_1K);
222 if (!rfbi_control) {
223 pr_err("Unable to ioremap rfbi_control\n");
224 return;
225 }
226 l = __raw_readl(rfbi_control);
227 l |= enable ? 0 : (1 << 1);
228 __raw_writel(l, rfbi_control);
229 iounmap(rfbi_control);
230 }
231
232 static void set_lcd_data_lines(int data_lines)
233 {
234 u32 l;
235 int code = 0;
236
237 switch (data_lines) {
238 case 12:
239 code = 0;
240 break;
241 case 16:
242 code = 1;
243 break;
244 case 18:
245 code = 2;
246 break;
247 case 24:
248 code = 3;
249 break;
250 default:
251 BUG();
252 }
253
254 l = dispc_read_reg(DISPC_CONTROL);
255 l &= ~(0x03 << 8);
256 l |= code << 8;
257 dispc_write_reg(DISPC_CONTROL, l);
258 }
259
260 static void set_load_mode(int mode)
261 {
262 BUG_ON(mode & ~(DISPC_LOAD_CLUT_ONLY | DISPC_LOAD_FRAME_ONLY |
263 DISPC_LOAD_CLUT_ONCE_FRAME));
264 MOD_REG_FLD(DISPC_CONFIG, 0x03 << 1, mode << 1);
265 }
266
267 void omap_dispc_set_lcd_size(int x, int y)
268 {
269 BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
270 enable_lcd_clocks(1);
271 MOD_REG_FLD(DISPC_SIZE_LCD, FLD_MASK(16, 11) | FLD_MASK(0, 11),
272 ((y - 1) << 16) | (x - 1));
273 enable_lcd_clocks(0);
274 }
275 EXPORT_SYMBOL(omap_dispc_set_lcd_size);
276
277 void omap_dispc_set_digit_size(int x, int y)
278 {
279 BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
280 enable_lcd_clocks(1);
281 MOD_REG_FLD(DISPC_SIZE_DIG, FLD_MASK(16, 11) | FLD_MASK(0, 11),
282 ((y - 1) << 16) | (x - 1));
283 enable_lcd_clocks(0);
284 }
285 EXPORT_SYMBOL(omap_dispc_set_digit_size);
286
287 static void setup_plane_fifo(int plane, int ext_mode)
288 {
289 const u32 ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
290 DISPC_VID1_BASE + DISPC_VID_FIFO_THRESHOLD,
291 DISPC_VID2_BASE + DISPC_VID_FIFO_THRESHOLD };
292 const u32 fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
293 DISPC_VID1_BASE + DISPC_VID_FIFO_SIZE_STATUS,
294 DISPC_VID2_BASE + DISPC_VID_FIFO_SIZE_STATUS };
295 int low, high;
296 u32 l;
297
298 BUG_ON(plane > 2);
299
300 l = dispc_read_reg(fsz_reg[plane]);
301 l &= FLD_MASK(0, 11);
302 if (ext_mode) {
303 low = l * 3 / 4;
304 high = l;
305 } else {
306 low = l / 4;
307 high = l * 3 / 4;
308 }
309 MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 12) | FLD_MASK(0, 12),
310 (high << 16) | low);
311 }
312
313 void omap_dispc_enable_lcd_out(int enable)
314 {
315 enable_lcd_clocks(1);
316 MOD_REG_FLD(DISPC_CONTROL, 1, enable ? 1 : 0);
317 enable_lcd_clocks(0);
318 }
319 EXPORT_SYMBOL(omap_dispc_enable_lcd_out);
320
321 void omap_dispc_enable_digit_out(int enable)
322 {
323 enable_lcd_clocks(1);
324 MOD_REG_FLD(DISPC_CONTROL, 1 << 1, enable ? 1 << 1 : 0);
325 enable_lcd_clocks(0);
326 }
327 EXPORT_SYMBOL(omap_dispc_enable_digit_out);
328
329 static inline int _setup_plane(int plane, int channel_out,
330 u32 paddr, int screen_width,
331 int pos_x, int pos_y, int width, int height,
332 int color_mode)
333 {
334 const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
335 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
336 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
337 const u32 ba_reg[] = { DISPC_GFX_BA0, DISPC_VID1_BASE + DISPC_VID_BA0,
338 DISPC_VID2_BASE + DISPC_VID_BA0 };
339 const u32 ps_reg[] = { DISPC_GFX_POSITION,
340 DISPC_VID1_BASE + DISPC_VID_POSITION,
341 DISPC_VID2_BASE + DISPC_VID_POSITION };
342 const u32 sz_reg[] = { DISPC_GFX_SIZE,
343 DISPC_VID1_BASE + DISPC_VID_PICTURE_SIZE,
344 DISPC_VID2_BASE + DISPC_VID_PICTURE_SIZE };
345 const u32 ri_reg[] = { DISPC_GFX_ROW_INC,
346 DISPC_VID1_BASE + DISPC_VID_ROW_INC,
347 DISPC_VID2_BASE + DISPC_VID_ROW_INC };
348 const u32 vs_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
349 DISPC_VID2_BASE + DISPC_VID_SIZE };
350
351 int chout_shift, burst_shift;
352 int chout_val;
353 int color_code;
354 int bpp;
355 int cconv_en;
356 int set_vsize;
357 u32 l;
358
359 #ifdef VERBOSE
360 dev_dbg(dispc.fbdev->dev, "plane %d channel %d paddr %#08x scr_width %d"
361 " pos_x %d pos_y %d width %d height %d color_mode %d\n",
362 plane, channel_out, paddr, screen_width, pos_x, pos_y,
363 width, height, color_mode);
364 #endif
365
366 set_vsize = 0;
367 switch (plane) {
368 case OMAPFB_PLANE_GFX:
369 burst_shift = 6;
370 chout_shift = 8;
371 break;
372 case OMAPFB_PLANE_VID1:
373 case OMAPFB_PLANE_VID2:
374 burst_shift = 14;
375 chout_shift = 16;
376 set_vsize = 1;
377 break;
378 default:
379 return -EINVAL;
380 }
381
382 switch (channel_out) {
383 case OMAPFB_CHANNEL_OUT_LCD:
384 chout_val = 0;
385 break;
386 case OMAPFB_CHANNEL_OUT_DIGIT:
387 chout_val = 1;
388 break;
389 default:
390 return -EINVAL;
391 }
392
393 cconv_en = 0;
394 switch (color_mode) {
395 case OMAPFB_COLOR_RGB565:
396 color_code = DISPC_RGB_16_BPP;
397 bpp = 16;
398 break;
399 case OMAPFB_COLOR_YUV422:
400 if (plane == 0)
401 return -EINVAL;
402 color_code = DISPC_UYVY_422;
403 cconv_en = 1;
404 bpp = 16;
405 break;
406 case OMAPFB_COLOR_YUY422:
407 if (plane == 0)
408 return -EINVAL;
409 color_code = DISPC_YUV2_422;
410 cconv_en = 1;
411 bpp = 16;
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 l = dispc_read_reg(at_reg[plane]);
418
419 l &= ~(0x0f << 1);
420 l |= color_code << 1;
421 l &= ~(1 << 9);
422 l |= cconv_en << 9;
423
424 l &= ~(0x03 << burst_shift);
425 l |= DISPC_BURST_8x32 << burst_shift;
426
427 l &= ~(1 << chout_shift);
428 l |= chout_val << chout_shift;
429
430 dispc_write_reg(at_reg[plane], l);
431
432 dispc_write_reg(ba_reg[plane], paddr);
433 MOD_REG_FLD(ps_reg[plane],
434 FLD_MASK(16, 11) | FLD_MASK(0, 11), (pos_y << 16) | pos_x);
435
436 MOD_REG_FLD(sz_reg[plane], FLD_MASK(16, 11) | FLD_MASK(0, 11),
437 ((height - 1) << 16) | (width - 1));
438
439 if (set_vsize) {
440 /* Set video size if set_scale hasn't set it */
441 if (!dispc.fir_vinc[plane])
442 MOD_REG_FLD(vs_reg[plane],
443 FLD_MASK(16, 11), (height - 1) << 16);
444 if (!dispc.fir_hinc[plane])
445 MOD_REG_FLD(vs_reg[plane],
446 FLD_MASK(0, 11), width - 1);
447 }
448
449 dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1);
450
451 return height * screen_width * bpp / 8;
452 }
453
454 static int omap_dispc_setup_plane(int plane, int channel_out,
455 unsigned long offset,
456 int screen_width,
457 int pos_x, int pos_y, int width, int height,
458 int color_mode)
459 {
460 u32 paddr;
461 int r;
462
463 if ((unsigned)plane > dispc.mem_desc.region_cnt)
464 return -EINVAL;
465 paddr = dispc.mem_desc.region[plane].paddr + offset;
466 enable_lcd_clocks(1);
467 r = _setup_plane(plane, channel_out, paddr,
468 screen_width,
469 pos_x, pos_y, width, height, color_mode);
470 enable_lcd_clocks(0);
471 return r;
472 }
473
474 static void write_firh_reg(int plane, int reg, u32 value)
475 {
476 u32 base;
477
478 if (plane == 1)
479 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_H0;
480 else
481 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_H0;
482 dispc_write_reg(base + reg * 8, value);
483 }
484
485 static void write_firhv_reg(int plane, int reg, u32 value)
486 {
487 u32 base;
488
489 if (plane == 1)
490 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_HV0;
491 else
492 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_HV0;
493 dispc_write_reg(base + reg * 8, value);
494 }
495
496 static void set_upsampling_coef_table(int plane)
497 {
498 const u32 coef[][2] = {
499 { 0x00800000, 0x00800000 },
500 { 0x0D7CF800, 0x037B02FF },
501 { 0x1E70F5FF, 0x0C6F05FE },
502 { 0x335FF5FE, 0x205907FB },
503 { 0xF74949F7, 0x00404000 },
504 { 0xF55F33FB, 0x075920FE },
505 { 0xF5701EFE, 0x056F0CFF },
506 { 0xF87C0DFF, 0x027B0300 },
507 };
508 int i;
509
510 for (i = 0; i < 8; i++) {
511 write_firh_reg(plane, i, coef[i][0]);
512 write_firhv_reg(plane, i, coef[i][1]);
513 }
514 }
515
516 static int omap_dispc_set_scale(int plane,
517 int orig_width, int orig_height,
518 int out_width, int out_height)
519 {
520 const u32 at_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
521 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
522 const u32 vs_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
523 DISPC_VID2_BASE + DISPC_VID_SIZE };
524 const u32 fir_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_FIR,
525 DISPC_VID2_BASE + DISPC_VID_FIR };
526
527 u32 l;
528 int fir_hinc;
529 int fir_vinc;
530
531 if ((unsigned)plane > OMAPFB_PLANE_NUM)
532 return -ENODEV;
533
534 if (plane == OMAPFB_PLANE_GFX &&
535 (out_width != orig_width || out_height != orig_height))
536 return -EINVAL;
537
538 enable_lcd_clocks(1);
539 if (orig_width < out_width) {
540 /*
541 * Upsampling.
542 * Currently you can only scale both dimensions in one way.
543 */
544 if (orig_height > out_height ||
545 orig_width * 8 < out_width ||
546 orig_height * 8 < out_height) {
547 enable_lcd_clocks(0);
548 return -EINVAL;
549 }
550 set_upsampling_coef_table(plane);
551 } else if (orig_width > out_width) {
552 /* Downsampling not yet supported
553 */
554
555 enable_lcd_clocks(0);
556 return -EINVAL;
557 }
558 if (!orig_width || orig_width == out_width)
559 fir_hinc = 0;
560 else
561 fir_hinc = 1024 * orig_width / out_width;
562 if (!orig_height || orig_height == out_height)
563 fir_vinc = 0;
564 else
565 fir_vinc = 1024 * orig_height / out_height;
566 dispc.fir_hinc[plane] = fir_hinc;
567 dispc.fir_vinc[plane] = fir_vinc;
568
569 MOD_REG_FLD(fir_reg[plane],
570 FLD_MASK(16, 12) | FLD_MASK(0, 12),
571 ((fir_vinc & 4095) << 16) |
572 (fir_hinc & 4095));
573
574 dev_dbg(dispc.fbdev->dev, "out_width %d out_height %d orig_width %d "
575 "orig_height %d fir_hinc %d fir_vinc %d\n",
576 out_width, out_height, orig_width, orig_height,
577 fir_hinc, fir_vinc);
578
579 MOD_REG_FLD(vs_reg[plane],
580 FLD_MASK(16, 11) | FLD_MASK(0, 11),
581 ((out_height - 1) << 16) | (out_width - 1));
582
583 l = dispc_read_reg(at_reg[plane]);
584 l &= ~(0x03 << 5);
585 l |= fir_hinc ? (1 << 5) : 0;
586 l |= fir_vinc ? (1 << 6) : 0;
587 dispc_write_reg(at_reg[plane], l);
588
589 enable_lcd_clocks(0);
590 return 0;
591 }
592
593 static int omap_dispc_enable_plane(int plane, int enable)
594 {
595 const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
596 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
597 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
598 if ((unsigned int)plane > dispc.mem_desc.region_cnt)
599 return -EINVAL;
600
601 enable_lcd_clocks(1);
602 MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0);
603 enable_lcd_clocks(0);
604
605 return 0;
606 }
607
608 static int omap_dispc_set_color_key(struct omapfb_color_key *ck)
609 {
610 u32 df_reg, tr_reg;
611 int shift, val;
612
613 switch (ck->channel_out) {
614 case OMAPFB_CHANNEL_OUT_LCD:
615 df_reg = DISPC_DEFAULT_COLOR0;
616 tr_reg = DISPC_TRANS_COLOR0;
617 shift = 10;
618 break;
619 case OMAPFB_CHANNEL_OUT_DIGIT:
620 df_reg = DISPC_DEFAULT_COLOR1;
621 tr_reg = DISPC_TRANS_COLOR1;
622 shift = 12;
623 break;
624 default:
625 return -EINVAL;
626 }
627 switch (ck->key_type) {
628 case OMAPFB_COLOR_KEY_DISABLED:
629 val = 0;
630 break;
631 case OMAPFB_COLOR_KEY_GFX_DST:
632 val = 1;
633 break;
634 case OMAPFB_COLOR_KEY_VID_SRC:
635 val = 3;
636 break;
637 default:
638 return -EINVAL;
639 }
640 enable_lcd_clocks(1);
641 MOD_REG_FLD(DISPC_CONFIG, FLD_MASK(shift, 2), val << shift);
642
643 if (val != 0)
644 dispc_write_reg(tr_reg, ck->trans_key);
645 dispc_write_reg(df_reg, ck->background);
646 enable_lcd_clocks(0);
647
648 dispc.color_key = *ck;
649
650 return 0;
651 }
652
653 static int omap_dispc_get_color_key(struct omapfb_color_key *ck)
654 {
655 *ck = dispc.color_key;
656 return 0;
657 }
658
659 static void load_palette(void)
660 {
661 }
662
663 static int omap_dispc_set_update_mode(enum omapfb_update_mode mode)
664 {
665 int r = 0;
666
667 if (mode != dispc.update_mode) {
668 switch (mode) {
669 case OMAPFB_AUTO_UPDATE:
670 case OMAPFB_MANUAL_UPDATE:
671 enable_lcd_clocks(1);
672 omap_dispc_enable_lcd_out(1);
673 dispc.update_mode = mode;
674 break;
675 case OMAPFB_UPDATE_DISABLED:
676 init_completion(&dispc.frame_done);
677 omap_dispc_enable_lcd_out(0);
678 if (!wait_for_completion_timeout(&dispc.frame_done,
679 msecs_to_jiffies(500))) {
680 dev_err(dispc.fbdev->dev,
681 "timeout waiting for FRAME DONE\n");
682 }
683 dispc.update_mode = mode;
684 enable_lcd_clocks(0);
685 break;
686 default:
687 r = -EINVAL;
688 }
689 }
690
691 return r;
692 }
693
694 static void omap_dispc_get_caps(int plane, struct omapfb_caps *caps)
695 {
696 caps->ctrl |= OMAPFB_CAPS_PLANE_RELOCATE_MEM;
697 if (plane > 0)
698 caps->ctrl |= OMAPFB_CAPS_PLANE_SCALE;
699 caps->plane_color |= (1 << OMAPFB_COLOR_RGB565) |
700 (1 << OMAPFB_COLOR_YUV422) |
701 (1 << OMAPFB_COLOR_YUY422);
702 if (plane == 0)
703 caps->plane_color |= (1 << OMAPFB_COLOR_CLUT_8BPP) |
704 (1 << OMAPFB_COLOR_CLUT_4BPP) |
705 (1 << OMAPFB_COLOR_CLUT_2BPP) |
706 (1 << OMAPFB_COLOR_CLUT_1BPP) |
707 (1 << OMAPFB_COLOR_RGB444);
708 }
709
710 static enum omapfb_update_mode omap_dispc_get_update_mode(void)
711 {
712 return dispc.update_mode;
713 }
714
715 static void setup_color_conv_coef(void)
716 {
717 u32 mask = FLD_MASK(16, 11) | FLD_MASK(0, 11);
718 int cf1_reg = DISPC_VID1_BASE + DISPC_VID_CONV_COEF0;
719 int cf2_reg = DISPC_VID2_BASE + DISPC_VID_CONV_COEF0;
720 int at1_reg = DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES;
721 int at2_reg = DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES;
722 const struct color_conv_coef {
723 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
724 int full_range;
725 } ctbl_bt601_5 = {
726 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
727 };
728 const struct color_conv_coef *ct;
729 #define CVAL(x, y) (((x & 2047) << 16) | (y & 2047))
730
731 ct = &ctbl_bt601_5;
732
733 MOD_REG_FLD(cf1_reg, mask, CVAL(ct->rcr, ct->ry));
734 MOD_REG_FLD(cf1_reg + 4, mask, CVAL(ct->gy, ct->rcb));
735 MOD_REG_FLD(cf1_reg + 8, mask, CVAL(ct->gcb, ct->gcr));
736 MOD_REG_FLD(cf1_reg + 12, mask, CVAL(ct->bcr, ct->by));
737 MOD_REG_FLD(cf1_reg + 16, mask, CVAL(0, ct->bcb));
738
739 MOD_REG_FLD(cf2_reg, mask, CVAL(ct->rcr, ct->ry));
740 MOD_REG_FLD(cf2_reg + 4, mask, CVAL(ct->gy, ct->rcb));
741 MOD_REG_FLD(cf2_reg + 8, mask, CVAL(ct->gcb, ct->gcr));
742 MOD_REG_FLD(cf2_reg + 12, mask, CVAL(ct->bcr, ct->by));
743 MOD_REG_FLD(cf2_reg + 16, mask, CVAL(0, ct->bcb));
744 #undef CVAL
745
746 MOD_REG_FLD(at1_reg, (1 << 11), ct->full_range);
747 MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);
748 }
749
750 static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div)
751 {
752 unsigned long fck, lck;
753
754 *lck_div = 1;
755 pck = max(1, pck);
756 fck = clk_get_rate(dispc.dss1_fck);
757 lck = fck;
758 *pck_div = (lck + pck - 1) / pck;
759 if (is_tft)
760 *pck_div = max(2, *pck_div);
761 else
762 *pck_div = max(3, *pck_div);
763 if (*pck_div > 255) {
764 *pck_div = 255;
765 lck = pck * *pck_div;
766 *lck_div = fck / lck;
767 BUG_ON(*lck_div < 1);
768 if (*lck_div > 255) {
769 *lck_div = 255;
770 dev_warn(dispc.fbdev->dev, "pixclock %d kHz too low.\n",
771 pck / 1000);
772 }
773 }
774 }
775
776 static void set_lcd_tft_mode(int enable)
777 {
778 u32 mask;
779
780 mask = 1 << 3;
781 MOD_REG_FLD(DISPC_CONTROL, mask, enable ? mask : 0);
782 }
783
784 static void set_lcd_timings(void)
785 {
786 u32 l;
787 int lck_div, pck_div;
788 struct lcd_panel *panel = dispc.fbdev->panel;
789 int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
790 unsigned long fck;
791
792 l = dispc_read_reg(DISPC_TIMING_H);
793 l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
794 l |= ( max(1, (min(64, panel->hsw))) - 1 ) << 0;
795 l |= ( max(1, (min(256, panel->hfp))) - 1 ) << 8;
796 l |= ( max(1, (min(256, panel->hbp))) - 1 ) << 20;
797 dispc_write_reg(DISPC_TIMING_H, l);
798
799 l = dispc_read_reg(DISPC_TIMING_V);
800 l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
801 l |= ( max(1, (min(64, panel->vsw))) - 1 ) << 0;
802 l |= ( max(0, (min(255, panel->vfp))) - 0 ) << 8;
803 l |= ( max(0, (min(255, panel->vbp))) - 0 ) << 20;
804 dispc_write_reg(DISPC_TIMING_V, l);
805
806 l = dispc_read_reg(DISPC_POL_FREQ);
807 l &= ~FLD_MASK(12, 6);
808 l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 12;
809 l |= panel->acb & 0xff;
810 dispc_write_reg(DISPC_POL_FREQ, l);
811
812 calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div);
813
814 l = dispc_read_reg(DISPC_DIVISOR);
815 l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8));
816 l |= (lck_div << 16) | (pck_div << 0);
817 dispc_write_reg(DISPC_DIVISOR, l);
818
819 /* update panel info with the exact clock */
820 fck = clk_get_rate(dispc.dss1_fck);
821 panel->pixel_clock = fck / lck_div / pck_div / 1000;
822 }
823
824 static void recalc_irq_mask(void)
825 {
826 int i;
827 unsigned long irq_mask = DISPC_IRQ_MASK_ERROR;
828
829 for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
830 if (!dispc.irq_handlers[i].callback)
831 continue;
832
833 irq_mask |= dispc.irq_handlers[i].irq_mask;
834 }
835
836 enable_lcd_clocks(1);
837 MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
838 enable_lcd_clocks(0);
839 }
840
841 int omap_dispc_request_irq(unsigned long irq_mask, void (*callback)(void *data),
842 void *data)
843 {
844 int i;
845
846 BUG_ON(callback == NULL);
847
848 for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
849 if (dispc.irq_handlers[i].callback)
850 continue;
851
852 dispc.irq_handlers[i].irq_mask = irq_mask;
853 dispc.irq_handlers[i].callback = callback;
854 dispc.irq_handlers[i].data = data;
855 recalc_irq_mask();
856
857 return 0;
858 }
859
860 return -EBUSY;
861 }
862 EXPORT_SYMBOL(omap_dispc_request_irq);
863
864 void omap_dispc_free_irq(unsigned long irq_mask, void (*callback)(void *data),
865 void *data)
866 {
867 int i;
868
869 for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
870 if (dispc.irq_handlers[i].callback == callback &&
871 dispc.irq_handlers[i].data == data) {
872 dispc.irq_handlers[i].irq_mask = 0;
873 dispc.irq_handlers[i].callback = NULL;
874 dispc.irq_handlers[i].data = NULL;
875 recalc_irq_mask();
876 return;
877 }
878 }
879
880 BUG();
881 }
882 EXPORT_SYMBOL(omap_dispc_free_irq);
883
884 static irqreturn_t omap_dispc_irq_handler(int irq, void *dev)
885 {
886 u32 stat;
887 int i = 0;
888
889 enable_lcd_clocks(1);
890
891 stat = dispc_read_reg(DISPC_IRQSTATUS);
892 if (stat & DISPC_IRQ_FRAMEMASK)
893 complete(&dispc.frame_done);
894
895 if (stat & DISPC_IRQ_MASK_ERROR) {
896 if (printk_ratelimit()) {
897 dev_err(dispc.fbdev->dev, "irq error status %04x\n",
898 stat & 0x7fff);
899 }
900 }
901
902 for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
903 if (unlikely(dispc.irq_handlers[i].callback &&
904 (stat & dispc.irq_handlers[i].irq_mask)))
905 dispc.irq_handlers[i].callback(
906 dispc.irq_handlers[i].data);
907 }
908
909 dispc_write_reg(DISPC_IRQSTATUS, stat);
910
911 enable_lcd_clocks(0);
912
913 return IRQ_HANDLED;
914 }
915
916 static int get_dss_clocks(void)
917 {
918 dispc.dss_ick = clk_get(&dispc.fbdev->dssdev->dev, "ick");
919 if (IS_ERR(dispc.dss_ick)) {
920 dev_err(dispc.fbdev->dev, "can't get ick\n");
921 return PTR_ERR(dispc.dss_ick);
922 }
923
924 dispc.dss1_fck = clk_get(&dispc.fbdev->dssdev->dev, "dss1_fck");
925 if (IS_ERR(dispc.dss1_fck)) {
926 dev_err(dispc.fbdev->dev, "can't get dss1_fck\n");
927 clk_put(dispc.dss_ick);
928 return PTR_ERR(dispc.dss1_fck);
929 }
930
931 dispc.dss_54m_fck = clk_get(&dispc.fbdev->dssdev->dev, "tv_fck");
932 if (IS_ERR(dispc.dss_54m_fck)) {
933 dev_err(dispc.fbdev->dev, "can't get tv_fck\n");
934 clk_put(dispc.dss_ick);
935 clk_put(dispc.dss1_fck);
936 return PTR_ERR(dispc.dss_54m_fck);
937 }
938
939 return 0;
940 }
941
942 static void put_dss_clocks(void)
943 {
944 clk_put(dispc.dss_54m_fck);
945 clk_put(dispc.dss1_fck);
946 clk_put(dispc.dss_ick);
947 }
948
949 static void enable_lcd_clocks(int enable)
950 {
951 if (enable) {
952 clk_enable(dispc.dss_ick);
953 clk_enable(dispc.dss1_fck);
954 } else {
955 clk_disable(dispc.dss1_fck);
956 clk_disable(dispc.dss_ick);
957 }
958 }
959
960 static void enable_digit_clocks(int enable)
961 {
962 if (enable)
963 clk_enable(dispc.dss_54m_fck);
964 else
965 clk_disable(dispc.dss_54m_fck);
966 }
967
968 static void omap_dispc_suspend(void)
969 {
970 if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
971 init_completion(&dispc.frame_done);
972 omap_dispc_enable_lcd_out(0);
973 if (!wait_for_completion_timeout(&dispc.frame_done,
974 msecs_to_jiffies(500))) {
975 dev_err(dispc.fbdev->dev,
976 "timeout waiting for FRAME DONE\n");
977 }
978 enable_lcd_clocks(0);
979 }
980 }
981
982 static void omap_dispc_resume(void)
983 {
984 if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
985 enable_lcd_clocks(1);
986 if (!dispc.ext_mode) {
987 set_lcd_timings();
988 load_palette();
989 }
990 omap_dispc_enable_lcd_out(1);
991 }
992 }
993
994
995 static int omap_dispc_update_window(struct fb_info *fbi,
996 struct omapfb_update_window *win,
997 void (*complete_callback)(void *arg),
998 void *complete_callback_data)
999 {
1000 return dispc.update_mode == OMAPFB_UPDATE_DISABLED ? -ENODEV : 0;
1001 }
1002
1003 static int mmap_kern(struct omapfb_mem_region *region)
1004 {
1005 struct vm_struct *kvma;
1006 struct vm_area_struct vma;
1007 pgprot_t pgprot;
1008 unsigned long vaddr;
1009
1010 kvma = get_vm_area(region->size, VM_IOREMAP);
1011 if (kvma == NULL) {
1012 dev_err(dispc.fbdev->dev, "can't get kernel vm area\n");
1013 return -ENOMEM;
1014 }
1015 vma.vm_mm = &init_mm;
1016
1017 vaddr = (unsigned long)kvma->addr;
1018
1019 pgprot = pgprot_writecombine(pgprot_kernel);
1020 vma.vm_start = vaddr;
1021 vma.vm_end = vaddr + region->size;
1022 if (io_remap_pfn_range(&vma, vaddr, region->paddr >> PAGE_SHIFT,
1023 region->size, pgprot) < 0) {
1024 dev_err(dispc.fbdev->dev, "kernel mmap for FBMEM failed\n");
1025 return -EAGAIN;
1026 }
1027 region->vaddr = (void *)vaddr;
1028
1029 return 0;
1030 }
1031
1032 static void mmap_user_open(struct vm_area_struct *vma)
1033 {
1034 int plane = (int)vma->vm_private_data;
1035
1036 atomic_inc(&dispc.map_count[plane]);
1037 }
1038
1039 static void mmap_user_close(struct vm_area_struct *vma)
1040 {
1041 int plane = (int)vma->vm_private_data;
1042
1043 atomic_dec(&dispc.map_count[plane]);
1044 }
1045
1046 static const struct vm_operations_struct mmap_user_ops = {
1047 .open = mmap_user_open,
1048 .close = mmap_user_close,
1049 };
1050
1051 static int omap_dispc_mmap_user(struct fb_info *info,
1052 struct vm_area_struct *vma)
1053 {
1054 struct omapfb_plane_struct *plane = info->par;
1055 unsigned long off;
1056 unsigned long start;
1057 u32 len;
1058
1059 if (vma->vm_end - vma->vm_start == 0)
1060 return 0;
1061 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1062 return -EINVAL;
1063 off = vma->vm_pgoff << PAGE_SHIFT;
1064
1065 start = info->fix.smem_start;
1066 len = info->fix.smem_len;
1067 if (off >= len)
1068 return -EINVAL;
1069 if ((vma->vm_end - vma->vm_start + off) > len)
1070 return -EINVAL;
1071 off += start;
1072 vma->vm_pgoff = off >> PAGE_SHIFT;
1073 vma->vm_flags |= VM_IO | VM_RESERVED;
1074 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1075 vma->vm_ops = &mmap_user_ops;
1076 vma->vm_private_data = (void *)plane->idx;
1077 if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
1078 vma->vm_end - vma->vm_start, vma->vm_page_prot))
1079 return -EAGAIN;
1080 /* vm_ops.open won't be called for mmap itself. */
1081 atomic_inc(&dispc.map_count[plane->idx]);
1082 return 0;
1083 }
1084
1085 static void unmap_kern(struct omapfb_mem_region *region)
1086 {
1087 vunmap(region->vaddr);
1088 }
1089
1090 static int alloc_palette_ram(void)
1091 {
1092 dispc.palette_vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1093 MAX_PALETTE_SIZE, &dispc.palette_paddr, GFP_KERNEL);
1094 if (dispc.palette_vaddr == NULL) {
1095 dev_err(dispc.fbdev->dev, "failed to alloc palette memory\n");
1096 return -ENOMEM;
1097 }
1098
1099 return 0;
1100 }
1101
1102 static void free_palette_ram(void)
1103 {
1104 dma_free_writecombine(dispc.fbdev->dev, MAX_PALETTE_SIZE,
1105 dispc.palette_vaddr, dispc.palette_paddr);
1106 }
1107
1108 static int alloc_fbmem(struct omapfb_mem_region *region)
1109 {
1110 region->vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1111 region->size, &region->paddr, GFP_KERNEL);
1112
1113 if (region->vaddr == NULL) {
1114 dev_err(dispc.fbdev->dev, "unable to allocate FB DMA memory\n");
1115 return -ENOMEM;
1116 }
1117
1118 return 0;
1119 }
1120
1121 static void free_fbmem(struct omapfb_mem_region *region)
1122 {
1123 dma_free_writecombine(dispc.fbdev->dev, region->size,
1124 region->vaddr, region->paddr);
1125 }
1126
1127 static struct resmap *init_resmap(unsigned long start, size_t size)
1128 {
1129 unsigned page_cnt;
1130 struct resmap *res_map;
1131
1132 page_cnt = PAGE_ALIGN(size) / PAGE_SIZE;
1133 res_map =
1134 kzalloc(sizeof(struct resmap) + RESMAP_SIZE(page_cnt), GFP_KERNEL);
1135 if (res_map == NULL)
1136 return NULL;
1137 res_map->start = start;
1138 res_map->page_cnt = page_cnt;
1139 res_map->map = (unsigned long *)(res_map + 1);
1140 return res_map;
1141 }
1142
1143 static void cleanup_resmap(struct resmap *res_map)
1144 {
1145 kfree(res_map);
1146 }
1147
1148 static inline int resmap_mem_type(unsigned long start)
1149 {
1150 if (start >= OMAP2_SRAM_START &&
1151 start < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
1152 return OMAPFB_MEMTYPE_SRAM;
1153 else
1154 return OMAPFB_MEMTYPE_SDRAM;
1155 }
1156
1157 static inline int resmap_page_reserved(struct resmap *res_map, unsigned page_nr)
1158 {
1159 return *RESMAP_PTR(res_map, page_nr) & RESMAP_MASK(page_nr) ? 1 : 0;
1160 }
1161
1162 static inline void resmap_reserve_page(struct resmap *res_map, unsigned page_nr)
1163 {
1164 BUG_ON(resmap_page_reserved(res_map, page_nr));
1165 *RESMAP_PTR(res_map, page_nr) |= RESMAP_MASK(page_nr);
1166 }
1167
1168 static inline void resmap_free_page(struct resmap *res_map, unsigned page_nr)
1169 {
1170 BUG_ON(!resmap_page_reserved(res_map, page_nr));
1171 *RESMAP_PTR(res_map, page_nr) &= ~RESMAP_MASK(page_nr);
1172 }
1173
1174 static void resmap_reserve_region(unsigned long start, size_t size)
1175 {
1176
1177 struct resmap *res_map;
1178 unsigned start_page;
1179 unsigned end_page;
1180 int mtype;
1181 unsigned i;
1182
1183 mtype = resmap_mem_type(start);
1184 res_map = dispc.res_map[mtype];
1185 dev_dbg(dispc.fbdev->dev, "reserve mem type %d start %08lx size %d\n",
1186 mtype, start, size);
1187 start_page = (start - res_map->start) / PAGE_SIZE;
1188 end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE;
1189 for (i = start_page; i < end_page; i++)
1190 resmap_reserve_page(res_map, i);
1191 }
1192
1193 static void resmap_free_region(unsigned long start, size_t size)
1194 {
1195 struct resmap *res_map;
1196 unsigned start_page;
1197 unsigned end_page;
1198 unsigned i;
1199 int mtype;
1200
1201 mtype = resmap_mem_type(start);
1202 res_map = dispc.res_map[mtype];
1203 dev_dbg(dispc.fbdev->dev, "free mem type %d start %08lx size %d\n",
1204 mtype, start, size);
1205 start_page = (start - res_map->start) / PAGE_SIZE;
1206 end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE;
1207 for (i = start_page; i < end_page; i++)
1208 resmap_free_page(res_map, i);
1209 }
1210
1211 static unsigned long resmap_alloc_region(int mtype, size_t size)
1212 {
1213 unsigned i;
1214 unsigned total;
1215 unsigned start_page;
1216 unsigned long start;
1217 struct resmap *res_map = dispc.res_map[mtype];
1218
1219 BUG_ON(mtype >= DISPC_MEMTYPE_NUM || res_map == NULL || !size);
1220
1221 size = PAGE_ALIGN(size) / PAGE_SIZE;
1222 start_page = 0;
1223 total = 0;
1224 for (i = 0; i < res_map->page_cnt; i++) {
1225 if (resmap_page_reserved(res_map, i)) {
1226 start_page = i + 1;
1227 total = 0;
1228 } else if (++total == size)
1229 break;
1230 }
1231 if (total < size)
1232 return 0;
1233
1234 start = res_map->start + start_page * PAGE_SIZE;
1235 resmap_reserve_region(start, size * PAGE_SIZE);
1236
1237 return start;
1238 }
1239
1240 /* Note that this will only work for user mappings, we don't deal with
1241 * kernel mappings here, so fbcon will keep using the old region.
1242 */
1243 static int omap_dispc_setup_mem(int plane, size_t size, int mem_type,
1244 unsigned long *paddr)
1245 {
1246 struct omapfb_mem_region *rg;
1247 unsigned long new_addr = 0;
1248
1249 if ((unsigned)plane > dispc.mem_desc.region_cnt)
1250 return -EINVAL;
1251 if (mem_type >= DISPC_MEMTYPE_NUM)
1252 return -EINVAL;
1253 if (dispc.res_map[mem_type] == NULL)
1254 return -ENOMEM;
1255 rg = &dispc.mem_desc.region[plane];
1256 if (size == rg->size && mem_type == rg->type)
1257 return 0;
1258 if (atomic_read(&dispc.map_count[plane]))
1259 return -EBUSY;
1260 if (rg->size != 0)
1261 resmap_free_region(rg->paddr, rg->size);
1262 if (size != 0) {
1263 new_addr = resmap_alloc_region(mem_type, size);
1264 if (!new_addr) {
1265 /* Reallocate old region. */
1266 resmap_reserve_region(rg->paddr, rg->size);
1267 return -ENOMEM;
1268 }
1269 }
1270 rg->paddr = new_addr;
1271 rg->size = size;
1272 rg->type = mem_type;
1273
1274 *paddr = new_addr;
1275
1276 return 0;
1277 }
1278
1279 static int setup_fbmem(struct omapfb_mem_desc *req_md)
1280 {
1281 struct omapfb_mem_region *rg;
1282 int i;
1283 int r;
1284 unsigned long mem_start[DISPC_MEMTYPE_NUM];
1285 unsigned long mem_end[DISPC_MEMTYPE_NUM];
1286
1287 if (!req_md->region_cnt) {
1288 dev_err(dispc.fbdev->dev, "no memory regions defined\n");
1289 return -ENOENT;
1290 }
1291
1292 rg = &req_md->region[0];
1293 memset(mem_start, 0xff, sizeof(mem_start));
1294 memset(mem_end, 0, sizeof(mem_end));
1295
1296 for (i = 0; i < req_md->region_cnt; i++, rg++) {
1297 int mtype;
1298 if (rg->paddr) {
1299 rg->alloc = 0;
1300 if (rg->vaddr == NULL) {
1301 rg->map = 1;
1302 if ((r = mmap_kern(rg)) < 0)
1303 return r;
1304 }
1305 } else {
1306 if (rg->type != OMAPFB_MEMTYPE_SDRAM) {
1307 dev_err(dispc.fbdev->dev,
1308 "unsupported memory type\n");
1309 return -EINVAL;
1310 }
1311 rg->alloc = rg->map = 1;
1312 if ((r = alloc_fbmem(rg)) < 0)
1313 return r;
1314 }
1315 mtype = rg->type;
1316
1317 if (rg->paddr < mem_start[mtype])
1318 mem_start[mtype] = rg->paddr;
1319 if (rg->paddr + rg->size > mem_end[mtype])
1320 mem_end[mtype] = rg->paddr + rg->size;
1321 }
1322
1323 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1324 unsigned long start;
1325 size_t size;
1326 if (mem_end[i] == 0)
1327 continue;
1328 start = mem_start[i];
1329 size = mem_end[i] - start;
1330 dispc.res_map[i] = init_resmap(start, size);
1331 r = -ENOMEM;
1332 if (dispc.res_map[i] == NULL)
1333 goto fail;
1334 /* Initial state is that everything is reserved. This
1335 * includes possible holes as well, which will never be
1336 * freed.
1337 */
1338 resmap_reserve_region(start, size);
1339 }
1340
1341 dispc.mem_desc = *req_md;
1342
1343 return 0;
1344 fail:
1345 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1346 if (dispc.res_map[i] != NULL)
1347 cleanup_resmap(dispc.res_map[i]);
1348 }
1349 return r;
1350 }
1351
1352 static void cleanup_fbmem(void)
1353 {
1354 struct omapfb_mem_region *rg;
1355 int i;
1356
1357 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1358 if (dispc.res_map[i] != NULL)
1359 cleanup_resmap(dispc.res_map[i]);
1360 }
1361 rg = &dispc.mem_desc.region[0];
1362 for (i = 0; i < dispc.mem_desc.region_cnt; i++, rg++) {
1363 if (rg->alloc)
1364 free_fbmem(rg);
1365 else {
1366 if (rg->map)
1367 unmap_kern(rg);
1368 }
1369 }
1370 }
1371
1372 static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
1373 struct omapfb_mem_desc *req_vram)
1374 {
1375 int r;
1376 u32 l;
1377 struct lcd_panel *panel = fbdev->panel;
1378 void __iomem *ram_fw_base;
1379 int tmo = 10000;
1380 int skip_init = 0;
1381 int i;
1382
1383 memset(&dispc, 0, sizeof(dispc));
1384
1385 dispc.base = ioremap(DISPC_BASE, SZ_1K);
1386 if (!dispc.base) {
1387 dev_err(fbdev->dev, "can't ioremap DISPC\n");
1388 return -ENOMEM;
1389 }
1390
1391 dispc.fbdev = fbdev;
1392 dispc.ext_mode = ext_mode;
1393
1394 init_completion(&dispc.frame_done);
1395
1396 if ((r = get_dss_clocks()) < 0)
1397 goto fail0;
1398
1399 enable_lcd_clocks(1);
1400
1401 #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
1402 l = dispc_read_reg(DISPC_CONTROL);
1403 /* LCD enabled ? */
1404 if (l & 1) {
1405 pr_info("omapfb: skipping hardware initialization\n");
1406 skip_init = 1;
1407 }
1408 #endif
1409
1410 if (!skip_init) {
1411 /* Reset monitoring works only w/ the 54M clk */
1412 enable_digit_clocks(1);
1413
1414 /* Soft reset */
1415 MOD_REG_FLD(DISPC_SYSCONFIG, 1 << 1, 1 << 1);
1416
1417 while (!(dispc_read_reg(DISPC_SYSSTATUS) & 1)) {
1418 if (!--tmo) {
1419 dev_err(dispc.fbdev->dev, "soft reset failed\n");
1420 r = -ENODEV;
1421 enable_digit_clocks(0);
1422 goto fail1;
1423 }
1424 }
1425
1426 enable_digit_clocks(0);
1427 }
1428
1429 /* Enable smart standby/idle, autoidle and wakeup */
1430 l = dispc_read_reg(DISPC_SYSCONFIG);
1431 l &= ~((3 << 12) | (3 << 3));
1432 l |= (2 << 12) | (2 << 3) | (1 << 2) | (1 << 0);
1433 dispc_write_reg(DISPC_SYSCONFIG, l);
1434 omap_writel(1 << 0, DSS_BASE + DSS_SYSCONFIG);
1435
1436 /* Set functional clock autogating */
1437 l = dispc_read_reg(DISPC_CONFIG);
1438 l |= 1 << 9;
1439 dispc_write_reg(DISPC_CONFIG, l);
1440
1441 l = dispc_read_reg(DISPC_IRQSTATUS);
1442 dispc_write_reg(DISPC_IRQSTATUS, l);
1443
1444 recalc_irq_mask();
1445
1446 if ((r = request_irq(INT_24XX_DSS_IRQ, omap_dispc_irq_handler,
1447 0, MODULE_NAME, fbdev)) < 0) {
1448 dev_err(dispc.fbdev->dev, "can't get DSS IRQ\n");
1449 goto fail1;
1450 }
1451
1452 /* L3 firewall setting: enable access to OCM RAM */
1453 ram_fw_base = ioremap(0x68005000, SZ_1K);
1454 if (!ram_fw_base) {
1455 dev_err(dispc.fbdev->dev, "Cannot ioremap to enable OCM RAM\n");
1456 goto fail1;
1457 }
1458 __raw_writel(0x402000b0, ram_fw_base + 0xa0);
1459 iounmap(ram_fw_base);
1460
1461 if ((r = alloc_palette_ram()) < 0)
1462 goto fail2;
1463
1464 if ((r = setup_fbmem(req_vram)) < 0)
1465 goto fail3;
1466
1467 if (!skip_init) {
1468 for (i = 0; i < dispc.mem_desc.region_cnt; i++) {
1469 memset(dispc.mem_desc.region[i].vaddr, 0,
1470 dispc.mem_desc.region[i].size);
1471 }
1472
1473 /* Set logic clock to fck, pixel clock to fck/2 for now */
1474 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(16, 8), 1 << 16);
1475 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(0, 8), 2 << 0);
1476
1477 setup_plane_fifo(0, ext_mode);
1478 setup_plane_fifo(1, ext_mode);
1479 setup_plane_fifo(2, ext_mode);
1480
1481 setup_color_conv_coef();
1482
1483 set_lcd_tft_mode(panel->config & OMAP_LCDC_PANEL_TFT);
1484 set_load_mode(DISPC_LOAD_FRAME_ONLY);
1485
1486 if (!ext_mode) {
1487 set_lcd_data_lines(panel->data_lines);
1488 omap_dispc_set_lcd_size(panel->x_res, panel->y_res);
1489 set_lcd_timings();
1490 } else
1491 set_lcd_data_lines(panel->bpp);
1492 enable_rfbi_mode(ext_mode);
1493 }
1494
1495 l = dispc_read_reg(DISPC_REVISION);
1496 pr_info("omapfb: DISPC version %d.%d initialized\n",
1497 l >> 4 & 0x0f, l & 0x0f);
1498 enable_lcd_clocks(0);
1499
1500 return 0;
1501 fail3:
1502 free_palette_ram();
1503 fail2:
1504 free_irq(INT_24XX_DSS_IRQ, fbdev);
1505 fail1:
1506 enable_lcd_clocks(0);
1507 put_dss_clocks();
1508 fail0:
1509 iounmap(dispc.base);
1510 return r;
1511 }
1512
1513 static void omap_dispc_cleanup(void)
1514 {
1515 int i;
1516
1517 omap_dispc_set_update_mode(OMAPFB_UPDATE_DISABLED);
1518 /* This will also disable clocks that are on */
1519 for (i = 0; i < dispc.mem_desc.region_cnt; i++)
1520 omap_dispc_enable_plane(i, 0);
1521 cleanup_fbmem();
1522 free_palette_ram();
1523 free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
1524 put_dss_clocks();
1525 iounmap(dispc.base);
1526 }
1527
1528 const struct lcd_ctrl omap2_int_ctrl = {
1529 .name = "internal",
1530 .init = omap_dispc_init,
1531 .cleanup = omap_dispc_cleanup,
1532 .get_caps = omap_dispc_get_caps,
1533 .set_update_mode = omap_dispc_set_update_mode,
1534 .get_update_mode = omap_dispc_get_update_mode,
1535 .update_window = omap_dispc_update_window,
1536 .suspend = omap_dispc_suspend,
1537 .resume = omap_dispc_resume,
1538 .setup_plane = omap_dispc_setup_plane,
1539 .setup_mem = omap_dispc_setup_mem,
1540 .set_scale = omap_dispc_set_scale,
1541 .enable_plane = omap_dispc_enable_plane,
1542 .set_color_key = omap_dispc_set_color_key,
1543 .get_color_key = omap_dispc_get_color_key,
1544 .mmap = omap_dispc_mmap_user,
1545 };