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[pohmelfs.git] / arch / avr32 / mach-at32ap / at32ap700x.c
blob402a7bb726696b4091e15a4e367004e634295859
1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/gpio.h>
17 #include <linux/spi/spi.h>
18 #include <linux/usb/atmel_usba_udc.h>
19
20 #include <mach/atmel-mci.h>
21 #include <linux/atmel-mci.h>
22
23 #include <asm/io.h>
24 #include <asm/irq.h>
25
26 #include <mach/at32ap700x.h>
27 #include <mach/board.h>
28 #include <mach/hmatrix.h>
29 #include <mach/portmux.h>
30 #include <mach/sram.h>
31
32 #include <sound/atmel-abdac.h>
33 #include <sound/atmel-ac97c.h>
34
35 #include <video/atmel_lcdc.h>
36
37 #include "clock.h"
38 #include "pio.h"
39 #include "pm.h"
40
41
42 #define PBMEM(base) \
43 { \
44 .start = base, \
45 .end = base + 0x3ff, \
46 .flags = IORESOURCE_MEM, \
47 }
48 #define IRQ(num) \
49 { \
50 .start = num, \
51 .end = num, \
52 .flags = IORESOURCE_IRQ, \
53 }
54 #define NAMED_IRQ(num, _name) \
55 { \
56 .start = num, \
57 .end = num, \
58 .name = _name, \
59 .flags = IORESOURCE_IRQ, \
60 }
61
62 /* REVISIT these assume *every* device supports DMA, but several
63 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
64 */
65 #define DEFINE_DEV(_name, _id) \
66 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
67 static struct platform_device _name##_id##_device = { \
68 .name = #_name, \
69 .id = _id, \
70 .dev = { \
71 .dma_mask = &_name##_id##_dma_mask, \
72 .coherent_dma_mask = DMA_BIT_MASK(32), \
73 }, \
74 .resource = _name##_id##_resource, \
75 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
76 }
77 #define DEFINE_DEV_DATA(_name, _id) \
78 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
79 static struct platform_device _name##_id##_device = { \
80 .name = #_name, \
81 .id = _id, \
82 .dev = { \
83 .dma_mask = &_name##_id##_dma_mask, \
84 .platform_data = &_name##_id##_data, \
85 .coherent_dma_mask = DMA_BIT_MASK(32), \
86 }, \
87 .resource = _name##_id##_resource, \
88 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
89 }
90
91 #define select_peripheral(port, pin_mask, periph, flags) \
92 at32_select_periph(GPIO_##port##_BASE, pin_mask, \
93 GPIO_##periph, flags)
94
95 #define DEV_CLK(_name, devname, bus, _index) \
96 static struct clk devname##_##_name = { \
97 .name = #_name, \
98 .dev = &devname##_device.dev, \
99 .parent = &bus##_clk, \
100 .mode = bus##_clk_mode, \
101 .get_rate = bus##_clk_get_rate, \
102 .index = _index, \
103 }
104
105 static DEFINE_SPINLOCK(pm_lock);
106
107 static struct clk osc0;
108 static struct clk osc1;
109
110 static unsigned long osc_get_rate(struct clk *clk)
111 {
112 return at32_board_osc_rates[clk->index];
113 }
114
115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
116 {
117 unsigned long div, mul, rate;
118
119 div = PM_BFEXT(PLLDIV, control) + 1;
120 mul = PM_BFEXT(PLLMUL, control) + 1;
121
122 rate = clk->parent->get_rate(clk->parent);
123 rate = (rate + div / 2) / div;
124 rate *= mul;
125
126 return rate;
127 }
128
129 static long pll_set_rate(struct clk *clk, unsigned long rate,
130 u32 *pll_ctrl)
131 {
132 unsigned long mul;
133 unsigned long mul_best_fit = 0;
134 unsigned long div;
135 unsigned long div_min;
136 unsigned long div_max;
137 unsigned long div_best_fit = 0;
138 unsigned long base;
139 unsigned long pll_in;
140 unsigned long actual = 0;
141 unsigned long rate_error;
142 unsigned long rate_error_prev = ~0UL;
143 u32 ctrl;
144
145 /* Rate must be between 80 MHz and 200 Mhz. */
146 if (rate < 80000000UL || rate > 200000000UL)
147 return -EINVAL;
148
149 ctrl = PM_BF(PLLOPT, 4);
150 base = clk->parent->get_rate(clk->parent);
151
152 /* PLL input frequency must be between 6 MHz and 32 MHz. */
153 div_min = DIV_ROUND_UP(base, 32000000UL);
154 div_max = base / 6000000UL;
155
156 if (div_max < div_min)
157 return -EINVAL;
158
159 for (div = div_min; div <= div_max; div++) {
160 pll_in = (base + div / 2) / div;
161 mul = (rate + pll_in / 2) / pll_in;
162
163 if (mul == 0)
164 continue;
165
166 actual = pll_in * mul;
167 rate_error = abs(actual - rate);
168
169 if (rate_error < rate_error_prev) {
170 mul_best_fit = mul;
171 div_best_fit = div;
172 rate_error_prev = rate_error;
173 }
174
175 if (rate_error == 0)
176 break;
177 }
178
179 if (div_best_fit == 0)
180 return -EINVAL;
181
182 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
183 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
184 ctrl |= PM_BF(PLLCOUNT, 16);
185
186 if (clk->parent == &osc1)
187 ctrl |= PM_BIT(PLLOSC);
188
189 *pll_ctrl = ctrl;
190
191 return actual;
192 }
193
194 static unsigned long pll0_get_rate(struct clk *clk)
195 {
196 u32 control;
197
198 control = pm_readl(PLL0);
199
200 return pll_get_rate(clk, control);
201 }
202
203 static void pll1_mode(struct clk *clk, int enabled)
204 {
205 unsigned long timeout;
206 u32 status;
207 u32 ctrl;
208
209 ctrl = pm_readl(PLL1);
210
211 if (enabled) {
212 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
213 pr_debug("clk %s: failed to enable, rate not set\n",
214 clk->name);
215 return;
216 }
217
218 ctrl |= PM_BIT(PLLEN);
219 pm_writel(PLL1, ctrl);
220
221 /* Wait for PLL lock. */
222 for (timeout = 10000; timeout; timeout--) {
223 status = pm_readl(ISR);
224 if (status & PM_BIT(LOCK1))
225 break;
226 udelay(10);
227 }
228
229 if (!(status & PM_BIT(LOCK1)))
230 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
231 clk->name);
232 } else {
233 ctrl &= ~PM_BIT(PLLEN);
234 pm_writel(PLL1, ctrl);
235 }
236 }
237
238 static unsigned long pll1_get_rate(struct clk *clk)
239 {
240 u32 control;
241
242 control = pm_readl(PLL1);
243
244 return pll_get_rate(clk, control);
245 }
246
247 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
248 {
249 u32 ctrl = 0;
250 unsigned long actual_rate;
251
252 actual_rate = pll_set_rate(clk, rate, &ctrl);
253
254 if (apply) {
255 if (actual_rate != rate)
256 return -EINVAL;
257 if (clk->users > 0)
258 return -EBUSY;
259 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
260 clk->name, rate, actual_rate);
261 pm_writel(PLL1, ctrl);
262 }
263
264 return actual_rate;
265 }
266
267 static int pll1_set_parent(struct clk *clk, struct clk *parent)
268 {
269 u32 ctrl;
270
271 if (clk->users > 0)
272 return -EBUSY;
273
274 ctrl = pm_readl(PLL1);
275 WARN_ON(ctrl & PM_BIT(PLLEN));
276
277 if (parent == &osc0)
278 ctrl &= ~PM_BIT(PLLOSC);
279 else if (parent == &osc1)
280 ctrl |= PM_BIT(PLLOSC);
281 else
282 return -EINVAL;
283
284 pm_writel(PLL1, ctrl);
285 clk->parent = parent;
286
287 return 0;
288 }
289
290 /*
291 * The AT32AP7000 has five primary clock sources: One 32kHz
292 * oscillator, two crystal oscillators and two PLLs.
293 */
294 static struct clk osc32k = {
295 .name = "osc32k",
296 .get_rate = osc_get_rate,
297 .users = 1,
298 .index = 0,
299 };
300 static struct clk osc0 = {
301 .name = "osc0",
302 .get_rate = osc_get_rate,
303 .users = 1,
304 .index = 1,
305 };
306 static struct clk osc1 = {
307 .name = "osc1",
308 .get_rate = osc_get_rate,
309 .index = 2,
310 };
311 static struct clk pll0 = {
312 .name = "pll0",
313 .get_rate = pll0_get_rate,
314 .parent = &osc0,
315 };
316 static struct clk pll1 = {
317 .name = "pll1",
318 .mode = pll1_mode,
319 .get_rate = pll1_get_rate,
320 .set_rate = pll1_set_rate,
321 .set_parent = pll1_set_parent,
322 .parent = &osc0,
323 };
324
325 /*
326 * The main clock can be either osc0 or pll0. The boot loader may
327 * have chosen one for us, so we don't really know which one until we
328 * have a look at the SM.
329 */
330 static struct clk *main_clock;
331
332 /*
333 * Synchronous clocks are generated from the main clock. The clocks
334 * must satisfy the constraint
335 * fCPU >= fHSB >= fPB
336 * i.e. each clock must not be faster than its parent.
337 */
338 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
339 {
340 return main_clock->get_rate(main_clock) >> shift;
341 };
342
343 static void cpu_clk_mode(struct clk *clk, int enabled)
344 {
345 unsigned long flags;
346 u32 mask;
347
348 spin_lock_irqsave(&pm_lock, flags);
349 mask = pm_readl(CPU_MASK);
350 if (enabled)
351 mask |= 1 << clk->index;
352 else
353 mask &= ~(1 << clk->index);
354 pm_writel(CPU_MASK, mask);
355 spin_unlock_irqrestore(&pm_lock, flags);
356 }
357
358 static unsigned long cpu_clk_get_rate(struct clk *clk)
359 {
360 unsigned long cksel, shift = 0;
361
362 cksel = pm_readl(CKSEL);
363 if (cksel & PM_BIT(CPUDIV))
364 shift = PM_BFEXT(CPUSEL, cksel) + 1;
365
366 return bus_clk_get_rate(clk, shift);
367 }
368
369 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
370 {
371 u32 control;
372 unsigned long parent_rate, child_div, actual_rate, div;
373
374 parent_rate = clk->parent->get_rate(clk->parent);
375 control = pm_readl(CKSEL);
376
377 if (control & PM_BIT(HSBDIV))
378 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
379 else
380 child_div = 1;
381
382 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
383 actual_rate = parent_rate;
384 control &= ~PM_BIT(CPUDIV);
385 } else {
386 unsigned int cpusel;
387 div = (parent_rate + rate / 2) / rate;
388 if (div > child_div)
389 div = child_div;
390 cpusel = (div > 1) ? (fls(div) - 2) : 0;
391 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
392 actual_rate = parent_rate / (1 << (cpusel + 1));
393 }
394
395 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
396 clk->name, rate, actual_rate);
397
398 if (apply)
399 pm_writel(CKSEL, control);
400
401 return actual_rate;
402 }
403
404 static void hsb_clk_mode(struct clk *clk, int enabled)
405 {
406 unsigned long flags;
407 u32 mask;
408
409 spin_lock_irqsave(&pm_lock, flags);
410 mask = pm_readl(HSB_MASK);
411 if (enabled)
412 mask |= 1 << clk->index;
413 else
414 mask &= ~(1 << clk->index);
415 pm_writel(HSB_MASK, mask);
416 spin_unlock_irqrestore(&pm_lock, flags);
417 }
418
419 static unsigned long hsb_clk_get_rate(struct clk *clk)
420 {
421 unsigned long cksel, shift = 0;
422
423 cksel = pm_readl(CKSEL);
424 if (cksel & PM_BIT(HSBDIV))
425 shift = PM_BFEXT(HSBSEL, cksel) + 1;
426
427 return bus_clk_get_rate(clk, shift);
428 }
429
430 void pba_clk_mode(struct clk *clk, int enabled)
431 {
432 unsigned long flags;
433 u32 mask;
434
435 spin_lock_irqsave(&pm_lock, flags);
436 mask = pm_readl(PBA_MASK);
437 if (enabled)
438 mask |= 1 << clk->index;
439 else
440 mask &= ~(1 << clk->index);
441 pm_writel(PBA_MASK, mask);
442 spin_unlock_irqrestore(&pm_lock, flags);
443 }
444
445 unsigned long pba_clk_get_rate(struct clk *clk)
446 {
447 unsigned long cksel, shift = 0;
448
449 cksel = pm_readl(CKSEL);
450 if (cksel & PM_BIT(PBADIV))
451 shift = PM_BFEXT(PBASEL, cksel) + 1;
452
453 return bus_clk_get_rate(clk, shift);
454 }
455
456 static void pbb_clk_mode(struct clk *clk, int enabled)
457 {
458 unsigned long flags;
459 u32 mask;
460
461 spin_lock_irqsave(&pm_lock, flags);
462 mask = pm_readl(PBB_MASK);
463 if (enabled)
464 mask |= 1 << clk->index;
465 else
466 mask &= ~(1 << clk->index);
467 pm_writel(PBB_MASK, mask);
468 spin_unlock_irqrestore(&pm_lock, flags);
469 }
470
471 static unsigned long pbb_clk_get_rate(struct clk *clk)
472 {
473 unsigned long cksel, shift = 0;
474
475 cksel = pm_readl(CKSEL);
476 if (cksel & PM_BIT(PBBDIV))
477 shift = PM_BFEXT(PBBSEL, cksel) + 1;
478
479 return bus_clk_get_rate(clk, shift);
480 }
481
482 static struct clk cpu_clk = {
483 .name = "cpu",
484 .get_rate = cpu_clk_get_rate,
485 .set_rate = cpu_clk_set_rate,
486 .users = 1,
487 };
488 static struct clk hsb_clk = {
489 .name = "hsb",
490 .parent = &cpu_clk,
491 .get_rate = hsb_clk_get_rate,
492 };
493 static struct clk pba_clk = {
494 .name = "pba",
495 .parent = &hsb_clk,
496 .mode = hsb_clk_mode,
497 .get_rate = pba_clk_get_rate,
498 .index = 1,
499 };
500 static struct clk pbb_clk = {
501 .name = "pbb",
502 .parent = &hsb_clk,
503 .mode = hsb_clk_mode,
504 .get_rate = pbb_clk_get_rate,
505 .users = 1,
506 .index = 2,
507 };
508
509 /* --------------------------------------------------------------------
510 * Generic Clock operations
511 * -------------------------------------------------------------------- */
512
513 static void genclk_mode(struct clk *clk, int enabled)
514 {
515 u32 control;
516
517 control = pm_readl(GCCTRL(clk->index));
518 if (enabled)
519 control |= PM_BIT(CEN);
520 else
521 control &= ~PM_BIT(CEN);
522 pm_writel(GCCTRL(clk->index), control);
523 }
524
525 static unsigned long genclk_get_rate(struct clk *clk)
526 {
527 u32 control;
528 unsigned long div = 1;
529
530 control = pm_readl(GCCTRL(clk->index));
531 if (control & PM_BIT(DIVEN))
532 div = 2 * (PM_BFEXT(DIV, control) + 1);
533
534 return clk->parent->get_rate(clk->parent) / div;
535 }
536
537 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
538 {
539 u32 control;
540 unsigned long parent_rate, actual_rate, div;
541
542 parent_rate = clk->parent->get_rate(clk->parent);
543 control = pm_readl(GCCTRL(clk->index));
544
545 if (rate > 3 * parent_rate / 4) {
546 actual_rate = parent_rate;
547 control &= ~PM_BIT(DIVEN);
548 } else {
549 div = (parent_rate + rate) / (2 * rate) - 1;
550 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
551 actual_rate = parent_rate / (2 * (div + 1));
552 }
553
554 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
555 clk->name, rate, actual_rate);
556
557 if (apply)
558 pm_writel(GCCTRL(clk->index), control);
559
560 return actual_rate;
561 }
562
563 int genclk_set_parent(struct clk *clk, struct clk *parent)
564 {
565 u32 control;
566
567 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
568 clk->name, parent->name, clk->parent->name);
569
570 control = pm_readl(GCCTRL(clk->index));
571
572 if (parent == &osc1 || parent == &pll1)
573 control |= PM_BIT(OSCSEL);
574 else if (parent == &osc0 || parent == &pll0)
575 control &= ~PM_BIT(OSCSEL);
576 else
577 return -EINVAL;
578
579 if (parent == &pll0 || parent == &pll1)
580 control |= PM_BIT(PLLSEL);
581 else
582 control &= ~PM_BIT(PLLSEL);
583
584 pm_writel(GCCTRL(clk->index), control);
585 clk->parent = parent;
586
587 return 0;
588 }
589
590 static void __init genclk_init_parent(struct clk *clk)
591 {
592 u32 control;
593 struct clk *parent;
594
595 BUG_ON(clk->index > 7);
596
597 control = pm_readl(GCCTRL(clk->index));
598 if (control & PM_BIT(OSCSEL))
599 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
600 else
601 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
602
603 clk->parent = parent;
604 }
605
606 static struct dw_dma_platform_data dw_dmac0_data = {
607 .nr_channels = 3,
608 };
609
610 static struct resource dw_dmac0_resource[] = {
611 PBMEM(0xff200000),
612 IRQ(2),
613 };
614 DEFINE_DEV_DATA(dw_dmac, 0);
615 DEV_CLK(hclk, dw_dmac0, hsb, 10);
616
617 /* --------------------------------------------------------------------
618 * System peripherals
619 * -------------------------------------------------------------------- */
620 static struct resource at32_pm0_resource[] = {
621 {
622 .start = 0xfff00000,
623 .end = 0xfff0007f,
624 .flags = IORESOURCE_MEM,
625 },
626 IRQ(20),
627 };
628
629 static struct resource at32ap700x_rtc0_resource[] = {
630 {
631 .start = 0xfff00080,
632 .end = 0xfff000af,
633 .flags = IORESOURCE_MEM,
634 },
635 IRQ(21),
636 };
637
638 static struct resource at32_wdt0_resource[] = {
639 {
640 .start = 0xfff000b0,
641 .end = 0xfff000cf,
642 .flags = IORESOURCE_MEM,
643 },
644 };
645
646 static struct resource at32_eic0_resource[] = {
647 {
648 .start = 0xfff00100,
649 .end = 0xfff0013f,
650 .flags = IORESOURCE_MEM,
651 },
652 IRQ(19),
653 };
654
655 DEFINE_DEV(at32_pm, 0);
656 DEFINE_DEV(at32ap700x_rtc, 0);
657 DEFINE_DEV(at32_wdt, 0);
658 DEFINE_DEV(at32_eic, 0);
659
660 /*
661 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
662 * is always running.
663 */
664 static struct clk at32_pm_pclk = {
665 .name = "pclk",
666 .dev = &at32_pm0_device.dev,
667 .parent = &pbb_clk,
668 .mode = pbb_clk_mode,
669 .get_rate = pbb_clk_get_rate,
670 .users = 1,
671 .index = 0,
672 };
673
674 static struct resource intc0_resource[] = {
675 PBMEM(0xfff00400),
676 };
677 struct platform_device at32_intc0_device = {
678 .name = "intc",
679 .id = 0,
680 .resource = intc0_resource,
681 .num_resources = ARRAY_SIZE(intc0_resource),
682 };
683 DEV_CLK(pclk, at32_intc0, pbb, 1);
684
685 static struct clk ebi_clk = {
686 .name = "ebi",
687 .parent = &hsb_clk,
688 .mode = hsb_clk_mode,
689 .get_rate = hsb_clk_get_rate,
690 .users = 1,
691 };
692 static struct clk hramc_clk = {
693 .name = "hramc",
694 .parent = &hsb_clk,
695 .mode = hsb_clk_mode,
696 .get_rate = hsb_clk_get_rate,
697 .users = 1,
698 .index = 3,
699 };
700 static struct clk sdramc_clk = {
701 .name = "sdramc_clk",
702 .parent = &pbb_clk,
703 .mode = pbb_clk_mode,
704 .get_rate = pbb_clk_get_rate,
705 .users = 1,
706 .index = 14,
707 };
708
709 static struct resource smc0_resource[] = {
710 PBMEM(0xfff03400),
711 };
712 DEFINE_DEV(smc, 0);
713 DEV_CLK(pclk, smc0, pbb, 13);
714 DEV_CLK(mck, smc0, hsb, 0);
715
716 static struct platform_device pdc_device = {
717 .name = "pdc",
718 .id = 0,
719 };
720 DEV_CLK(hclk, pdc, hsb, 4);
721 DEV_CLK(pclk, pdc, pba, 16);
722
723 static struct clk pico_clk = {
724 .name = "pico",
725 .parent = &cpu_clk,
726 .mode = cpu_clk_mode,
727 .get_rate = cpu_clk_get_rate,
728 .users = 1,
729 };
730
731 /* --------------------------------------------------------------------
732 * HMATRIX
733 * -------------------------------------------------------------------- */
734
735 struct clk at32_hmatrix_clk = {
736 .name = "hmatrix_clk",
737 .parent = &pbb_clk,
738 .mode = pbb_clk_mode,
739 .get_rate = pbb_clk_get_rate,
740 .index = 2,
741 .users = 1,
742 };
743
744 /*
745 * Set bits in the HMATRIX Special Function Register (SFR) used by the
746 * External Bus Interface (EBI). This can be used to enable special
747 * features like CompactFlash support, NAND Flash support, etc. on
748 * certain chipselects.
749 */
750 static inline void set_ebi_sfr_bits(u32 mask)
751 {
752 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
753 }
754
755 /* --------------------------------------------------------------------
756 * Timer/Counter (TC)
757 * -------------------------------------------------------------------- */
758
759 static struct resource at32_tcb0_resource[] = {
760 PBMEM(0xfff00c00),
761 IRQ(22),
762 };
763 static struct platform_device at32_tcb0_device = {
764 .name = "atmel_tcb",
765 .id = 0,
766 .resource = at32_tcb0_resource,
767 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
768 };
769 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
770
771 static struct resource at32_tcb1_resource[] = {
772 PBMEM(0xfff01000),
773 IRQ(23),
774 };
775 static struct platform_device at32_tcb1_device = {
776 .name = "atmel_tcb",
777 .id = 1,
778 .resource = at32_tcb1_resource,
779 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
780 };
781 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
782
783 /* --------------------------------------------------------------------
784 * PIO
785 * -------------------------------------------------------------------- */
786
787 static struct resource pio0_resource[] = {
788 PBMEM(0xffe02800),
789 IRQ(13),
790 };
791 DEFINE_DEV(pio, 0);
792 DEV_CLK(mck, pio0, pba, 10);
793
794 static struct resource pio1_resource[] = {
795 PBMEM(0xffe02c00),
796 IRQ(14),
797 };
798 DEFINE_DEV(pio, 1);
799 DEV_CLK(mck, pio1, pba, 11);
800
801 static struct resource pio2_resource[] = {
802 PBMEM(0xffe03000),
803 IRQ(15),
804 };
805 DEFINE_DEV(pio, 2);
806 DEV_CLK(mck, pio2, pba, 12);
807
808 static struct resource pio3_resource[] = {
809 PBMEM(0xffe03400),
810 IRQ(16),
811 };
812 DEFINE_DEV(pio, 3);
813 DEV_CLK(mck, pio3, pba, 13);
814
815 static struct resource pio4_resource[] = {
816 PBMEM(0xffe03800),
817 IRQ(17),
818 };
819 DEFINE_DEV(pio, 4);
820 DEV_CLK(mck, pio4, pba, 14);
821
822 static int __init system_device_init(void)
823 {
824 platform_device_register(&at32_pm0_device);
825 platform_device_register(&at32_intc0_device);
826 platform_device_register(&at32ap700x_rtc0_device);
827 platform_device_register(&at32_wdt0_device);
828 platform_device_register(&at32_eic0_device);
829 platform_device_register(&smc0_device);
830 platform_device_register(&pdc_device);
831 platform_device_register(&dw_dmac0_device);
832
833 platform_device_register(&at32_tcb0_device);
834 platform_device_register(&at32_tcb1_device);
835
836 platform_device_register(&pio0_device);
837 platform_device_register(&pio1_device);
838 platform_device_register(&pio2_device);
839 platform_device_register(&pio3_device);
840 platform_device_register(&pio4_device);
841
842 return 0;
843 }
844 core_initcall(system_device_init);
845
846 /* --------------------------------------------------------------------
847 * PSIF
848 * -------------------------------------------------------------------- */
849 static struct resource atmel_psif0_resource[] __initdata = {
850 {
851 .start = 0xffe03c00,
852 .end = 0xffe03cff,
853 .flags = IORESOURCE_MEM,
854 },
855 IRQ(18),
856 };
857 static struct clk atmel_psif0_pclk = {
858 .name = "pclk",
859 .parent = &pba_clk,
860 .mode = pba_clk_mode,
861 .get_rate = pba_clk_get_rate,
862 .index = 15,
863 };
864
865 static struct resource atmel_psif1_resource[] __initdata = {
866 {
867 .start = 0xffe03d00,
868 .end = 0xffe03dff,
869 .flags = IORESOURCE_MEM,
870 },
871 IRQ(18),
872 };
873 static struct clk atmel_psif1_pclk = {
874 .name = "pclk",
875 .parent = &pba_clk,
876 .mode = pba_clk_mode,
877 .get_rate = pba_clk_get_rate,
878 .index = 15,
879 };
880
881 struct platform_device *__init at32_add_device_psif(unsigned int id)
882 {
883 struct platform_device *pdev;
884 u32 pin_mask;
885
886 if (!(id == 0 || id == 1))
887 return NULL;
888
889 pdev = platform_device_alloc("atmel_psif", id);
890 if (!pdev)
891 return NULL;
892
893 switch (id) {
894 case 0:
895 pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */
896
897 if (platform_device_add_resources(pdev, atmel_psif0_resource,
898 ARRAY_SIZE(atmel_psif0_resource)))
899 goto err_add_resources;
900 atmel_psif0_pclk.dev = &pdev->dev;
901 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
902 break;
903 case 1:
904 pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */
905
906 if (platform_device_add_resources(pdev, atmel_psif1_resource,
907 ARRAY_SIZE(atmel_psif1_resource)))
908 goto err_add_resources;
909 atmel_psif1_pclk.dev = &pdev->dev;
910 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
911 break;
912 default:
913 return NULL;
914 }
915
916 platform_device_add(pdev);
917 return pdev;
918
919 err_add_resources:
920 platform_device_put(pdev);
921 return NULL;
922 }
923
924 /* --------------------------------------------------------------------
925 * USART
926 * -------------------------------------------------------------------- */
927
928 static struct atmel_uart_data atmel_usart0_data = {
929 .use_dma_tx = 1,
930 .use_dma_rx = 1,
931 };
932 static struct resource atmel_usart0_resource[] = {
933 PBMEM(0xffe00c00),
934 IRQ(6),
935 };
936 DEFINE_DEV_DATA(atmel_usart, 0);
937 DEV_CLK(usart, atmel_usart0, pba, 3);
938
939 static struct atmel_uart_data atmel_usart1_data = {
940 .use_dma_tx = 1,
941 .use_dma_rx = 1,
942 };
943 static struct resource atmel_usart1_resource[] = {
944 PBMEM(0xffe01000),
945 IRQ(7),
946 };
947 DEFINE_DEV_DATA(atmel_usart, 1);
948 DEV_CLK(usart, atmel_usart1, pba, 4);
949
950 static struct atmel_uart_data atmel_usart2_data = {
951 .use_dma_tx = 1,
952 .use_dma_rx = 1,
953 };
954 static struct resource atmel_usart2_resource[] = {
955 PBMEM(0xffe01400),
956 IRQ(8),
957 };
958 DEFINE_DEV_DATA(atmel_usart, 2);
959 DEV_CLK(usart, atmel_usart2, pba, 5);
960
961 static struct atmel_uart_data atmel_usart3_data = {
962 .use_dma_tx = 1,
963 .use_dma_rx = 1,
964 };
965 static struct resource atmel_usart3_resource[] = {
966 PBMEM(0xffe01800),
967 IRQ(9),
968 };
969 DEFINE_DEV_DATA(atmel_usart, 3);
970 DEV_CLK(usart, atmel_usart3, pba, 6);
971
972 static inline void configure_usart0_pins(int flags)
973 {
974 u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
975 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6);
976 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7);
977 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10);
978
979 select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
980 }
981
982 static inline void configure_usart1_pins(int flags)
983 {
984 u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
985 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19);
986 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20);
987 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16);
988
989 select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
990 }
991
992 static inline void configure_usart2_pins(int flags)
993 {
994 u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
995 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30);
996 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29);
997 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28);
998
999 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1000 }
1001
1002 static inline void configure_usart3_pins(int flags)
1003 {
1004 u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1005 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16);
1006 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15);
1007 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19);
1008
1009 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1010 }
1011
1012 static struct platform_device *__initdata at32_usarts[4];
1013
1014 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1015 {
1016 struct platform_device *pdev;
1017 struct atmel_uart_data *pdata;
1018
1019 switch (hw_id) {
1020 case 0:
1021 pdev = &atmel_usart0_device;
1022 configure_usart0_pins(flags);
1023 break;
1024 case 1:
1025 pdev = &atmel_usart1_device;
1026 configure_usart1_pins(flags);
1027 break;
1028 case 2:
1029 pdev = &atmel_usart2_device;
1030 configure_usart2_pins(flags);
1031 break;
1032 case 3:
1033 pdev = &atmel_usart3_device;
1034 configure_usart3_pins(flags);
1035 break;
1036 default:
1037 return;
1038 }
1039
1040 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1041 /* Addresses in the P4 segment are permanently mapped 1:1 */
1042 struct atmel_uart_data *data = pdev->dev.platform_data;
1043 data->regs = (void __iomem *)pdev->resource[0].start;
1044 }
1045
1046 pdev->id = line;
1047 pdata = pdev->dev.platform_data;
1048 pdata->num = line;
1049 at32_usarts[line] = pdev;
1050 }
1051
1052 struct platform_device *__init at32_add_device_usart(unsigned int id)
1053 {
1054 platform_device_register(at32_usarts[id]);
1055 return at32_usarts[id];
1056 }
1057
1058 struct platform_device *atmel_default_console_device;
1059
1060 void __init at32_setup_serial_console(unsigned int usart_id)
1061 {
1062 atmel_default_console_device = at32_usarts[usart_id];
1063 }
1064
1065 /* --------------------------------------------------------------------
1066 * Ethernet
1067 * -------------------------------------------------------------------- */
1068
1069 #ifdef CONFIG_CPU_AT32AP7000
1070 static struct macb_platform_data macb0_data;
1071 static struct resource macb0_resource[] = {
1072 PBMEM(0xfff01800),
1073 IRQ(25),
1074 };
1075 DEFINE_DEV_DATA(macb, 0);
1076 DEV_CLK(hclk, macb0, hsb, 8);
1077 DEV_CLK(pclk, macb0, pbb, 6);
1078
1079 static struct macb_platform_data macb1_data;
1080 static struct resource macb1_resource[] = {
1081 PBMEM(0xfff01c00),
1082 IRQ(26),
1083 };
1084 DEFINE_DEV_DATA(macb, 1);
1085 DEV_CLK(hclk, macb1, hsb, 9);
1086 DEV_CLK(pclk, macb1, pbb, 7);
1087
1088 struct platform_device *__init
1089 at32_add_device_eth(unsigned int id, struct macb_platform_data *data)
1090 {
1091 struct platform_device *pdev;
1092 u32 pin_mask;
1093
1094 switch (id) {
1095 case 0:
1096 pdev = &macb0_device;
1097
1098 pin_mask = (1 << 3); /* TXD0 */
1099 pin_mask |= (1 << 4); /* TXD1 */
1100 pin_mask |= (1 << 7); /* TXEN */
1101 pin_mask |= (1 << 8); /* TXCK */
1102 pin_mask |= (1 << 9); /* RXD0 */
1103 pin_mask |= (1 << 10); /* RXD1 */
1104 pin_mask |= (1 << 13); /* RXER */
1105 pin_mask |= (1 << 15); /* RXDV */
1106 pin_mask |= (1 << 16); /* MDC */
1107 pin_mask |= (1 << 17); /* MDIO */
1108
1109 if (!data->is_rmii) {
1110 pin_mask |= (1 << 0); /* COL */
1111 pin_mask |= (1 << 1); /* CRS */
1112 pin_mask |= (1 << 2); /* TXER */
1113 pin_mask |= (1 << 5); /* TXD2 */
1114 pin_mask |= (1 << 6); /* TXD3 */
1115 pin_mask |= (1 << 11); /* RXD2 */
1116 pin_mask |= (1 << 12); /* RXD3 */
1117 pin_mask |= (1 << 14); /* RXCK */
1118 #ifndef CONFIG_BOARD_MIMC200
1119 pin_mask |= (1 << 18); /* SPD */
1120 #endif
1121 }
1122
1123 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1124
1125 break;
1126
1127 case 1:
1128 pdev = &macb1_device;
1129
1130 pin_mask = (1 << 13); /* TXD0 */
1131 pin_mask |= (1 << 14); /* TXD1 */
1132 pin_mask |= (1 << 11); /* TXEN */
1133 pin_mask |= (1 << 12); /* TXCK */
1134 pin_mask |= (1 << 10); /* RXD0 */
1135 pin_mask |= (1 << 6); /* RXD1 */
1136 pin_mask |= (1 << 5); /* RXER */
1137 pin_mask |= (1 << 4); /* RXDV */
1138 pin_mask |= (1 << 3); /* MDC */
1139 pin_mask |= (1 << 2); /* MDIO */
1140
1141 #ifndef CONFIG_BOARD_MIMC200
1142 if (!data->is_rmii)
1143 pin_mask |= (1 << 15); /* SPD */
1144 #endif
1145
1146 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1147
1148 if (!data->is_rmii) {
1149 pin_mask = (1 << 19); /* COL */
1150 pin_mask |= (1 << 23); /* CRS */
1151 pin_mask |= (1 << 26); /* TXER */
1152 pin_mask |= (1 << 27); /* TXD2 */
1153 pin_mask |= (1 << 28); /* TXD3 */
1154 pin_mask |= (1 << 29); /* RXD2 */
1155 pin_mask |= (1 << 30); /* RXD3 */
1156 pin_mask |= (1 << 24); /* RXCK */
1157
1158 select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1159 }
1160 break;
1161
1162 default:
1163 return NULL;
1164 }
1165
1166 memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data));
1167 platform_device_register(pdev);
1168
1169 return pdev;
1170 }
1171 #endif
1172
1173 /* --------------------------------------------------------------------
1174 * SPI
1175 * -------------------------------------------------------------------- */
1176 static struct resource atmel_spi0_resource[] = {
1177 PBMEM(0xffe00000),
1178 IRQ(3),
1179 };
1180 DEFINE_DEV(atmel_spi, 0);
1181 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1182
1183 static struct resource atmel_spi1_resource[] = {
1184 PBMEM(0xffe00400),
1185 IRQ(4),
1186 };
1187 DEFINE_DEV(atmel_spi, 1);
1188 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1189
1190 void __init
1191 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1192 {
1193 /*
1194 * Manage the chipselects as GPIOs, normally using the same pins
1195 * the SPI controller expects; but boards can use other pins.
1196 */
1197 static u8 __initdata spi_pins[][4] = {
1198 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1199 GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1200 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1201 GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1202 };
1203 unsigned int pin, mode;
1204
1205 /* There are only 2 SPI controllers */
1206 if (bus_num > 1)
1207 return;
1208
1209 for (; n; n--, b++) {
1210 b->bus_num = bus_num;
1211 if (b->chip_select >= 4)
1212 continue;
1213 pin = (unsigned)b->controller_data;
1214 if (!pin) {
1215 pin = spi_pins[bus_num][b->chip_select];
1216 b->controller_data = (void *)pin;
1217 }
1218 mode = AT32_GPIOF_OUTPUT;
1219 if (!(b->mode & SPI_CS_HIGH))
1220 mode |= AT32_GPIOF_HIGH;
1221 at32_select_gpio(pin, mode);
1222 }
1223 }
1224
1225 struct platform_device *__init
1226 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1227 {
1228 struct platform_device *pdev;
1229 u32 pin_mask;
1230
1231 switch (id) {
1232 case 0:
1233 pdev = &atmel_spi0_device;
1234 pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */
1235
1236 /* pullup MISO so a level is always defined */
1237 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1238 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1239
1240 at32_spi_setup_slaves(0, b, n);
1241 break;
1242
1243 case 1:
1244 pdev = &atmel_spi1_device;
1245 pin_mask = (1 << 1) | (1 << 5); /* MOSI */
1246
1247 /* pullup MISO so a level is always defined */
1248 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1249 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1250
1251 at32_spi_setup_slaves(1, b, n);
1252 break;
1253
1254 default:
1255 return NULL;
1256 }
1257
1258 spi_register_board_info(b, n);
1259 platform_device_register(pdev);
1260 return pdev;
1261 }
1262
1263 /* --------------------------------------------------------------------
1264 * TWI
1265 * -------------------------------------------------------------------- */
1266 static struct resource atmel_twi0_resource[] __initdata = {
1267 PBMEM(0xffe00800),
1268 IRQ(5),
1269 };
1270 static struct clk atmel_twi0_pclk = {
1271 .name = "twi_pclk",
1272 .parent = &pba_clk,
1273 .mode = pba_clk_mode,
1274 .get_rate = pba_clk_get_rate,
1275 .index = 2,
1276 };
1277
1278 struct platform_device *__init at32_add_device_twi(unsigned int id,
1279 struct i2c_board_info *b,
1280 unsigned int n)
1281 {
1282 struct platform_device *pdev;
1283 u32 pin_mask;
1284
1285 if (id != 0)
1286 return NULL;
1287
1288 pdev = platform_device_alloc("atmel_twi", id);
1289 if (!pdev)
1290 return NULL;
1291
1292 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1293 ARRAY_SIZE(atmel_twi0_resource)))
1294 goto err_add_resources;
1295
1296 pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */
1297
1298 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1299
1300 atmel_twi0_pclk.dev = &pdev->dev;
1301
1302 if (b)
1303 i2c_register_board_info(id, b, n);
1304
1305 platform_device_add(pdev);
1306 return pdev;
1307
1308 err_add_resources:
1309 platform_device_put(pdev);
1310 return NULL;
1311 }
1312
1313 /* --------------------------------------------------------------------
1314 * MMC
1315 * -------------------------------------------------------------------- */
1316 static struct resource atmel_mci0_resource[] __initdata = {
1317 PBMEM(0xfff02400),
1318 IRQ(28),
1319 };
1320 static struct clk atmel_mci0_pclk = {
1321 .name = "mci_clk",
1322 .parent = &pbb_clk,
1323 .mode = pbb_clk_mode,
1324 .get_rate = pbb_clk_get_rate,
1325 .index = 9,
1326 };
1327
1328 struct platform_device *__init
1329 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1330 {
1331 struct platform_device *pdev;
1332 struct mci_dma_data *slave;
1333 u32 pioa_mask;
1334 u32 piob_mask;
1335
1336 if (id != 0 || !data)
1337 return NULL;
1338
1339 /* Must have at least one usable slot */
1340 if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1341 return NULL;
1342
1343 pdev = platform_device_alloc("atmel_mci", id);
1344 if (!pdev)
1345 goto fail;
1346
1347 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1348 ARRAY_SIZE(atmel_mci0_resource)))
1349 goto fail;
1350
1351 slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
1352 if (!slave)
1353 goto fail;
1354
1355 slave->sdata.dma_dev = &dw_dmac0_device.dev;
1356 slave->sdata.reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
1357 slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)
1358 | DWC_CFGH_DST_PER(1));
1359 slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1360 | DWC_CFGL_HS_SRC_POL);
1361
1362 data->dma_slave = slave;
1363
1364 if (platform_device_add_data(pdev, data,
1365 sizeof(struct mci_platform_data)))
1366 goto fail_free;
1367
1368 /* CLK line is common to both slots */
1369 pioa_mask = 1 << 10;
1370
1371 switch (data->slot[0].bus_width) {
1372 case 4:
1373 pioa_mask |= 1 << 13; /* DATA1 */
1374 pioa_mask |= 1 << 14; /* DATA2 */
1375 pioa_mask |= 1 << 15; /* DATA3 */
1376 /* fall through */
1377 case 1:
1378 pioa_mask |= 1 << 11; /* CMD */
1379 pioa_mask |= 1 << 12; /* DATA0 */
1380
1381 if (gpio_is_valid(data->slot[0].detect_pin))
1382 at32_select_gpio(data->slot[0].detect_pin, 0);
1383 if (gpio_is_valid(data->slot[0].wp_pin))
1384 at32_select_gpio(data->slot[0].wp_pin, 0);
1385 break;
1386 case 0:
1387 /* Slot is unused */
1388 break;
1389 default:
1390 goto fail_free;
1391 }
1392
1393 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1394 piob_mask = 0;
1395
1396 switch (data->slot[1].bus_width) {
1397 case 4:
1398 piob_mask |= 1 << 8; /* DATA1 */
1399 piob_mask |= 1 << 9; /* DATA2 */
1400 piob_mask |= 1 << 10; /* DATA3 */
1401 /* fall through */
1402 case 1:
1403 piob_mask |= 1 << 6; /* CMD */
1404 piob_mask |= 1 << 7; /* DATA0 */
1405 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1406
1407 if (gpio_is_valid(data->slot[1].detect_pin))
1408 at32_select_gpio(data->slot[1].detect_pin, 0);
1409 if (gpio_is_valid(data->slot[1].wp_pin))
1410 at32_select_gpio(data->slot[1].wp_pin, 0);
1411 break;
1412 case 0:
1413 /* Slot is unused */
1414 break;
1415 default:
1416 if (!data->slot[0].bus_width)
1417 goto fail_free;
1418
1419 data->slot[1].bus_width = 0;
1420 break;
1421 }
1422
1423 atmel_mci0_pclk.dev = &pdev->dev;
1424
1425 platform_device_add(pdev);
1426 return pdev;
1427
1428 fail_free:
1429 kfree(slave);
1430 fail:
1431 data->dma_slave = NULL;
1432 platform_device_put(pdev);
1433 return NULL;
1434 }
1435
1436 /* --------------------------------------------------------------------
1437 * LCDC
1438 * -------------------------------------------------------------------- */
1439 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1440 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1441 static struct resource atmel_lcdfb0_resource[] = {
1442 {
1443 .start = 0xff000000,
1444 .end = 0xff000fff,
1445 .flags = IORESOURCE_MEM,
1446 },
1447 IRQ(1),
1448 {
1449 /* Placeholder for pre-allocated fb memory */
1450 .start = 0x00000000,
1451 .end = 0x00000000,
1452 .flags = 0,
1453 },
1454 };
1455 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1456 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1457 static struct clk atmel_lcdfb0_pixclk = {
1458 .name = "lcdc_clk",
1459 .dev = &atmel_lcdfb0_device.dev,
1460 .mode = genclk_mode,
1461 .get_rate = genclk_get_rate,
1462 .set_rate = genclk_set_rate,
1463 .set_parent = genclk_set_parent,
1464 .index = 7,
1465 };
1466
1467 struct platform_device *__init
1468 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1469 unsigned long fbmem_start, unsigned long fbmem_len,
1470 u64 pin_mask)
1471 {
1472 struct platform_device *pdev;
1473 struct atmel_lcdfb_info *info;
1474 struct fb_monspecs *monspecs;
1475 struct fb_videomode *modedb;
1476 unsigned int modedb_size;
1477 u32 portc_mask, portd_mask, porte_mask;
1478
1479 /*
1480 * Do a deep copy of the fb data, monspecs and modedb. Make
1481 * sure all allocations are done before setting up the
1482 * portmux.
1483 */
1484 monspecs = kmemdup(data->default_monspecs,
1485 sizeof(struct fb_monspecs), GFP_KERNEL);
1486 if (!monspecs)
1487 return NULL;
1488
1489 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1490 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1491 if (!modedb)
1492 goto err_dup_modedb;
1493 monspecs->modedb = modedb;
1494
1495 switch (id) {
1496 case 0:
1497 pdev = &atmel_lcdfb0_device;
1498
1499 if (pin_mask == 0ULL)
1500 /* Default to "full" lcdc control signals and 24bit */
1501 pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1502
1503 /* LCDC on port C */
1504 portc_mask = pin_mask & 0xfff80000;
1505 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1506
1507 /* LCDC on port D */
1508 portd_mask = pin_mask & 0x0003ffff;
1509 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1510
1511 /* LCDC on port E */
1512 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1513 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1514
1515 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1516 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1517 break;
1518
1519 default:
1520 goto err_invalid_id;
1521 }
1522
1523 if (fbmem_len) {
1524 pdev->resource[2].start = fbmem_start;
1525 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1526 pdev->resource[2].flags = IORESOURCE_MEM;
1527 }
1528
1529 info = pdev->dev.platform_data;
1530 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1531 info->default_monspecs = monspecs;
1532
1533 platform_device_register(pdev);
1534 return pdev;
1535
1536 err_invalid_id:
1537 kfree(modedb);
1538 err_dup_modedb:
1539 kfree(monspecs);
1540 return NULL;
1541 }
1542 #endif
1543
1544 /* --------------------------------------------------------------------
1545 * PWM
1546 * -------------------------------------------------------------------- */
1547 static struct resource atmel_pwm0_resource[] __initdata = {
1548 PBMEM(0xfff01400),
1549 IRQ(24),
1550 };
1551 static struct clk atmel_pwm0_mck = {
1552 .name = "pwm_clk",
1553 .parent = &pbb_clk,
1554 .mode = pbb_clk_mode,
1555 .get_rate = pbb_clk_get_rate,
1556 .index = 5,
1557 };
1558
1559 struct platform_device *__init at32_add_device_pwm(u32 mask)
1560 {
1561 struct platform_device *pdev;
1562 u32 pin_mask;
1563
1564 if (!mask)
1565 return NULL;
1566
1567 pdev = platform_device_alloc("atmel_pwm", 0);
1568 if (!pdev)
1569 return NULL;
1570
1571 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1572 ARRAY_SIZE(atmel_pwm0_resource)))
1573 goto out_free_pdev;
1574
1575 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1576 goto out_free_pdev;
1577
1578 pin_mask = 0;
1579 if (mask & (1 << 0))
1580 pin_mask |= (1 << 28);
1581 if (mask & (1 << 1))
1582 pin_mask |= (1 << 29);
1583 if (pin_mask > 0)
1584 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1585
1586 pin_mask = 0;
1587 if (mask & (1 << 2))
1588 pin_mask |= (1 << 21);
1589 if (mask & (1 << 3))
1590 pin_mask |= (1 << 22);
1591 if (pin_mask > 0)
1592 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1593
1594 atmel_pwm0_mck.dev = &pdev->dev;
1595
1596 platform_device_add(pdev);
1597
1598 return pdev;
1599
1600 out_free_pdev:
1601 platform_device_put(pdev);
1602 return NULL;
1603 }
1604
1605 /* --------------------------------------------------------------------
1606 * SSC
1607 * -------------------------------------------------------------------- */
1608 static struct resource ssc0_resource[] = {
1609 PBMEM(0xffe01c00),
1610 IRQ(10),
1611 };
1612 DEFINE_DEV(ssc, 0);
1613 DEV_CLK(pclk, ssc0, pba, 7);
1614
1615 static struct resource ssc1_resource[] = {
1616 PBMEM(0xffe02000),
1617 IRQ(11),
1618 };
1619 DEFINE_DEV(ssc, 1);
1620 DEV_CLK(pclk, ssc1, pba, 8);
1621
1622 static struct resource ssc2_resource[] = {
1623 PBMEM(0xffe02400),
1624 IRQ(12),
1625 };
1626 DEFINE_DEV(ssc, 2);
1627 DEV_CLK(pclk, ssc2, pba, 9);
1628
1629 struct platform_device *__init
1630 at32_add_device_ssc(unsigned int id, unsigned int flags)
1631 {
1632 struct platform_device *pdev;
1633 u32 pin_mask = 0;
1634
1635 switch (id) {
1636 case 0:
1637 pdev = &ssc0_device;
1638 if (flags & ATMEL_SSC_RF)
1639 pin_mask |= (1 << 21); /* RF */
1640 if (flags & ATMEL_SSC_RK)
1641 pin_mask |= (1 << 22); /* RK */
1642 if (flags & ATMEL_SSC_TK)
1643 pin_mask |= (1 << 23); /* TK */
1644 if (flags & ATMEL_SSC_TF)
1645 pin_mask |= (1 << 24); /* TF */
1646 if (flags & ATMEL_SSC_TD)
1647 pin_mask |= (1 << 25); /* TD */
1648 if (flags & ATMEL_SSC_RD)
1649 pin_mask |= (1 << 26); /* RD */
1650
1651 if (pin_mask > 0)
1652 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1653
1654 break;
1655 case 1:
1656 pdev = &ssc1_device;
1657 if (flags & ATMEL_SSC_RF)
1658 pin_mask |= (1 << 0); /* RF */
1659 if (flags & ATMEL_SSC_RK)
1660 pin_mask |= (1 << 1); /* RK */
1661 if (flags & ATMEL_SSC_TK)
1662 pin_mask |= (1 << 2); /* TK */
1663 if (flags & ATMEL_SSC_TF)
1664 pin_mask |= (1 << 3); /* TF */
1665 if (flags & ATMEL_SSC_TD)
1666 pin_mask |= (1 << 4); /* TD */
1667 if (flags & ATMEL_SSC_RD)
1668 pin_mask |= (1 << 5); /* RD */
1669
1670 if (pin_mask > 0)
1671 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1672
1673 break;
1674 case 2:
1675 pdev = &ssc2_device;
1676 if (flags & ATMEL_SSC_TD)
1677 pin_mask |= (1 << 13); /* TD */
1678 if (flags & ATMEL_SSC_RD)
1679 pin_mask |= (1 << 14); /* RD */
1680 if (flags & ATMEL_SSC_TK)
1681 pin_mask |= (1 << 15); /* TK */
1682 if (flags & ATMEL_SSC_TF)
1683 pin_mask |= (1 << 16); /* TF */
1684 if (flags & ATMEL_SSC_RF)
1685 pin_mask |= (1 << 17); /* RF */
1686 if (flags & ATMEL_SSC_RK)
1687 pin_mask |= (1 << 18); /* RK */
1688
1689 if (pin_mask > 0)
1690 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1691
1692 break;
1693 default:
1694 return NULL;
1695 }
1696
1697 platform_device_register(pdev);
1698 return pdev;
1699 }
1700
1701 /* --------------------------------------------------------------------
1702 * USB Device Controller
1703 * -------------------------------------------------------------------- */
1704 static struct resource usba0_resource[] __initdata = {
1705 {
1706 .start = 0xff300000,
1707 .end = 0xff3fffff,
1708 .flags = IORESOURCE_MEM,
1709 }, {
1710 .start = 0xfff03000,
1711 .end = 0xfff033ff,
1712 .flags = IORESOURCE_MEM,
1713 },
1714 IRQ(31),
1715 };
1716 static struct clk usba0_pclk = {
1717 .name = "pclk",
1718 .parent = &pbb_clk,
1719 .mode = pbb_clk_mode,
1720 .get_rate = pbb_clk_get_rate,
1721 .index = 12,
1722 };
1723 static struct clk usba0_hclk = {
1724 .name = "hclk",
1725 .parent = &hsb_clk,
1726 .mode = hsb_clk_mode,
1727 .get_rate = hsb_clk_get_rate,
1728 .index = 6,
1729 };
1730
1731 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1732 [idx] = { \
1733 .name = nam, \
1734 .index = idx, \
1735 .fifo_size = maxpkt, \
1736 .nr_banks = maxbk, \
1737 .can_dma = dma, \
1738 .can_isoc = isoc, \
1739 }
1740
1741 static struct usba_ep_data at32_usba_ep[] __initdata = {
1742 EP("ep0", 0, 64, 1, 0, 0),
1743 EP("ep1", 1, 512, 2, 1, 1),
1744 EP("ep2", 2, 512, 2, 1, 1),
1745 EP("ep3-int", 3, 64, 3, 1, 0),
1746 EP("ep4-int", 4, 64, 3, 1, 0),
1747 EP("ep5", 5, 1024, 3, 1, 1),
1748 EP("ep6", 6, 1024, 3, 1, 1),
1749 };
1750
1751 #undef EP
1752
1753 struct platform_device *__init
1754 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1755 {
1756 /*
1757 * pdata doesn't have room for any endpoints, so we need to
1758 * append room for the ones we need right after it.
1759 */
1760 struct {
1761 struct usba_platform_data pdata;
1762 struct usba_ep_data ep[7];
1763 } usba_data;
1764 struct platform_device *pdev;
1765
1766 if (id != 0)
1767 return NULL;
1768
1769 pdev = platform_device_alloc("atmel_usba_udc", 0);
1770 if (!pdev)
1771 return NULL;
1772
1773 if (platform_device_add_resources(pdev, usba0_resource,
1774 ARRAY_SIZE(usba0_resource)))
1775 goto out_free_pdev;
1776
1777 if (data) {
1778 usba_data.pdata.vbus_pin = data->vbus_pin;
1779 usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
1780 } else {
1781 usba_data.pdata.vbus_pin = -EINVAL;
1782 usba_data.pdata.vbus_pin_inverted = -EINVAL;
1783 }
1784
1785 data = &usba_data.pdata;
1786 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1787 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1788
1789 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1790 goto out_free_pdev;
1791
1792 if (gpio_is_valid(data->vbus_pin))
1793 at32_select_gpio(data->vbus_pin, 0);
1794
1795 usba0_pclk.dev = &pdev->dev;
1796 usba0_hclk.dev = &pdev->dev;
1797
1798 platform_device_add(pdev);
1799
1800 return pdev;
1801
1802 out_free_pdev:
1803 platform_device_put(pdev);
1804 return NULL;
1805 }
1806
1807 /* --------------------------------------------------------------------
1808 * IDE / CompactFlash
1809 * -------------------------------------------------------------------- */
1810 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1811 static struct resource at32_smc_cs4_resource[] __initdata = {
1812 {
1813 .start = 0x04000000,
1814 .end = 0x07ffffff,
1815 .flags = IORESOURCE_MEM,
1816 },
1817 IRQ(~0UL), /* Magic IRQ will be overridden */
1818 };
1819 static struct resource at32_smc_cs5_resource[] __initdata = {
1820 {
1821 .start = 0x20000000,
1822 .end = 0x23ffffff,
1823 .flags = IORESOURCE_MEM,
1824 },
1825 IRQ(~0UL), /* Magic IRQ will be overridden */
1826 };
1827
1828 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1829 unsigned int cs, unsigned int extint)
1830 {
1831 static unsigned int extint_pin_map[4] __initdata = {
1832 (1 << 25),
1833 (1 << 26),
1834 (1 << 27),
1835 (1 << 28),
1836 };
1837 static bool common_pins_initialized __initdata = false;
1838 unsigned int extint_pin;
1839 int ret;
1840 u32 pin_mask;
1841
1842 if (extint >= ARRAY_SIZE(extint_pin_map))
1843 return -EINVAL;
1844 extint_pin = extint_pin_map[extint];
1845
1846 switch (cs) {
1847 case 4:
1848 ret = platform_device_add_resources(pdev,
1849 at32_smc_cs4_resource,
1850 ARRAY_SIZE(at32_smc_cs4_resource));
1851 if (ret)
1852 return ret;
1853
1854 /* NCS4 -> OE_N */
1855 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1856 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1857 break;
1858 case 5:
1859 ret = platform_device_add_resources(pdev,
1860 at32_smc_cs5_resource,
1861 ARRAY_SIZE(at32_smc_cs5_resource));
1862 if (ret)
1863 return ret;
1864
1865 /* NCS5 -> OE_N */
1866 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1867 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1868 break;
1869 default:
1870 return -EINVAL;
1871 }
1872
1873 if (!common_pins_initialized) {
1874 pin_mask = (1 << 19); /* CFCE1 -> CS0_N */
1875 pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */
1876 pin_mask |= (1 << 23); /* CFRNW -> DIR */
1877 pin_mask |= (1 << 24); /* NWAIT <- IORDY */
1878
1879 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1880
1881 common_pins_initialized = true;
1882 }
1883
1884 select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1885
1886 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1887 pdev->resource[1].end = pdev->resource[1].start;
1888
1889 return 0;
1890 }
1891
1892 struct platform_device *__init
1893 at32_add_device_ide(unsigned int id, unsigned int extint,
1894 struct ide_platform_data *data)
1895 {
1896 struct platform_device *pdev;
1897
1898 pdev = platform_device_alloc("at32_ide", id);
1899 if (!pdev)
1900 goto fail;
1901
1902 if (platform_device_add_data(pdev, data,
1903 sizeof(struct ide_platform_data)))
1904 goto fail;
1905
1906 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1907 goto fail;
1908
1909 platform_device_add(pdev);
1910 return pdev;
1911
1912 fail:
1913 platform_device_put(pdev);
1914 return NULL;
1915 }
1916
1917 struct platform_device *__init
1918 at32_add_device_cf(unsigned int id, unsigned int extint,
1919 struct cf_platform_data *data)
1920 {
1921 struct platform_device *pdev;
1922
1923 pdev = platform_device_alloc("at32_cf", id);
1924 if (!pdev)
1925 goto fail;
1926
1927 if (platform_device_add_data(pdev, data,
1928 sizeof(struct cf_platform_data)))
1929 goto fail;
1930
1931 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1932 goto fail;
1933
1934 if (gpio_is_valid(data->detect_pin))
1935 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1936 if (gpio_is_valid(data->reset_pin))
1937 at32_select_gpio(data->reset_pin, 0);
1938 if (gpio_is_valid(data->vcc_pin))
1939 at32_select_gpio(data->vcc_pin, 0);
1940 /* READY is used as extint, so we can't select it as gpio */
1941
1942 platform_device_add(pdev);
1943 return pdev;
1944
1945 fail:
1946 platform_device_put(pdev);
1947 return NULL;
1948 }
1949 #endif
1950
1951 /* --------------------------------------------------------------------
1952 * NAND Flash / SmartMedia
1953 * -------------------------------------------------------------------- */
1954 static struct resource smc_cs3_resource[] __initdata = {
1955 {
1956 .start = 0x0c000000,
1957 .end = 0x0fffffff,
1958 .flags = IORESOURCE_MEM,
1959 }, {
1960 .start = 0xfff03c00,
1961 .end = 0xfff03fff,
1962 .flags = IORESOURCE_MEM,
1963 },
1964 };
1965
1966 struct platform_device *__init
1967 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1968 {
1969 struct platform_device *pdev;
1970
1971 if (id != 0 || !data)
1972 return NULL;
1973
1974 pdev = platform_device_alloc("atmel_nand", id);
1975 if (!pdev)
1976 goto fail;
1977
1978 if (platform_device_add_resources(pdev, smc_cs3_resource,
1979 ARRAY_SIZE(smc_cs3_resource)))
1980 goto fail;
1981
1982 if (platform_device_add_data(pdev, data,
1983 sizeof(struct atmel_nand_data)))
1984 goto fail;
1985
1986 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1987 if (data->enable_pin)
1988 at32_select_gpio(data->enable_pin,
1989 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1990 if (data->rdy_pin)
1991 at32_select_gpio(data->rdy_pin, 0);
1992 if (data->det_pin)
1993 at32_select_gpio(data->det_pin, 0);
1994
1995 platform_device_add(pdev);
1996 return pdev;
1997
1998 fail:
1999 platform_device_put(pdev);
2000 return NULL;
2001 }
2002
2003 /* --------------------------------------------------------------------
2004 * AC97C
2005 * -------------------------------------------------------------------- */
2006 static struct resource atmel_ac97c0_resource[] __initdata = {
2007 PBMEM(0xfff02800),
2008 IRQ(29),
2009 };
2010 static struct clk atmel_ac97c0_pclk = {
2011 .name = "pclk",
2012 .parent = &pbb_clk,
2013 .mode = pbb_clk_mode,
2014 .get_rate = pbb_clk_get_rate,
2015 .index = 10,
2016 };
2017
2018 struct platform_device *__init
2019 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2020 unsigned int flags)
2021 {
2022 struct platform_device *pdev;
2023 struct dw_dma_slave *rx_dws;
2024 struct dw_dma_slave *tx_dws;
2025 struct ac97c_platform_data _data;
2026 u32 pin_mask;
2027
2028 if (id != 0)
2029 return NULL;
2030
2031 pdev = platform_device_alloc("atmel_ac97c", id);
2032 if (!pdev)
2033 return NULL;
2034
2035 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2036 ARRAY_SIZE(atmel_ac97c0_resource)))
2037 goto out_free_resources;
2038
2039 if (!data) {
2040 data = &_data;
2041 memset(data, 0, sizeof(struct ac97c_platform_data));
2042 data->reset_pin = -ENODEV;
2043 }
2044
2045 rx_dws = &data->rx_dws;
2046 tx_dws = &data->tx_dws;
2047
2048 /* Check if DMA slave interface for capture should be configured. */
2049 if (flags & AC97C_CAPTURE) {
2050 rx_dws->dma_dev = &dw_dmac0_device.dev;
2051 rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2052 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
2053 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2054 rx_dws->src_master = 0;
2055 rx_dws->dst_master = 1;
2056 rx_dws->src_msize = DW_DMA_MSIZE_1;
2057 rx_dws->dst_msize = DW_DMA_MSIZE_1;
2058 rx_dws->fc = DW_DMA_FC_D_P2M;
2059 }
2060
2061 /* Check if DMA slave interface for playback should be configured. */
2062 if (flags & AC97C_PLAYBACK) {
2063 tx_dws->dma_dev = &dw_dmac0_device.dev;
2064 tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2065 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
2066 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2067 tx_dws->src_master = 0;
2068 tx_dws->dst_master = 1;
2069 tx_dws->src_msize = DW_DMA_MSIZE_1;
2070 tx_dws->dst_msize = DW_DMA_MSIZE_1;
2071 tx_dws->fc = DW_DMA_FC_D_M2P;
2072 }
2073
2074 if (platform_device_add_data(pdev, data,
2075 sizeof(struct ac97c_platform_data)))
2076 goto out_free_resources;
2077
2078 /* SDO | SYNC | SCLK | SDI */
2079 pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2080
2081 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2082
2083 if (gpio_is_valid(data->reset_pin))
2084 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2085 | AT32_GPIOF_HIGH);
2086
2087 atmel_ac97c0_pclk.dev = &pdev->dev;
2088
2089 platform_device_add(pdev);
2090 return pdev;
2091
2092 out_free_resources:
2093 platform_device_put(pdev);
2094 return NULL;
2095 }
2096
2097 /* --------------------------------------------------------------------
2098 * ABDAC
2099 * -------------------------------------------------------------------- */
2100 static struct resource abdac0_resource[] __initdata = {
2101 PBMEM(0xfff02000),
2102 IRQ(27),
2103 };
2104 static struct clk abdac0_pclk = {
2105 .name = "pclk",
2106 .parent = &pbb_clk,
2107 .mode = pbb_clk_mode,
2108 .get_rate = pbb_clk_get_rate,
2109 .index = 8,
2110 };
2111 static struct clk abdac0_sample_clk = {
2112 .name = "sample_clk",
2113 .mode = genclk_mode,
2114 .get_rate = genclk_get_rate,
2115 .set_rate = genclk_set_rate,
2116 .set_parent = genclk_set_parent,
2117 .index = 6,
2118 };
2119
2120 struct platform_device *__init
2121 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2122 {
2123 struct platform_device *pdev;
2124 struct dw_dma_slave *dws;
2125 u32 pin_mask;
2126
2127 if (id != 0 || !data)
2128 return NULL;
2129
2130 pdev = platform_device_alloc("atmel_abdac", id);
2131 if (!pdev)
2132 return NULL;
2133
2134 if (platform_device_add_resources(pdev, abdac0_resource,
2135 ARRAY_SIZE(abdac0_resource)))
2136 goto out_free_resources;
2137
2138 dws = &data->dws;
2139
2140 dws->dma_dev = &dw_dmac0_device.dev;
2141 dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
2142 dws->cfg_hi = DWC_CFGH_DST_PER(2);
2143 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2144 dws->src_master = 0;
2145 dws->dst_master = 1;
2146 dws->src_msize = DW_DMA_MSIZE_1;
2147 dws->dst_msize = DW_DMA_MSIZE_1;
2148 dws->fc = DW_DMA_FC_D_M2P;
2149
2150 if (platform_device_add_data(pdev, data,
2151 sizeof(struct atmel_abdac_pdata)))
2152 goto out_free_resources;
2153
2154 pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
2155 pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
2156
2157 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2158
2159 abdac0_pclk.dev = &pdev->dev;
2160 abdac0_sample_clk.dev = &pdev->dev;
2161
2162 platform_device_add(pdev);
2163 return pdev;
2164
2165 out_free_resources:
2166 platform_device_put(pdev);
2167 return NULL;
2168 }
2169
2170 /* --------------------------------------------------------------------
2171 * GCLK
2172 * -------------------------------------------------------------------- */
2173 static struct clk gclk0 = {
2174 .name = "gclk0",
2175 .mode = genclk_mode,
2176 .get_rate = genclk_get_rate,
2177 .set_rate = genclk_set_rate,
2178 .set_parent = genclk_set_parent,
2179 .index = 0,
2180 };
2181 static struct clk gclk1 = {
2182 .name = "gclk1",
2183 .mode = genclk_mode,
2184 .get_rate = genclk_get_rate,
2185 .set_rate = genclk_set_rate,
2186 .set_parent = genclk_set_parent,
2187 .index = 1,
2188 };
2189 static struct clk gclk2 = {
2190 .name = "gclk2",
2191 .mode = genclk_mode,
2192 .get_rate = genclk_get_rate,
2193 .set_rate = genclk_set_rate,
2194 .set_parent = genclk_set_parent,
2195 .index = 2,
2196 };
2197 static struct clk gclk3 = {
2198 .name = "gclk3",
2199 .mode = genclk_mode,
2200 .get_rate = genclk_get_rate,
2201 .set_rate = genclk_set_rate,
2202 .set_parent = genclk_set_parent,
2203 .index = 3,
2204 };
2205 static struct clk gclk4 = {
2206 .name = "gclk4",
2207 .mode = genclk_mode,
2208 .get_rate = genclk_get_rate,
2209 .set_rate = genclk_set_rate,
2210 .set_parent = genclk_set_parent,
2211 .index = 4,
2212 };
2213
2214 static __initdata struct clk *init_clocks[] = {
2215 &osc32k,
2216 &osc0,
2217 &osc1,
2218 &pll0,
2219 &pll1,
2220 &cpu_clk,
2221 &hsb_clk,
2222 &pba_clk,
2223 &pbb_clk,
2224 &at32_pm_pclk,
2225 &at32_intc0_pclk,
2226 &at32_hmatrix_clk,
2227 &ebi_clk,
2228 &hramc_clk,
2229 &sdramc_clk,
2230 &smc0_pclk,
2231 &smc0_mck,
2232 &pdc_hclk,
2233 &pdc_pclk,
2234 &dw_dmac0_hclk,
2235 &pico_clk,
2236 &pio0_mck,
2237 &pio1_mck,
2238 &pio2_mck,
2239 &pio3_mck,
2240 &pio4_mck,
2241 &at32_tcb0_t0_clk,
2242 &at32_tcb1_t0_clk,
2243 &atmel_psif0_pclk,
2244 &atmel_psif1_pclk,
2245 &atmel_usart0_usart,
2246 &atmel_usart1_usart,
2247 &atmel_usart2_usart,
2248 &atmel_usart3_usart,
2249 &atmel_pwm0_mck,
2250 #if defined(CONFIG_CPU_AT32AP7000)
2251 &macb0_hclk,
2252 &macb0_pclk,
2253 &macb1_hclk,
2254 &macb1_pclk,
2255 #endif
2256 &atmel_spi0_spi_clk,
2257 &atmel_spi1_spi_clk,
2258 &atmel_twi0_pclk,
2259 &atmel_mci0_pclk,
2260 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2261 &atmel_lcdfb0_hck1,
2262 &atmel_lcdfb0_pixclk,
2263 #endif
2264 &ssc0_pclk,
2265 &ssc1_pclk,
2266 &ssc2_pclk,
2267 &usba0_hclk,
2268 &usba0_pclk,
2269 &atmel_ac97c0_pclk,
2270 &abdac0_pclk,
2271 &abdac0_sample_clk,
2272 &gclk0,
2273 &gclk1,
2274 &gclk2,
2275 &gclk3,
2276 &gclk4,
2277 };
2278
2279 void __init setup_platform(void)
2280 {
2281 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2282 int i;
2283
2284 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2285 main_clock = &pll0;
2286 cpu_clk.parent = &pll0;
2287 } else {
2288 main_clock = &osc0;
2289 cpu_clk.parent = &osc0;
2290 }
2291
2292 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2293 pll0.parent = &osc1;
2294 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2295 pll1.parent = &osc1;
2296
2297 genclk_init_parent(&gclk0);
2298 genclk_init_parent(&gclk1);
2299 genclk_init_parent(&gclk2);
2300 genclk_init_parent(&gclk3);
2301 genclk_init_parent(&gclk4);
2302 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2303 genclk_init_parent(&atmel_lcdfb0_pixclk);
2304 #endif
2305 genclk_init_parent(&abdac0_sample_clk);
2306
2307 /*
2308 * Build initial dynamic clock list by registering all clocks
2309 * from the array.
2310 * At the same time, turn on all clocks that have at least one
2311 * user already, and turn off everything else. We only do this
2312 * for module clocks, and even though it isn't particularly
2313 * pretty to check the address of the mode function, it should
2314 * do the trick...
2315 */
2316 for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2317 struct clk *clk = init_clocks[i];
2318
2319 /* first, register clock */
2320 at32_clk_register(clk);
2321
2322 if (clk->users == 0)
2323 continue;
2324
2325 if (clk->mode == &cpu_clk_mode)
2326 cpu_mask |= 1 << clk->index;
2327 else if (clk->mode == &hsb_clk_mode)
2328 hsb_mask |= 1 << clk->index;
2329 else if (clk->mode == &pba_clk_mode)
2330 pba_mask |= 1 << clk->index;
2331 else if (clk->mode == &pbb_clk_mode)
2332 pbb_mask |= 1 << clk->index;
2333 }
2334
2335 pm_writel(CPU_MASK, cpu_mask);
2336 pm_writel(HSB_MASK, hsb_mask);
2337 pm_writel(PBA_MASK, pba_mask);
2338 pm_writel(PBB_MASK, pbb_mask);
2339
2340 /* Initialize the port muxes */
2341 at32_init_pio(&pio0_device);
2342 at32_init_pio(&pio1_device);
2343 at32_init_pio(&pio2_device);
2344 at32_init_pio(&pio3_device);
2345 at32_init_pio(&pio4_device);
2346 }
2347
2348 struct gen_pool *sram_pool;
2349
2350 static int __init sram_init(void)
2351 {
2352 struct gen_pool *pool;
2353
2354 /* 1KiB granularity */
2355 pool = gen_pool_create(10, -1);
2356 if (!pool)
2357 goto fail;
2358
2359 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2360 goto err_pool_add;
2361
2362 sram_pool = pool;
2363 return 0;
2364
2365 err_pool_add:
2366 gen_pool_destroy(pool);
2367 fail:
2368 pr_err("Failed to create SRAM pool\n");
2369 return -ENOMEM;
2370 }
2371 core_initcall(sram_init);