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Linux 2.6.33
[pohmelfs.git] / arch / arm / mach-davinci / dma.c
blob648fbb760ae1d63c74e700eae260629046add8b1
1 /*
2 * EDMA3 support for DaVinci
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/interrupt.h>
24 #include <linux/platform_device.h>
25 #include <linux/io.h>
26
27 #include <mach/edma.h>
28
29 /* Offsets matching "struct edmacc_param" */
30 #define PARM_OPT 0x00
31 #define PARM_SRC 0x04
32 #define PARM_A_B_CNT 0x08
33 #define PARM_DST 0x0c
34 #define PARM_SRC_DST_BIDX 0x10
35 #define PARM_LINK_BCNTRLD 0x14
36 #define PARM_SRC_DST_CIDX 0x18
37 #define PARM_CCNT 0x1c
38
39 #define PARM_SIZE 0x20
40
41 /* Offsets for EDMA CC global channel registers and their shadows */
42 #define SH_ER 0x00 /* 64 bits */
43 #define SH_ECR 0x08 /* 64 bits */
44 #define SH_ESR 0x10 /* 64 bits */
45 #define SH_CER 0x18 /* 64 bits */
46 #define SH_EER 0x20 /* 64 bits */
47 #define SH_EECR 0x28 /* 64 bits */
48 #define SH_EESR 0x30 /* 64 bits */
49 #define SH_SER 0x38 /* 64 bits */
50 #define SH_SECR 0x40 /* 64 bits */
51 #define SH_IER 0x50 /* 64 bits */
52 #define SH_IECR 0x58 /* 64 bits */
53 #define SH_IESR 0x60 /* 64 bits */
54 #define SH_IPR 0x68 /* 64 bits */
55 #define SH_ICR 0x70 /* 64 bits */
56 #define SH_IEVAL 0x78
57 #define SH_QER 0x80
58 #define SH_QEER 0x84
59 #define SH_QEECR 0x88
60 #define SH_QEESR 0x8c
61 #define SH_QSER 0x90
62 #define SH_QSECR 0x94
63 #define SH_SIZE 0x200
64
65 /* Offsets for EDMA CC global registers */
66 #define EDMA_REV 0x0000
67 #define EDMA_CCCFG 0x0004
68 #define EDMA_QCHMAP 0x0200 /* 8 registers */
69 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
70 #define EDMA_QDMAQNUM 0x0260
71 #define EDMA_QUETCMAP 0x0280
72 #define EDMA_QUEPRI 0x0284
73 #define EDMA_EMR 0x0300 /* 64 bits */
74 #define EDMA_EMCR 0x0308 /* 64 bits */
75 #define EDMA_QEMR 0x0310
76 #define EDMA_QEMCR 0x0314
77 #define EDMA_CCERR 0x0318
78 #define EDMA_CCERRCLR 0x031c
79 #define EDMA_EEVAL 0x0320
80 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
81 #define EDMA_QRAE 0x0380 /* 4 registers */
82 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
83 #define EDMA_QSTAT 0x0600 /* 2 registers */
84 #define EDMA_QWMTHRA 0x0620
85 #define EDMA_QWMTHRB 0x0624
86 #define EDMA_CCSTAT 0x0640
87
88 #define EDMA_M 0x1000 /* global channel registers */
89 #define EDMA_ECR 0x1008
90 #define EDMA_ECRH 0x100C
91 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
92 #define EDMA_PARM 0x4000 /* 128 param entries */
93
94 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
95
96 #define EDMA_DCHMAP 0x0100 /* 64 registers */
97 #define CHMAP_EXIST BIT(24)
98
99 #define EDMA_MAX_DMACH 64
100 #define EDMA_MAX_PARAMENTRY 512
101 #define EDMA_MAX_CC 2
102
103
104 /*****************************************************************************/
105
106 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
107
108 static inline unsigned int edma_read(unsigned ctlr, int offset)
109 {
110 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
111 }
112
113 static inline void edma_write(unsigned ctlr, int offset, int val)
114 {
115 __raw_writel(val, edmacc_regs_base[ctlr] + offset);
116 }
117 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
118 unsigned or)
119 {
120 unsigned val = edma_read(ctlr, offset);
121 val &= and;
122 val |= or;
123 edma_write(ctlr, offset, val);
124 }
125 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
126 {
127 unsigned val = edma_read(ctlr, offset);
128 val &= and;
129 edma_write(ctlr, offset, val);
130 }
131 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
132 {
133 unsigned val = edma_read(ctlr, offset);
134 val |= or;
135 edma_write(ctlr, offset, val);
136 }
137 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
138 {
139 return edma_read(ctlr, offset + (i << 2));
140 }
141 static inline void edma_write_array(unsigned ctlr, int offset, int i,
142 unsigned val)
143 {
144 edma_write(ctlr, offset + (i << 2), val);
145 }
146 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
147 unsigned and, unsigned or)
148 {
149 edma_modify(ctlr, offset + (i << 2), and, or);
150 }
151 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
152 {
153 edma_or(ctlr, offset + (i << 2), or);
154 }
155 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
156 unsigned or)
157 {
158 edma_or(ctlr, offset + ((i*2 + j) << 2), or);
159 }
160 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
161 unsigned val)
162 {
163 edma_write(ctlr, offset + ((i*2 + j) << 2), val);
164 }
165 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
166 {
167 return edma_read(ctlr, EDMA_SHADOW0 + offset);
168 }
169 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
170 int i)
171 {
172 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
173 }
174 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
175 {
176 edma_write(ctlr, EDMA_SHADOW0 + offset, val);
177 }
178 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
179 unsigned val)
180 {
181 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
182 }
183 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
184 int param_no)
185 {
186 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
187 }
188 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
189 unsigned val)
190 {
191 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
192 }
193 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
194 unsigned and, unsigned or)
195 {
196 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
197 }
198 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
199 unsigned and)
200 {
201 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
202 }
203 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
204 unsigned or)
205 {
206 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
207 }
208
209 /*****************************************************************************/
210
211 /* actual number of DMA channels and slots on this silicon */
212 struct edma {
213 /* how many dma resources of each type */
214 unsigned num_channels;
215 unsigned num_region;
216 unsigned num_slots;
217 unsigned num_tc;
218 unsigned num_cc;
219 enum dma_event_q default_queue;
220
221 /* list of channels with no even trigger; terminated by "-1" */
222 const s8 *noevent;
223
224 /* The edma_inuse bit for each PaRAM slot is clear unless the
225 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
226 */
227 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
228
229 /* The edma_noevent bit for each channel is clear unless
230 * it doesn't trigger DMA events on this platform. It uses a
231 * bit of SOC-specific initialization code.
232 */
233 DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH);
234
235 unsigned irq_res_start;
236 unsigned irq_res_end;
237
238 struct dma_interrupt_data {
239 void (*callback)(unsigned channel, unsigned short ch_status,
240 void *data);
241 void *data;
242 } intr_data[EDMA_MAX_DMACH];
243 };
244
245 static struct edma *edma_info[EDMA_MAX_CC];
246
247 /* dummy param set used to (re)initialize parameter RAM slots */
248 static const struct edmacc_param dummy_paramset = {
249 .link_bcntrld = 0xffff,
250 .ccnt = 1,
251 };
252
253 /*****************************************************************************/
254
255 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
256 enum dma_event_q queue_no)
257 {
258 int bit = (ch_no & 0x7) * 4;
259
260 /* default to low priority queue */
261 if (queue_no == EVENTQ_DEFAULT)
262 queue_no = edma_info[ctlr]->default_queue;
263
264 queue_no &= 7;
265 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
266 ~(0x7 << bit), queue_no << bit);
267 }
268
269 static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
270 {
271 int bit = queue_no * 4;
272 edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
273 }
274
275 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
276 int priority)
277 {
278 int bit = queue_no * 4;
279 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
280 ((priority & 0x7) << bit));
281 }
282
283 /**
284 * map_dmach_param - Maps channel number to param entry number
285 *
286 * This maps the dma channel number to param entry numberter. In
287 * other words using the DMA channel mapping registers a param entry
288 * can be mapped to any channel
289 *
290 * Callers are responsible for ensuring the channel mapping logic is
291 * included in that particular EDMA variant (Eg : dm646x)
292 *
293 */
294 static void __init map_dmach_param(unsigned ctlr)
295 {
296 int i;
297 for (i = 0; i < EDMA_MAX_DMACH; i++)
298 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
299 }
300
301 static inline void
302 setup_dma_interrupt(unsigned lch,
303 void (*callback)(unsigned channel, u16 ch_status, void *data),
304 void *data)
305 {
306 unsigned ctlr;
307
308 ctlr = EDMA_CTLR(lch);
309 lch = EDMA_CHAN_SLOT(lch);
310
311 if (!callback) {
312 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
313 (1 << (lch & 0x1f)));
314 }
315
316 edma_info[ctlr]->intr_data[lch].callback = callback;
317 edma_info[ctlr]->intr_data[lch].data = data;
318
319 if (callback) {
320 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
321 (1 << (lch & 0x1f)));
322 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
323 (1 << (lch & 0x1f)));
324 }
325 }
326
327 static int irq2ctlr(int irq)
328 {
329 if (irq >= edma_info[0]->irq_res_start &&
330 irq <= edma_info[0]->irq_res_end)
331 return 0;
332 else if (irq >= edma_info[1]->irq_res_start &&
333 irq <= edma_info[1]->irq_res_end)
334 return 1;
335
336 return -1;
337 }
338
339 /******************************************************************************
340 *
341 * DMA interrupt handler
342 *
343 *****************************************************************************/
344 static irqreturn_t dma_irq_handler(int irq, void *data)
345 {
346 int i;
347 unsigned ctlr;
348 unsigned int cnt = 0;
349
350 ctlr = irq2ctlr(irq);
351
352 dev_dbg(data, "dma_irq_handler\n");
353
354 if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
355 && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
356 return IRQ_NONE;
357
358 while (1) {
359 int j;
360 if (edma_shadow0_read_array(ctlr, SH_IPR, 0))
361 j = 0;
362 else if (edma_shadow0_read_array(ctlr, SH_IPR, 1))
363 j = 1;
364 else
365 break;
366 dev_dbg(data, "IPR%d %08x\n", j,
367 edma_shadow0_read_array(ctlr, SH_IPR, j));
368 for (i = 0; i < 32; i++) {
369 int k = (j << 5) + i;
370 if (edma_shadow0_read_array(ctlr, SH_IPR, j) &
371 (1 << i)) {
372 /* Clear the corresponding IPR bits */
373 edma_shadow0_write_array(ctlr, SH_ICR, j,
374 (1 << i));
375 if (edma_info[ctlr]->intr_data[k].callback) {
376 edma_info[ctlr]->intr_data[k].callback(
377 k, DMA_COMPLETE,
378 edma_info[ctlr]->intr_data[k].
379 data);
380 }
381 }
382 }
383 cnt++;
384 if (cnt > 10)
385 break;
386 }
387 edma_shadow0_write(ctlr, SH_IEVAL, 1);
388 return IRQ_HANDLED;
389 }
390
391 /******************************************************************************
392 *
393 * DMA error interrupt handler
394 *
395 *****************************************************************************/
396 static irqreturn_t dma_ccerr_handler(int irq, void *data)
397 {
398 int i;
399 unsigned ctlr;
400 unsigned int cnt = 0;
401
402 ctlr = irq2ctlr(irq);
403
404 dev_dbg(data, "dma_ccerr_handler\n");
405
406 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
407 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
408 (edma_read(ctlr, EDMA_QEMR) == 0) &&
409 (edma_read(ctlr, EDMA_CCERR) == 0))
410 return IRQ_NONE;
411
412 while (1) {
413 int j = -1;
414 if (edma_read_array(ctlr, EDMA_EMR, 0))
415 j = 0;
416 else if (edma_read_array(ctlr, EDMA_EMR, 1))
417 j = 1;
418 if (j >= 0) {
419 dev_dbg(data, "EMR%d %08x\n", j,
420 edma_read_array(ctlr, EDMA_EMR, j));
421 for (i = 0; i < 32; i++) {
422 int k = (j << 5) + i;
423 if (edma_read_array(ctlr, EDMA_EMR, j) &
424 (1 << i)) {
425 /* Clear the corresponding EMR bits */
426 edma_write_array(ctlr, EDMA_EMCR, j,
427 1 << i);
428 /* Clear any SER */
429 edma_shadow0_write_array(ctlr, SH_SECR,
430 j, (1 << i));
431 if (edma_info[ctlr]->intr_data[k].
432 callback) {
433 edma_info[ctlr]->intr_data[k].
434 callback(k,
435 DMA_CC_ERROR,
436 edma_info[ctlr]->intr_data
437 [k].data);
438 }
439 }
440 }
441 } else if (edma_read(ctlr, EDMA_QEMR)) {
442 dev_dbg(data, "QEMR %02x\n",
443 edma_read(ctlr, EDMA_QEMR));
444 for (i = 0; i < 8; i++) {
445 if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) {
446 /* Clear the corresponding IPR bits */
447 edma_write(ctlr, EDMA_QEMCR, 1 << i);
448 edma_shadow0_write(ctlr, SH_QSECR,
449 (1 << i));
450
451 /* NOTE: not reported!! */
452 }
453 }
454 } else if (edma_read(ctlr, EDMA_CCERR)) {
455 dev_dbg(data, "CCERR %08x\n",
456 edma_read(ctlr, EDMA_CCERR));
457 /* FIXME: CCERR.BIT(16) ignored! much better
458 * to just write CCERRCLR with CCERR value...
459 */
460 for (i = 0; i < 8; i++) {
461 if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) {
462 /* Clear the corresponding IPR bits */
463 edma_write(ctlr, EDMA_CCERRCLR, 1 << i);
464
465 /* NOTE: not reported!! */
466 }
467 }
468 }
469 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
470 && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
471 && (edma_read(ctlr, EDMA_QEMR) == 0)
472 && (edma_read(ctlr, EDMA_CCERR) == 0)) {
473 break;
474 }
475 cnt++;
476 if (cnt > 10)
477 break;
478 }
479 edma_write(ctlr, EDMA_EEVAL, 1);
480 return IRQ_HANDLED;
481 }
482
483 /******************************************************************************
484 *
485 * Transfer controller error interrupt handlers
486 *
487 *****************************************************************************/
488
489 #define tc_errs_handled false /* disabled as long as they're NOPs */
490
491 static irqreturn_t dma_tc0err_handler(int irq, void *data)
492 {
493 dev_dbg(data, "dma_tc0err_handler\n");
494 return IRQ_HANDLED;
495 }
496
497 static irqreturn_t dma_tc1err_handler(int irq, void *data)
498 {
499 dev_dbg(data, "dma_tc1err_handler\n");
500 return IRQ_HANDLED;
501 }
502
503 static int reserve_contiguous_slots(int ctlr, unsigned int id,
504 unsigned int num_slots,
505 unsigned int start_slot)
506 {
507 int i, j;
508 unsigned int count = num_slots;
509 int stop_slot = start_slot;
510 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
511
512 for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) {
513 j = EDMA_CHAN_SLOT(i);
514 if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) {
515 /* Record our current beginning slot */
516 if (count == num_slots)
517 stop_slot = i;
518
519 count--;
520 set_bit(j, tmp_inuse);
521
522 if (count == 0)
523 break;
524 } else {
525 clear_bit(j, tmp_inuse);
526
527 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
528 stop_slot = i;
529 break;
530 } else
531 count = num_slots;
532 }
533 }
534
535 /*
536 * We have to clear any bits that we set
537 * if we run out parameter RAM slots, i.e we do find a set
538 * of contiguous parameter RAM slots but do not find the exact number
539 * requested as we may reach the total number of parameter RAM slots
540 */
541 if (i == edma_info[ctlr]->num_slots)
542 stop_slot = i;
543
544 for (j = start_slot; j < stop_slot; j++)
545 if (test_bit(j, tmp_inuse))
546 clear_bit(j, edma_info[ctlr]->edma_inuse);
547
548 if (count)
549 return -EBUSY;
550
551 for (j = i - num_slots + 1; j <= i; ++j)
552 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
553 &dummy_paramset, PARM_SIZE);
554
555 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
556 }
557
558 /*-----------------------------------------------------------------------*/
559
560 /* Resource alloc/free: dma channels, parameter RAM slots */
561
562 /**
563 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
564 * @channel: specific channel to allocate; negative for "any unmapped channel"
565 * @callback: optional; to be issued on DMA completion or errors
566 * @data: passed to callback
567 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
568 * Controller (TC) executes requests using this channel. Use
569 * EVENTQ_DEFAULT unless you really need a high priority queue.
570 *
571 * This allocates a DMA channel and its associated parameter RAM slot.
572 * The parameter RAM is initialized to hold a dummy transfer.
573 *
574 * Normal use is to pass a specific channel number as @channel, to make
575 * use of hardware events mapped to that channel. When the channel will
576 * be used only for software triggering or event chaining, channels not
577 * mapped to hardware events (or mapped to unused events) are preferable.
578 *
579 * DMA transfers start from a channel using edma_start(), or by
580 * chaining. When the transfer described in that channel's parameter RAM
581 * slot completes, that slot's data may be reloaded through a link.
582 *
583 * DMA errors are only reported to the @callback associated with the
584 * channel driving that transfer, but transfer completion callbacks can
585 * be sent to another channel under control of the TCC field in
586 * the option word of the transfer's parameter RAM set. Drivers must not
587 * use DMA transfer completion callbacks for channels they did not allocate.
588 * (The same applies to TCC codes used in transfer chaining.)
589 *
590 * Returns the number of the channel, else negative errno.
591 */
592 int edma_alloc_channel(int channel,
593 void (*callback)(unsigned channel, u16 ch_status, void *data),
594 void *data,
595 enum dma_event_q eventq_no)
596 {
597 unsigned i, done, ctlr = 0;
598
599 if (channel >= 0) {
600 ctlr = EDMA_CTLR(channel);
601 channel = EDMA_CHAN_SLOT(channel);
602 }
603
604 if (channel < 0) {
605 for (i = 0; i < EDMA_MAX_CC; i++) {
606 channel = 0;
607 for (;;) {
608 channel = find_next_bit(edma_info[i]->
609 edma_noevent,
610 edma_info[i]->num_channels,
611 channel);
612 if (channel == edma_info[i]->num_channels)
613 return -ENOMEM;
614 if (!test_and_set_bit(channel,
615 edma_info[i]->edma_inuse)) {
616 done = 1;
617 ctlr = i;
618 break;
619 }
620 channel++;
621 }
622 if (done)
623 break;
624 }
625 } else if (channel >= edma_info[ctlr]->num_channels) {
626 return -EINVAL;
627 } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
628 return -EBUSY;
629 }
630
631 /* ensure access through shadow region 0 */
632 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
633
634 /* ensure no events are pending */
635 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
636 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
637 &dummy_paramset, PARM_SIZE);
638
639 if (callback)
640 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
641 callback, data);
642
643 map_dmach_queue(ctlr, channel, eventq_no);
644
645 return channel;
646 }
647 EXPORT_SYMBOL(edma_alloc_channel);
648
649
650 /**
651 * edma_free_channel - deallocate DMA channel
652 * @channel: dma channel returned from edma_alloc_channel()
653 *
654 * This deallocates the DMA channel and associated parameter RAM slot
655 * allocated by edma_alloc_channel().
656 *
657 * Callers are responsible for ensuring the channel is inactive, and
658 * will not be reactivated by linking, chaining, or software calls to
659 * edma_start().
660 */
661 void edma_free_channel(unsigned channel)
662 {
663 unsigned ctlr;
664
665 ctlr = EDMA_CTLR(channel);
666 channel = EDMA_CHAN_SLOT(channel);
667
668 if (channel >= edma_info[ctlr]->num_channels)
669 return;
670
671 setup_dma_interrupt(channel, NULL, NULL);
672 /* REVISIT should probably take out of shadow region 0 */
673
674 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
675 &dummy_paramset, PARM_SIZE);
676 clear_bit(channel, edma_info[ctlr]->edma_inuse);
677 }
678 EXPORT_SYMBOL(edma_free_channel);
679
680 /**
681 * edma_alloc_slot - allocate DMA parameter RAM
682 * @slot: specific slot to allocate; negative for "any unused slot"
683 *
684 * This allocates a parameter RAM slot, initializing it to hold a
685 * dummy transfer. Slots allocated using this routine have not been
686 * mapped to a hardware DMA channel, and will normally be used by
687 * linking to them from a slot associated with a DMA channel.
688 *
689 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
690 * slots may be allocated on behalf of DSP firmware.
691 *
692 * Returns the number of the slot, else negative errno.
693 */
694 int edma_alloc_slot(unsigned ctlr, int slot)
695 {
696 if (slot >= 0)
697 slot = EDMA_CHAN_SLOT(slot);
698
699 if (slot < 0) {
700 slot = edma_info[ctlr]->num_channels;
701 for (;;) {
702 slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse,
703 edma_info[ctlr]->num_slots, slot);
704 if (slot == edma_info[ctlr]->num_slots)
705 return -ENOMEM;
706 if (!test_and_set_bit(slot,
707 edma_info[ctlr]->edma_inuse))
708 break;
709 }
710 } else if (slot < edma_info[ctlr]->num_channels ||
711 slot >= edma_info[ctlr]->num_slots) {
712 return -EINVAL;
713 } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) {
714 return -EBUSY;
715 }
716
717 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
718 &dummy_paramset, PARM_SIZE);
719
720 return EDMA_CTLR_CHAN(ctlr, slot);
721 }
722 EXPORT_SYMBOL(edma_alloc_slot);
723
724 /**
725 * edma_free_slot - deallocate DMA parameter RAM
726 * @slot: parameter RAM slot returned from edma_alloc_slot()
727 *
728 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
729 * Callers are responsible for ensuring the slot is inactive, and will
730 * not be activated.
731 */
732 void edma_free_slot(unsigned slot)
733 {
734 unsigned ctlr;
735
736 ctlr = EDMA_CTLR(slot);
737 slot = EDMA_CHAN_SLOT(slot);
738
739 if (slot < edma_info[ctlr]->num_channels ||
740 slot >= edma_info[ctlr]->num_slots)
741 return;
742
743 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
744 &dummy_paramset, PARM_SIZE);
745 clear_bit(slot, edma_info[ctlr]->edma_inuse);
746 }
747 EXPORT_SYMBOL(edma_free_slot);
748
749
750 /**
751 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
752 * The API will return the starting point of a set of
753 * contiguous parameter RAM slots that have been requested
754 *
755 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
756 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
757 * @count: number of contiguous Paramter RAM slots
758 * @slot - the start value of Parameter RAM slot that should be passed if id
759 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
760 *
761 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
762 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
763 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
764 *
765 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
766 * set of contiguous parameter RAM slots from the "slot" that is passed as an
767 * argument to the API.
768 *
769 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
770 * starts looking for a set of contiguous parameter RAMs from the "slot"
771 * that is passed as an argument to the API. On failure the API will try to
772 * find a set of contiguous Parameter RAM slots from the remaining Parameter
773 * RAM slots
774 */
775 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
776 {
777 /*
778 * The start slot requested should be greater than
779 * the number of channels and lesser than the total number
780 * of slots
781 */
782 if ((id != EDMA_CONT_PARAMS_ANY) &&
783 (slot < edma_info[ctlr]->num_channels ||
784 slot >= edma_info[ctlr]->num_slots))
785 return -EINVAL;
786
787 /*
788 * The number of parameter RAM slots requested cannot be less than 1
789 * and cannot be more than the number of slots minus the number of
790 * channels
791 */
792 if (count < 1 || count >
793 (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels))
794 return -EINVAL;
795
796 switch (id) {
797 case EDMA_CONT_PARAMS_ANY:
798 return reserve_contiguous_slots(ctlr, id, count,
799 edma_info[ctlr]->num_channels);
800 case EDMA_CONT_PARAMS_FIXED_EXACT:
801 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
802 return reserve_contiguous_slots(ctlr, id, count, slot);
803 default:
804 return -EINVAL;
805 }
806
807 }
808 EXPORT_SYMBOL(edma_alloc_cont_slots);
809
810 /**
811 * edma_free_cont_slots - deallocate DMA parameter RAM slots
812 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
813 * @count: the number of contiguous parameter RAM slots to be freed
814 *
815 * This deallocates the parameter RAM slots allocated by
816 * edma_alloc_cont_slots.
817 * Callers/applications need to keep track of sets of contiguous
818 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
819 * API.
820 * Callers are responsible for ensuring the slots are inactive, and will
821 * not be activated.
822 */
823 int edma_free_cont_slots(unsigned slot, int count)
824 {
825 unsigned ctlr, slot_to_free;
826 int i;
827
828 ctlr = EDMA_CTLR(slot);
829 slot = EDMA_CHAN_SLOT(slot);
830
831 if (slot < edma_info[ctlr]->num_channels ||
832 slot >= edma_info[ctlr]->num_slots ||
833 count < 1)
834 return -EINVAL;
835
836 for (i = slot; i < slot + count; ++i) {
837 ctlr = EDMA_CTLR(i);
838 slot_to_free = EDMA_CHAN_SLOT(i);
839
840 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
841 &dummy_paramset, PARM_SIZE);
842 clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse);
843 }
844
845 return 0;
846 }
847 EXPORT_SYMBOL(edma_free_cont_slots);
848
849 /*-----------------------------------------------------------------------*/
850
851 /* Parameter RAM operations (i) -- read/write partial slots */
852
853 /**
854 * edma_set_src - set initial DMA source address in parameter RAM slot
855 * @slot: parameter RAM slot being configured
856 * @src_port: physical address of source (memory, controller FIFO, etc)
857 * @addressMode: INCR, except in very rare cases
858 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
859 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
860 *
861 * Note that the source address is modified during the DMA transfer
862 * according to edma_set_src_index().
863 */
864 void edma_set_src(unsigned slot, dma_addr_t src_port,
865 enum address_mode mode, enum fifo_width width)
866 {
867 unsigned ctlr;
868
869 ctlr = EDMA_CTLR(slot);
870 slot = EDMA_CHAN_SLOT(slot);
871
872 if (slot < edma_info[ctlr]->num_slots) {
873 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
874
875 if (mode) {
876 /* set SAM and program FWID */
877 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
878 } else {
879 /* clear SAM */
880 i &= ~SAM;
881 }
882 edma_parm_write(ctlr, PARM_OPT, slot, i);
883
884 /* set the source port address
885 in source register of param structure */
886 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
887 }
888 }
889 EXPORT_SYMBOL(edma_set_src);
890
891 /**
892 * edma_set_dest - set initial DMA destination address in parameter RAM slot
893 * @slot: parameter RAM slot being configured
894 * @dest_port: physical address of destination (memory, controller FIFO, etc)
895 * @addressMode: INCR, except in very rare cases
896 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
897 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
898 *
899 * Note that the destination address is modified during the DMA transfer
900 * according to edma_set_dest_index().
901 */
902 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
903 enum address_mode mode, enum fifo_width width)
904 {
905 unsigned ctlr;
906
907 ctlr = EDMA_CTLR(slot);
908 slot = EDMA_CHAN_SLOT(slot);
909
910 if (slot < edma_info[ctlr]->num_slots) {
911 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
912
913 if (mode) {
914 /* set DAM and program FWID */
915 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
916 } else {
917 /* clear DAM */
918 i &= ~DAM;
919 }
920 edma_parm_write(ctlr, PARM_OPT, slot, i);
921 /* set the destination port address
922 in dest register of param structure */
923 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
924 }
925 }
926 EXPORT_SYMBOL(edma_set_dest);
927
928 /**
929 * edma_get_position - returns the current transfer points
930 * @slot: parameter RAM slot being examined
931 * @src: pointer to source port position
932 * @dst: pointer to destination port position
933 *
934 * Returns current source and destination addresses for a particular
935 * parameter RAM slot. Its channel should not be active when this is called.
936 */
937 void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
938 {
939 struct edmacc_param temp;
940 unsigned ctlr;
941
942 ctlr = EDMA_CTLR(slot);
943 slot = EDMA_CHAN_SLOT(slot);
944
945 edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
946 if (src != NULL)
947 *src = temp.src;
948 if (dst != NULL)
949 *dst = temp.dst;
950 }
951 EXPORT_SYMBOL(edma_get_position);
952
953 /**
954 * edma_set_src_index - configure DMA source address indexing
955 * @slot: parameter RAM slot being configured
956 * @src_bidx: byte offset between source arrays in a frame
957 * @src_cidx: byte offset between source frames in a block
958 *
959 * Offsets are specified to support either contiguous or discontiguous
960 * memory transfers, or repeated access to a hardware register, as needed.
961 * When accessing hardware registers, both offsets are normally zero.
962 */
963 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
964 {
965 unsigned ctlr;
966
967 ctlr = EDMA_CTLR(slot);
968 slot = EDMA_CHAN_SLOT(slot);
969
970 if (slot < edma_info[ctlr]->num_slots) {
971 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
972 0xffff0000, src_bidx);
973 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
974 0xffff0000, src_cidx);
975 }
976 }
977 EXPORT_SYMBOL(edma_set_src_index);
978
979 /**
980 * edma_set_dest_index - configure DMA destination address indexing
981 * @slot: parameter RAM slot being configured
982 * @dest_bidx: byte offset between destination arrays in a frame
983 * @dest_cidx: byte offset between destination frames in a block
984 *
985 * Offsets are specified to support either contiguous or discontiguous
986 * memory transfers, or repeated access to a hardware register, as needed.
987 * When accessing hardware registers, both offsets are normally zero.
988 */
989 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
990 {
991 unsigned ctlr;
992
993 ctlr = EDMA_CTLR(slot);
994 slot = EDMA_CHAN_SLOT(slot);
995
996 if (slot < edma_info[ctlr]->num_slots) {
997 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
998 0x0000ffff, dest_bidx << 16);
999 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1000 0x0000ffff, dest_cidx << 16);
1001 }
1002 }
1003 EXPORT_SYMBOL(edma_set_dest_index);
1004
1005 /**
1006 * edma_set_transfer_params - configure DMA transfer parameters
1007 * @slot: parameter RAM slot being configured
1008 * @acnt: how many bytes per array (at least one)
1009 * @bcnt: how many arrays per frame (at least one)
1010 * @ccnt: how many frames per block (at least one)
1011 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1012 * the value to reload into bcnt when it decrements to zero
1013 * @sync_mode: ASYNC or ABSYNC
1014 *
1015 * See the EDMA3 documentation to understand how to configure and link
1016 * transfers using the fields in PaRAM slots. If you are not doing it
1017 * all at once with edma_write_slot(), you will use this routine
1018 * plus two calls each for source and destination, setting the initial
1019 * address and saying how to index that address.
1020 *
1021 * An example of an A-Synchronized transfer is a serial link using a
1022 * single word shift register. In that case, @acnt would be equal to
1023 * that word size; the serial controller issues a DMA synchronization
1024 * event to transfer each word, and memory access by the DMA transfer
1025 * controller will be word-at-a-time.
1026 *
1027 * An example of an AB-Synchronized transfer is a device using a FIFO.
1028 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1029 * The controller with the FIFO issues DMA synchronization events when
1030 * the FIFO threshold is reached, and the DMA transfer controller will
1031 * transfer one frame to (or from) the FIFO. It will probably use
1032 * efficient burst modes to access memory.
1033 */
1034 void edma_set_transfer_params(unsigned slot,
1035 u16 acnt, u16 bcnt, u16 ccnt,
1036 u16 bcnt_rld, enum sync_dimension sync_mode)
1037 {
1038 unsigned ctlr;
1039
1040 ctlr = EDMA_CTLR(slot);
1041 slot = EDMA_CHAN_SLOT(slot);
1042
1043 if (slot < edma_info[ctlr]->num_slots) {
1044 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1045 0x0000ffff, bcnt_rld << 16);
1046 if (sync_mode == ASYNC)
1047 edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
1048 else
1049 edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
1050 /* Set the acount, bcount, ccount registers */
1051 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1052 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
1053 }
1054 }
1055 EXPORT_SYMBOL(edma_set_transfer_params);
1056
1057 /**
1058 * edma_link - link one parameter RAM slot to another
1059 * @from: parameter RAM slot originating the link
1060 * @to: parameter RAM slot which is the link target
1061 *
1062 * The originating slot should not be part of any active DMA transfer.
1063 */
1064 void edma_link(unsigned from, unsigned to)
1065 {
1066 unsigned ctlr_from, ctlr_to;
1067
1068 ctlr_from = EDMA_CTLR(from);
1069 from = EDMA_CHAN_SLOT(from);
1070 ctlr_to = EDMA_CTLR(to);
1071 to = EDMA_CHAN_SLOT(to);
1072
1073 if (from >= edma_info[ctlr_from]->num_slots)
1074 return;
1075 if (to >= edma_info[ctlr_to]->num_slots)
1076 return;
1077 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1078 PARM_OFFSET(to));
1079 }
1080 EXPORT_SYMBOL(edma_link);
1081
1082 /**
1083 * edma_unlink - cut link from one parameter RAM slot
1084 * @from: parameter RAM slot originating the link
1085 *
1086 * The originating slot should not be part of any active DMA transfer.
1087 * Its link is set to 0xffff.
1088 */
1089 void edma_unlink(unsigned from)
1090 {
1091 unsigned ctlr;
1092
1093 ctlr = EDMA_CTLR(from);
1094 from = EDMA_CHAN_SLOT(from);
1095
1096 if (from >= edma_info[ctlr]->num_slots)
1097 return;
1098 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1099 }
1100 EXPORT_SYMBOL(edma_unlink);
1101
1102 /*-----------------------------------------------------------------------*/
1103
1104 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1105
1106 /**
1107 * edma_write_slot - write parameter RAM data for slot
1108 * @slot: number of parameter RAM slot being modified
1109 * @param: data to be written into parameter RAM slot
1110 *
1111 * Use this to assign all parameters of a transfer at once. This
1112 * allows more efficient setup of transfers than issuing multiple
1113 * calls to set up those parameters in small pieces, and provides
1114 * complete control over all transfer options.
1115 */
1116 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1117 {
1118 unsigned ctlr;
1119
1120 ctlr = EDMA_CTLR(slot);
1121 slot = EDMA_CHAN_SLOT(slot);
1122
1123 if (slot >= edma_info[ctlr]->num_slots)
1124 return;
1125 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1126 PARM_SIZE);
1127 }
1128 EXPORT_SYMBOL(edma_write_slot);
1129
1130 /**
1131 * edma_read_slot - read parameter RAM data from slot
1132 * @slot: number of parameter RAM slot being copied
1133 * @param: where to store copy of parameter RAM data
1134 *
1135 * Use this to read data from a parameter RAM slot, perhaps to
1136 * save them as a template for later reuse.
1137 */
1138 void edma_read_slot(unsigned slot, struct edmacc_param *param)
1139 {
1140 unsigned ctlr;
1141
1142 ctlr = EDMA_CTLR(slot);
1143 slot = EDMA_CHAN_SLOT(slot);
1144
1145 if (slot >= edma_info[ctlr]->num_slots)
1146 return;
1147 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1148 PARM_SIZE);
1149 }
1150 EXPORT_SYMBOL(edma_read_slot);
1151
1152 /*-----------------------------------------------------------------------*/
1153
1154 /* Various EDMA channel control operations */
1155
1156 /**
1157 * edma_pause - pause dma on a channel
1158 * @channel: on which edma_start() has been called
1159 *
1160 * This temporarily disables EDMA hardware events on the specified channel,
1161 * preventing them from triggering new transfers on its behalf
1162 */
1163 void edma_pause(unsigned channel)
1164 {
1165 unsigned ctlr;
1166
1167 ctlr = EDMA_CTLR(channel);
1168 channel = EDMA_CHAN_SLOT(channel);
1169
1170 if (channel < edma_info[ctlr]->num_channels) {
1171 unsigned int mask = (1 << (channel & 0x1f));
1172
1173 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1174 }
1175 }
1176 EXPORT_SYMBOL(edma_pause);
1177
1178 /**
1179 * edma_resume - resumes dma on a paused channel
1180 * @channel: on which edma_pause() has been called
1181 *
1182 * This re-enables EDMA hardware events on the specified channel.
1183 */
1184 void edma_resume(unsigned channel)
1185 {
1186 unsigned ctlr;
1187
1188 ctlr = EDMA_CTLR(channel);
1189 channel = EDMA_CHAN_SLOT(channel);
1190
1191 if (channel < edma_info[ctlr]->num_channels) {
1192 unsigned int mask = (1 << (channel & 0x1f));
1193
1194 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1195 }
1196 }
1197 EXPORT_SYMBOL(edma_resume);
1198
1199 /**
1200 * edma_start - start dma on a channel
1201 * @channel: channel being activated
1202 *
1203 * Channels with event associations will be triggered by their hardware
1204 * events, and channels without such associations will be triggered by
1205 * software. (At this writing there is no interface for using software
1206 * triggers except with channels that don't support hardware triggers.)
1207 *
1208 * Returns zero on success, else negative errno.
1209 */
1210 int edma_start(unsigned channel)
1211 {
1212 unsigned ctlr;
1213
1214 ctlr = EDMA_CTLR(channel);
1215 channel = EDMA_CHAN_SLOT(channel);
1216
1217 if (channel < edma_info[ctlr]->num_channels) {
1218 int j = channel >> 5;
1219 unsigned int mask = (1 << (channel & 0x1f));
1220
1221 /* EDMA channels without event association */
1222 if (test_bit(channel, edma_info[ctlr]->edma_noevent)) {
1223 pr_debug("EDMA: ESR%d %08x\n", j,
1224 edma_shadow0_read_array(ctlr, SH_ESR, j));
1225 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1226 return 0;
1227 }
1228
1229 /* EDMA channel with event association */
1230 pr_debug("EDMA: ER%d %08x\n", j,
1231 edma_shadow0_read_array(ctlr, SH_ER, j));
1232 /* Clear any pending error */
1233 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1234 /* Clear any SER */
1235 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1236 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1237 pr_debug("EDMA: EER%d %08x\n", j,
1238 edma_shadow0_read_array(ctlr, SH_EER, j));
1239 return 0;
1240 }
1241
1242 return -EINVAL;
1243 }
1244 EXPORT_SYMBOL(edma_start);
1245
1246 /**
1247 * edma_stop - stops dma on the channel passed
1248 * @channel: channel being deactivated
1249 *
1250 * When @lch is a channel, any active transfer is paused and
1251 * all pending hardware events are cleared. The current transfer
1252 * may not be resumed, and the channel's Parameter RAM should be
1253 * reinitialized before being reused.
1254 */
1255 void edma_stop(unsigned channel)
1256 {
1257 unsigned ctlr;
1258
1259 ctlr = EDMA_CTLR(channel);
1260 channel = EDMA_CHAN_SLOT(channel);
1261
1262 if (channel < edma_info[ctlr]->num_channels) {
1263 int j = channel >> 5;
1264 unsigned int mask = (1 << (channel & 0x1f));
1265
1266 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1267 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1268 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1269 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1270
1271 pr_debug("EDMA: EER%d %08x\n", j,
1272 edma_shadow0_read_array(ctlr, SH_EER, j));
1273
1274 /* REVISIT: consider guarding against inappropriate event
1275 * chaining by overwriting with dummy_paramset.
1276 */
1277 }
1278 }
1279 EXPORT_SYMBOL(edma_stop);
1280
1281 /******************************************************************************
1282 *
1283 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1284 * been removed before EDMA has finished.It is usedful for removable media.
1285 * Arguments:
1286 * ch_no - channel no
1287 *
1288 * Return: zero on success, or corresponding error no on failure
1289 *
1290 * FIXME this should not be needed ... edma_stop() should suffice.
1291 *
1292 *****************************************************************************/
1293
1294 void edma_clean_channel(unsigned channel)
1295 {
1296 unsigned ctlr;
1297
1298 ctlr = EDMA_CTLR(channel);
1299 channel = EDMA_CHAN_SLOT(channel);
1300
1301 if (channel < edma_info[ctlr]->num_channels) {
1302 int j = (channel >> 5);
1303 unsigned int mask = 1 << (channel & 0x1f);
1304
1305 pr_debug("EDMA: EMR%d %08x\n", j,
1306 edma_read_array(ctlr, EDMA_EMR, j));
1307 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1308 /* Clear the corresponding EMR bits */
1309 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1310 /* Clear any SER */
1311 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1312 edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3);
1313 }
1314 }
1315 EXPORT_SYMBOL(edma_clean_channel);
1316
1317 /*
1318 * edma_clear_event - clear an outstanding event on the DMA channel
1319 * Arguments:
1320 * channel - channel number
1321 */
1322 void edma_clear_event(unsigned channel)
1323 {
1324 unsigned ctlr;
1325
1326 ctlr = EDMA_CTLR(channel);
1327 channel = EDMA_CHAN_SLOT(channel);
1328
1329 if (channel >= edma_info[ctlr]->num_channels)
1330 return;
1331 if (channel < 32)
1332 edma_write(ctlr, EDMA_ECR, 1 << channel);
1333 else
1334 edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32));
1335 }
1336 EXPORT_SYMBOL(edma_clear_event);
1337
1338 /*-----------------------------------------------------------------------*/
1339
1340 static int __init edma_probe(struct platform_device *pdev)
1341 {
1342 struct edma_soc_info *info = pdev->dev.platform_data;
1343 const s8 (*queue_priority_mapping)[2];
1344 const s8 (*queue_tc_mapping)[2];
1345 int i, j, found = 0;
1346 int status = -1;
1347 const s8 *noevent;
1348 int irq[EDMA_MAX_CC] = {0, 0};
1349 int err_irq[EDMA_MAX_CC] = {0, 0};
1350 struct resource *r[EDMA_MAX_CC] = {NULL};
1351 resource_size_t len[EDMA_MAX_CC];
1352 char res_name[10];
1353 char irq_name[10];
1354
1355 if (!info)
1356 return -ENODEV;
1357
1358 for (j = 0; j < EDMA_MAX_CC; j++) {
1359 sprintf(res_name, "edma_cc%d", j);
1360 r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1361 res_name);
1362 if (!r[j]) {
1363 if (found)
1364 break;
1365 else
1366 return -ENODEV;
1367 } else
1368 found = 1;
1369
1370 len[j] = resource_size(r[j]);
1371
1372 r[j] = request_mem_region(r[j]->start, len[j],
1373 dev_name(&pdev->dev));
1374 if (!r[j]) {
1375 status = -EBUSY;
1376 goto fail1;
1377 }
1378
1379 edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
1380 if (!edmacc_regs_base[j]) {
1381 status = -EBUSY;
1382 goto fail1;
1383 }
1384
1385 edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
1386 if (!edma_info[j]) {
1387 status = -ENOMEM;
1388 goto fail1;
1389 }
1390 memset(edma_info[j], 0, sizeof(struct edma));
1391
1392 edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel,
1393 EDMA_MAX_DMACH);
1394 edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot,
1395 EDMA_MAX_PARAMENTRY);
1396 edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc,
1397 EDMA_MAX_CC);
1398
1399 edma_info[j]->default_queue = info[j].default_queue;
1400 if (!edma_info[j]->default_queue)
1401 edma_info[j]->default_queue = EVENTQ_1;
1402
1403 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1404 edmacc_regs_base[j]);
1405
1406 for (i = 0; i < edma_info[j]->num_slots; i++)
1407 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1408 &dummy_paramset, PARM_SIZE);
1409
1410 noevent = info[j].noevent;
1411 if (noevent) {
1412 while (*noevent != -1)
1413 set_bit(*noevent++, edma_info[j]->edma_noevent);
1414 }
1415
1416 sprintf(irq_name, "edma%d", j);
1417 irq[j] = platform_get_irq_byname(pdev, irq_name);
1418 edma_info[j]->irq_res_start = irq[j];
1419 status = request_irq(irq[j], dma_irq_handler, 0, "edma",
1420 &pdev->dev);
1421 if (status < 0) {
1422 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1423 irq[j], status);
1424 goto fail;
1425 }
1426
1427 sprintf(irq_name, "edma%d_err", j);
1428 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1429 edma_info[j]->irq_res_end = err_irq[j];
1430 status = request_irq(err_irq[j], dma_ccerr_handler, 0,
1431 "edma_error", &pdev->dev);
1432 if (status < 0) {
1433 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1434 err_irq[j], status);
1435 goto fail;
1436 }
1437
1438 /* Everything lives on transfer controller 1 until otherwise
1439 * specified. This way, long transfers on the low priority queue
1440 * started by the codec engine will not cause audio defects.
1441 */
1442 for (i = 0; i < edma_info[j]->num_channels; i++)
1443 map_dmach_queue(j, i, EVENTQ_1);
1444
1445 queue_tc_mapping = info[j].queue_tc_mapping;
1446 queue_priority_mapping = info[j].queue_priority_mapping;
1447
1448 /* Event queue to TC mapping */
1449 for (i = 0; queue_tc_mapping[i][0] != -1; i++)
1450 map_queue_tc(j, queue_tc_mapping[i][0],
1451 queue_tc_mapping[i][1]);
1452
1453 /* Event queue priority mapping */
1454 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1455 assign_priority_to_queue(j,
1456 queue_priority_mapping[i][0],
1457 queue_priority_mapping[i][1]);
1458
1459 /* Map the channel to param entry if channel mapping logic
1460 * exist
1461 */
1462 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1463 map_dmach_param(j);
1464
1465 for (i = 0; i < info[j].n_region; i++) {
1466 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1467 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1468 edma_write_array(j, EDMA_QRAE, i, 0x0);
1469 }
1470 }
1471
1472 if (tc_errs_handled) {
1473 status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
1474 "edma_tc0", &pdev->dev);
1475 if (status < 0) {
1476 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1477 IRQ_TCERRINT0, status);
1478 return status;
1479 }
1480 status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
1481 "edma_tc1", &pdev->dev);
1482 if (status < 0) {
1483 dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
1484 IRQ_TCERRINT, status);
1485 return status;
1486 }
1487 }
1488
1489 return 0;
1490
1491 fail:
1492 for (i = 0; i < EDMA_MAX_CC; i++) {
1493 if (err_irq[i])
1494 free_irq(err_irq[i], &pdev->dev);
1495 if (irq[i])
1496 free_irq(irq[i], &pdev->dev);
1497 }
1498 fail1:
1499 for (i = 0; i < EDMA_MAX_CC; i++) {
1500 if (r[i])
1501 release_mem_region(r[i]->start, len[i]);
1502 if (edmacc_regs_base[i])
1503 iounmap(edmacc_regs_base[i]);
1504 kfree(edma_info[i]);
1505 }
1506 return status;
1507 }
1508
1509
1510 static struct platform_driver edma_driver = {
1511 .driver.name = "edma",
1512 };
1513
1514 static int __init edma_init(void)
1515 {
1516 return platform_driver_probe(&edma_driver, edma_probe);
1517 }
1518 arch_initcall(edma_init);
1519