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Linux 2.6.33
[pohmelfs.git] / arch / arm / mach-omap2 / mailbox.c
blob281ab63424481b99535b2c7ebc5d08a24b6b12ae
1 /*
2 * Mailbox reservation modules for OMAP2/3
3 *
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 * and Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
17 #include <linux/io.h>
18 #include <plat/mailbox.h>
19 #include <mach/irqs.h>
20
21 #define DRV_NAME "omap2-mailbox"
22
23 #define MAILBOX_REVISION 0x000
24 #define MAILBOX_SYSCONFIG 0x010
25 #define MAILBOX_SYSSTATUS 0x014
26 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
27 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
28 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
29 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
30 #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
31
32 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
33 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
34 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
35
36 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
37 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
38
39 /* SYSCONFIG: register bit definition */
40 #define AUTOIDLE (1 << 0)
41 #define SOFTRESET (1 << 1)
42 #define SMARTIDLE (2 << 3)
43
44 /* SYSSTATUS: register bit definition */
45 #define RESETDONE (1 << 0)
46
47 #define MBOX_REG_SIZE 0x120
48
49 #define OMAP4_MBOX_REG_SIZE 0x130
50
51 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
52 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
53
54 static void __iomem *mbox_base;
55
56 struct omap_mbox2_fifo {
57 unsigned long msg;
58 unsigned long fifo_stat;
59 unsigned long msg_stat;
60 };
61
62 struct omap_mbox2_priv {
63 struct omap_mbox2_fifo tx_fifo;
64 struct omap_mbox2_fifo rx_fifo;
65 unsigned long irqenable;
66 unsigned long irqstatus;
67 u32 newmsg_bit;
68 u32 notfull_bit;
69 u32 ctx[OMAP4_MBOX_NR_REGS];
70 unsigned long irqdisable;
71 };
72
73 static struct clk *mbox_ick_handle;
74
75 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
76 omap_mbox_type_t irq);
77
78 static inline unsigned int mbox_read_reg(size_t ofs)
79 {
80 return __raw_readl(mbox_base + ofs);
81 }
82
83 static inline void mbox_write_reg(u32 val, size_t ofs)
84 {
85 __raw_writel(val, mbox_base + ofs);
86 }
87
88 /* Mailbox H/W preparations */
89 static int omap2_mbox_startup(struct omap_mbox *mbox)
90 {
91 u32 l;
92 unsigned long timeout;
93
94 mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
95 if (IS_ERR(mbox_ick_handle)) {
96 printk(KERN_ERR "Could not get mailboxes_ick: %d\n",
97 PTR_ERR(mbox_ick_handle));
98 return PTR_ERR(mbox_ick_handle);
99 }
100 clk_enable(mbox_ick_handle);
101
102 mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
103 timeout = jiffies + msecs_to_jiffies(20);
104 do {
105 l = mbox_read_reg(MAILBOX_SYSSTATUS);
106 if (l & RESETDONE)
107 break;
108 } while (!time_after(jiffies, timeout));
109
110 if (!(l & RESETDONE)) {
111 pr_err("Can't take mmu out of reset\n");
112 return -ENODEV;
113 }
114
115 l = mbox_read_reg(MAILBOX_REVISION);
116 pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
117
118 l = SMARTIDLE | AUTOIDLE;
119 mbox_write_reg(l, MAILBOX_SYSCONFIG);
120
121 omap2_mbox_enable_irq(mbox, IRQ_RX);
122
123 return 0;
124 }
125
126 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
127 {
128 clk_disable(mbox_ick_handle);
129 clk_put(mbox_ick_handle);
130 mbox_ick_handle = NULL;
131 }
132
133 /* Mailbox FIFO handle functions */
134 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
135 {
136 struct omap_mbox2_fifo *fifo =
137 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
138 return (mbox_msg_t) mbox_read_reg(fifo->msg);
139 }
140
141 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
142 {
143 struct omap_mbox2_fifo *fifo =
144 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
145 mbox_write_reg(msg, fifo->msg);
146 }
147
148 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
149 {
150 struct omap_mbox2_fifo *fifo =
151 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
152 return (mbox_read_reg(fifo->msg_stat) == 0);
153 }
154
155 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
156 {
157 struct omap_mbox2_fifo *fifo =
158 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
159 return mbox_read_reg(fifo->fifo_stat);
160 }
161
162 /* Mailbox IRQ handle functions */
163 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
164 omap_mbox_type_t irq)
165 {
166 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
167 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
168
169 l = mbox_read_reg(p->irqenable);
170 l |= bit;
171 mbox_write_reg(l, p->irqenable);
172 }
173
174 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
175 omap_mbox_type_t irq)
176 {
177 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
178 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
179 l = mbox_read_reg(p->irqdisable);
180 l &= ~bit;
181 mbox_write_reg(l, p->irqdisable);
182 }
183
184 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
185 omap_mbox_type_t irq)
186 {
187 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
188 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
189
190 mbox_write_reg(bit, p->irqstatus);
191
192 /* Flush posted write for irq status to avoid spurious interrupts */
193 mbox_read_reg(p->irqstatus);
194 }
195
196 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
197 omap_mbox_type_t irq)
198 {
199 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
200 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
201 u32 enable = mbox_read_reg(p->irqenable);
202 u32 status = mbox_read_reg(p->irqstatus);
203
204 return (int)(enable & status & bit);
205 }
206
207 static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
208 {
209 int i;
210 struct omap_mbox2_priv *p = mbox->priv;
211 int nr_regs;
212 if (cpu_is_omap44xx())
213 nr_regs = OMAP4_MBOX_NR_REGS;
214 else
215 nr_regs = MBOX_NR_REGS;
216 for (i = 0; i < nr_regs; i++) {
217 p->ctx[i] = mbox_read_reg(i * sizeof(u32));
218
219 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
220 i, p->ctx[i]);
221 }
222 }
223
224 static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
225 {
226 int i;
227 struct omap_mbox2_priv *p = mbox->priv;
228 int nr_regs;
229 if (cpu_is_omap44xx())
230 nr_regs = OMAP4_MBOX_NR_REGS;
231 else
232 nr_regs = MBOX_NR_REGS;
233 for (i = 0; i < nr_regs; i++) {
234 mbox_write_reg(p->ctx[i], i * sizeof(u32));
235
236 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
237 i, p->ctx[i]);
238 }
239 }
240
241 static struct omap_mbox_ops omap2_mbox_ops = {
242 .type = OMAP_MBOX_TYPE2,
243 .startup = omap2_mbox_startup,
244 .shutdown = omap2_mbox_shutdown,
245 .fifo_read = omap2_mbox_fifo_read,
246 .fifo_write = omap2_mbox_fifo_write,
247 .fifo_empty = omap2_mbox_fifo_empty,
248 .fifo_full = omap2_mbox_fifo_full,
249 .enable_irq = omap2_mbox_enable_irq,
250 .disable_irq = omap2_mbox_disable_irq,
251 .ack_irq = omap2_mbox_ack_irq,
252 .is_irq = omap2_mbox_is_irq,
253 .save_ctx = omap2_mbox_save_ctx,
254 .restore_ctx = omap2_mbox_restore_ctx,
255 };
256
257 /*
258 * MAILBOX 0: ARM -> DSP,
259 * MAILBOX 1: ARM <- DSP.
260 * MAILBOX 2: ARM -> IVA,
261 * MAILBOX 3: ARM <- IVA.
262 */
263
264 /* FIXME: the following structs should be filled automatically by the user id */
265 /* DSP */
266 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
267 .tx_fifo = {
268 .msg = MAILBOX_MESSAGE(0),
269 .fifo_stat = MAILBOX_FIFOSTATUS(0),
270 },
271 .rx_fifo = {
272 .msg = MAILBOX_MESSAGE(1),
273 .msg_stat = MAILBOX_MSGSTATUS(1),
274 },
275 .irqenable = MAILBOX_IRQENABLE(0),
276 .irqstatus = MAILBOX_IRQSTATUS(0),
277 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
278 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
279 .irqdisable = MAILBOX_IRQENABLE(0),
280 };
281
282
283
284 /* OMAP4 specific data structure. Use the cpu_is_omap4xxx()
285 to use this*/
286 static struct omap_mbox2_priv omap2_mbox_1_priv = {
287 .tx_fifo = {
288 .msg = MAILBOX_MESSAGE(0),
289 .fifo_stat = MAILBOX_FIFOSTATUS(0),
290 },
291 .rx_fifo = {
292 .msg = MAILBOX_MESSAGE(1),
293 .msg_stat = MAILBOX_MSGSTATUS(1),
294 },
295 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
296 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
297 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
298 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
299 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
300 };
301
302 struct omap_mbox mbox_1_info = {
303 .name = "mailbox-1",
304 .ops = &omap2_mbox_ops,
305 .priv = &omap2_mbox_1_priv,
306 };
307 EXPORT_SYMBOL(mbox_1_info);
308
309 struct omap_mbox mbox_dsp_info = {
310 .name = "dsp",
311 .ops = &omap2_mbox_ops,
312 .priv = &omap2_mbox_dsp_priv,
313 };
314 EXPORT_SYMBOL(mbox_dsp_info);
315
316 static struct omap_mbox2_priv omap2_mbox_2_priv = {
317 .tx_fifo = {
318 .msg = MAILBOX_MESSAGE(3),
319 .fifo_stat = MAILBOX_FIFOSTATUS(3),
320 },
321 .rx_fifo = {
322 .msg = MAILBOX_MESSAGE(2),
323 .msg_stat = MAILBOX_MSGSTATUS(2),
324 },
325 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
326 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
327 .notfull_bit = MAILBOX_IRQ_NOTFULL(3),
328 .newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
329 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
330 };
331
332 struct omap_mbox mbox_2_info = {
333 .name = "mailbox-2",
334 .ops = &omap2_mbox_ops,
335 .priv = &omap2_mbox_2_priv,
336 };
337 EXPORT_SYMBOL(mbox_2_info);
338
339
340 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
341 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
342 .tx_fifo = {
343 .msg = MAILBOX_MESSAGE(2),
344 .fifo_stat = MAILBOX_FIFOSTATUS(2),
345 },
346 .rx_fifo = {
347 .msg = MAILBOX_MESSAGE(3),
348 .msg_stat = MAILBOX_MSGSTATUS(3),
349 },
350 .irqenable = MAILBOX_IRQENABLE(3),
351 .irqstatus = MAILBOX_IRQSTATUS(3),
352 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
353 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
354 .irqdisable = MAILBOX_IRQENABLE(3),
355 };
356
357 static struct omap_mbox mbox_iva_info = {
358 .name = "iva",
359 .ops = &omap2_mbox_ops,
360 .priv = &omap2_mbox_iva_priv,
361 };
362 #endif
363
364 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
365 {
366 struct resource *res;
367 int ret;
368
369 /* MBOX base */
370 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
371 if (unlikely(!res)) {
372 dev_err(&pdev->dev, "invalid mem resource\n");
373 return -ENODEV;
374 }
375 mbox_base = ioremap(res->start, resource_size(res));
376 if (!mbox_base)
377 return -ENOMEM;
378
379 /* DSP or IVA2 IRQ */
380 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
381
382 if (unlikely(!res)) {
383 dev_err(&pdev->dev, "invalid irq resource\n");
384 ret = -ENODEV;
385 goto err_dsp;
386 }
387 if (cpu_is_omap44xx()) {
388 mbox_1_info.irq = res->start;
389 ret = omap_mbox_register(&pdev->dev, &mbox_1_info);
390 } else {
391 mbox_dsp_info.irq = res->start;
392 ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
393 }
394 if (ret)
395 goto err_dsp;
396
397 if (cpu_is_omap44xx()) {
398 mbox_2_info.irq = res->start;
399 ret = omap_mbox_register(&pdev->dev, &mbox_2_info);
400 if (ret) {
401 omap_mbox_unregister(&mbox_1_info);
402 goto err_dsp;
403 }
404 }
405 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
406 if (cpu_is_omap2420()) {
407 /* IVA IRQ */
408 res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
409 if (unlikely(!res)) {
410 dev_err(&pdev->dev, "invalid irq resource\n");
411 ret = -ENODEV;
412 goto err_iva1;
413 }
414 mbox_iva_info.irq = res->start;
415 ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
416 if (ret)
417 goto err_iva1;
418 }
419 #endif
420 return 0;
421
422 err_iva1:
423 omap_mbox_unregister(&mbox_dsp_info);
424
425 err_dsp:
426 iounmap(mbox_base);
427 return ret;
428 }
429
430 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
431 {
432 #if defined(CONFIG_ARCH_OMAP2420)
433 omap_mbox_unregister(&mbox_iva_info);
434 #endif
435
436 if (cpu_is_omap44xx()) {
437 omap_mbox_unregister(&mbox_2_info);
438 omap_mbox_unregister(&mbox_1_info);
439 } else
440 omap_mbox_unregister(&mbox_dsp_info);
441 iounmap(mbox_base);
442 return 0;
443 }
444
445 static struct platform_driver omap2_mbox_driver = {
446 .probe = omap2_mbox_probe,
447 .remove = __devexit_p(omap2_mbox_remove),
448 .driver = {
449 .name = DRV_NAME,
450 },
451 };
452
453 static int __init omap2_mbox_init(void)
454 {
455 return platform_driver_register(&omap2_mbox_driver);
456 }
457
458 static void __exit omap2_mbox_exit(void)
459 {
460 platform_driver_unregister(&omap2_mbox_driver);
461 }
462
463 module_init(omap2_mbox_init);
464 module_exit(omap2_mbox_exit);
465
466 MODULE_LICENSE("GPL v2");
467 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
468 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
469 MODULE_ALIAS("platform:"DRV_NAME);