arch/arm/mach-s5pc100/include/mach/map.h

   1 /* linux/arch/arm/mach-s5pc100/include/mach/map.h
   2  *
   3  * Copyright 2009 Samsung Electronics Co.
   4  *      Byungho Min <bhmin@samsung.com>
   5  *
   6  * Based on mach-s3c6400/include/mach/map.h
   7  *
   8  * S5PC1XX - Memory map definitions
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #ifndef __ASM_ARCH_MAP_H
  16 #define __ASM_ARCH_MAP_H __FILE__
  17
  18 #include <plat/map-base.h>
  19
  20 /*
  21  * map-base.h has already defined virtual memory address
  22  * S3C_VA_IRQ           S3C_ADDR(0x00000000)    irq controller(s)
  23  * S3C_VA_SYS           S3C_ADDR(0x00100000)    system control
  24  * S3C_VA_MEM           S3C_ADDR(0x00200000)    system control (not used)
  25  * S3C_VA_TIMER         S3C_ADDR(0x00300000)    timer block
  26  * S3C_VA_WATCHDOG      S3C_ADDR(0x00400000)    watchdog
  27  * S3C_VA_UART          S3C_ADDR(0x01000000)    UART
  28  *
  29  * S5PC100 specific virtual memory address can be defined here
  30  * S5PC1XX_VA_GPIO      S3C_ADDR(0x00500000)    GPIO
  31  *
  32  */
  33
  34 /* Chip ID */
  35 #define S5PC100_PA_CHIPID       (0xE0000000)
  36 #define S5PC1XX_PA_CHIPID       S5PC100_PA_CHIPID
  37 #define S5PC1XX_VA_CHIPID       S3C_VA_SYS
  38
  39 /* System */
  40 #define S5PC100_PA_CLK          (0xE0100000)
  41 #define S5PC100_PA_CLK_OTHER    (0xE0200000)
  42 #define S5PC100_PA_PWR          (0xE0108000)
  43 #define S5PC1XX_PA_CLK          S5PC100_PA_CLK
  44 #define S5PC1XX_PA_PWR          S5PC100_PA_PWR
  45 #define S5PC1XX_PA_CLK_OTHER    S5PC100_PA_CLK_OTHER
  46 #define S5PC1XX_VA_CLK          (S3C_VA_SYS + 0x10000)
  47 #define S5PC1XX_VA_PWR          (S3C_VA_SYS + 0x20000)
  48 #define S5PC1XX_VA_CLK_OTHER    (S3C_VA_SYS + 0x30000)
  49
  50 /* GPIO */
  51 #define S5PC100_PA_GPIO         (0xE0300000)
  52 #define S5PC1XX_PA_GPIO         S5PC100_PA_GPIO
  53 #define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
  54
  55 /* Interrupt */
  56 #define S5PC100_PA_VIC          (0xE4000000)
  57 #define S5PC100_VA_VIC          S3C_VA_IRQ
  58 #define S5PC100_PA_VIC_OFFSET   0x100000
  59 #define S5PC100_VA_VIC_OFFSET   0x10000
  60 #define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
  61 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
  62
  63 /* DMA */
  64 #define S5PC100_PA_MDMA         (0xE8100000)
  65 #define S5PC100_PA_PDMA0        (0xE9000000)
  66 #define S5PC100_PA_PDMA1        (0xE9200000)
  67
  68 /* Timer */
  69 #define S5PC100_PA_TIMER        (0xEA000000)
  70 #define S5PC1XX_PA_TIMER        S5PC100_PA_TIMER
  71 #define S5PC1XX_VA_TIMER        S3C_VA_TIMER
  72
  73 /* RTC */
  74 #define S5PC100_PA_RTC          (0xEA300000)
  75
  76 /* UART */
  77 #define S5PC100_PA_UART         (0xEC000000)
  78 #define S5PC1XX_PA_UART         S5PC100_PA_UART
  79 #define S5PC1XX_VA_UART         S3C_VA_UART
  80
  81 /* I2C */
  82 #define S5PC100_PA_I2C          (0xEC100000)
  83 #define S5PC100_PA_I2C1         (0xEC200000)
  84
  85 /* USB HS OTG */
  86 #define S5PC100_PA_USB_HSOTG    (0xED200000)
  87 #define S5PC100_PA_USB_HSPHY    (0xED300000)
  88
  89 /* SD/MMC */
  90 #define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
  91 #define S5PC100_PA_HSMMC0       S5PC100_PA_HSMMC(0)
  92 #define S5PC100_PA_HSMMC1       S5PC100_PA_HSMMC(1)
  93 #define S5PC100_PA_HSMMC2       S5PC100_PA_HSMMC(2)
  94
  95 /* LCD */
  96 #define S5PC100_PA_FB           (0xEE000000)
  97
  98 /* Multimedia */
  99 #define S5PC100_PA_G2D          (0xEE800000)
 100 #define S5PC100_PA_JPEG         (0xEE500000)
 101 #define S5PC100_PA_ROTATOR      (0xEE100000)
 102 #define S5PC100_PA_G3D          (0xEF000000)
 103
 104 /* I2S */
 105 #define S5PC100_PA_I2S0         (0xF2000000)
 106 #define S5PC100_PA_I2S1         (0xF2100000)
 107 #define S5PC100_PA_I2S2         (0xF2200000)
 108
 109 /* KEYPAD */
 110 #define S5PC100_PA_KEYPAD       (0xF3100000)
 111
 112 /* ADC & TouchScreen */
 113 #define S5PC100_PA_TSADC        (0xF3000000)
 114
 115 /* ETC */
 116 #define S5PC100_PA_SDRAM        (0x20000000)
 117 #define S5PC1XX_PA_SDRAM        S5PC100_PA_SDRAM
 118
 119 /* compatibility defines. */
 120 #define S3C_PA_RTC              S5PC100_PA_RTC
 121 #define S3C_PA_UART             S5PC100_PA_UART
 122 #define S3C_PA_UART0            (S5PC100_PA_UART + 0x0)
 123 #define S3C_PA_UART1            (S5PC100_PA_UART + 0x400)
 124 #define S3C_PA_UART2            (S5PC100_PA_UART + 0x800)
 125 #define S3C_PA_UART3            (S5PC100_PA_UART + 0xC00)
 126 #define S3C_VA_UART0            (S3C_VA_UART + 0x0)
 127 #define S3C_VA_UART1            (S3C_VA_UART + 0x400)
 128 #define S3C_VA_UART2            (S3C_VA_UART + 0x800)
 129 #define S3C_VA_UART3            (S3C_VA_UART + 0xC00)
 130 #define S3C_UART_OFFSET         0x400
 131 #define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 132 #define S3C_PA_FB               S5PC100_PA_FB
 133 #define S3C_PA_G2D              S5PC100_PA_G2D
 134 #define S3C_PA_G3D              S5PC100_PA_G3D
 135 #define S3C_PA_JPEG             S5PC100_PA_JPEG
 136 #define S3C_PA_ROTATOR          S5PC100_PA_ROTATOR
 137 #define S3C_VA_VIC0             (S3C_VA_IRQ + 0x0)
 138 #define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
 139 #define S3C_VA_VIC2             (S3C_VA_IRQ + 0x20000)
 140 #define S3C_PA_IIC              S5PC100_PA_I2C
 141 #define S3C_PA_IIC1             S5PC100_PA_I2C1
 142 #define S3C_PA_USB_HSOTG        S5PC100_PA_USB_HSOTG
 143 #define S3C_PA_USB_HSPHY        S5PC100_PA_USB_HSPHY
 144 #define S3C_PA_HSMMC0           S5PC100_PA_HSMMC0
 145 #define S3C_PA_HSMMC1           S5PC100_PA_HSMMC1
 146 #define S3C_PA_HSMMC2           S5PC100_PA_HSMMC2
 147 #define S3C_PA_KEYPAD           S5PC100_PA_KEYPAD
 148 #define S3C_PA_TSADC            S5PC100_PA_TSADC
 149
 150 #endif /* __ASM_ARCH_C100_MAP_H */