drivers/spi/xilinx_spi.c

   1 /*
   2  * xilinx_spi.c
   3  *
   4  * Xilinx SPI controller driver (master mode only)
   5  *
   6  * Author: MontaVista Software, Inc.
   7  *      source@mvista.com
   8  *
   9  * 2002-2007 (c) MontaVista Software, Inc.  This file is licensed under the
  10  * terms of the GNU General Public License version 2.  This program is licensed
  11  * "as is" without any warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17
  18 #include <linux/spi/spi.h>
  19 #include <linux/spi/spi_bitbang.h>
  20 #include <linux/io.h>
  21
  22 #include "xilinx_spi.h"
  23 #include <linux/spi/xilinx_spi.h>
  24
  25 #define XILINX_SPI_NAME "xilinx_spi"
  26
  27 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
  28  * Product Specification", DS464
  29  */
  30 #define XSPI_CR_OFFSET          0x60    /* Control Register */
  31
  32 #define XSPI_CR_ENABLE          0x02
  33 #define XSPI_CR_MASTER_MODE     0x04
  34 #define XSPI_CR_CPOL            0x08
  35 #define XSPI_CR_CPHA            0x10
  36 #define XSPI_CR_MODE_MASK       (XSPI_CR_CPHA | XSPI_CR_CPOL)
  37 #define XSPI_CR_TXFIFO_RESET    0x20
  38 #define XSPI_CR_RXFIFO_RESET    0x40
  39 #define XSPI_CR_MANUAL_SSELECT  0x80
  40 #define XSPI_CR_TRANS_INHIBIT   0x100
  41 #define XSPI_CR_LSB_FIRST       0x200
  42
  43 #define XSPI_SR_OFFSET          0x64    /* Status Register */
  44
  45 #define XSPI_SR_RX_EMPTY_MASK   0x01    /* Receive FIFO is empty */
  46 #define XSPI_SR_RX_FULL_MASK    0x02    /* Receive FIFO is full */
  47 #define XSPI_SR_TX_EMPTY_MASK   0x04    /* Transmit FIFO is empty */
  48 #define XSPI_SR_TX_FULL_MASK    0x08    /* Transmit FIFO is full */
  49 #define XSPI_SR_MODE_FAULT_MASK 0x10    /* Mode fault error */
  50
  51 #define XSPI_TXD_OFFSET         0x68    /* Data Transmit Register */
  52 #define XSPI_RXD_OFFSET         0x6c    /* Data Receive Register */
  53
  54 #define XSPI_SSR_OFFSET         0x70    /* 32-bit Slave Select Register */
  55
  56 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
  57  * IPIF registers are 32 bit
  58  */
  59 #define XIPIF_V123B_DGIER_OFFSET        0x1c    /* IPIF global int enable reg */
  60 #define XIPIF_V123B_GINTR_ENABLE        0x80000000
  61
  62 #define XIPIF_V123B_IISR_OFFSET         0x20    /* IPIF interrupt status reg */
  63 #define XIPIF_V123B_IIER_OFFSET         0x28    /* IPIF interrupt enable reg */
  64
  65 #define XSPI_INTR_MODE_FAULT            0x01    /* Mode fault error */
  66 #define XSPI_INTR_SLAVE_MODE_FAULT      0x02    /* Selected as slave while
  67                                                  * disabled */
  68 #define XSPI_INTR_TX_EMPTY              0x04    /* TxFIFO is empty */
  69 #define XSPI_INTR_TX_UNDERRUN           0x08    /* TxFIFO was underrun */
  70 #define XSPI_INTR_RX_FULL               0x10    /* RxFIFO is full */
  71 #define XSPI_INTR_RX_OVERRUN            0x20    /* RxFIFO was overrun */
  72 #define XSPI_INTR_TX_HALF_EMPTY         0x40    /* TxFIFO is half empty */
  73
  74 #define XIPIF_V123B_RESETR_OFFSET       0x40    /* IPIF reset register */
  75 #define XIPIF_V123B_RESET_MASK          0x0a    /* the value to write */
  76
  77 struct xilinx_spi {
  78         /* bitbang has to be first */
  79         struct spi_bitbang bitbang;
  80         struct completion done;
  81         struct resource mem; /* phys mem */
  82         void __iomem    *regs;  /* virt. address of the control registers */
  83
  84         u32             irq;
  85
  86         u8 *rx_ptr;             /* pointer in the Tx buffer */
  87         const u8 *tx_ptr;       /* pointer in the Rx buffer */
  88         int remaining_bytes;    /* the number of bytes left to transfer */
  89         u8 bits_per_word;
  90         unsigned int (*read_fn) (void __iomem *);
  91         void (*write_fn) (u32, void __iomem *);
  92         void (*tx_fn) (struct xilinx_spi *);
  93         void (*rx_fn) (struct xilinx_spi *);
  94 };
  95
  96 static void xspi_tx8(struct xilinx_spi *xspi)
  97 {
  98         xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
  99         xspi->tx_ptr++;
 100 }
 101
 102 static void xspi_tx16(struct xilinx_spi *xspi)
 103 {
 104         xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
 105         xspi->tx_ptr += 2;
 106 }
 107
 108 static void xspi_tx32(struct xilinx_spi *xspi)
 109 {
 110         xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
 111         xspi->tx_ptr += 4;
 112 }
 113
 114 static void xspi_rx8(struct xilinx_spi *xspi)
 115 {
 116         u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
 117         if (xspi->rx_ptr) {
 118                 *xspi->rx_ptr = data & 0xff;
 119                 xspi->rx_ptr++;
 120         }
 121 }
 122
 123 static void xspi_rx16(struct xilinx_spi *xspi)
 124 {
 125         u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
 126         if (xspi->rx_ptr) {
 127                 *(u16 *)(xspi->rx_ptr) = data & 0xffff;
 128                 xspi->rx_ptr += 2;
 129         }
 130 }
 131
 132 static void xspi_rx32(struct xilinx_spi *xspi)
 133 {
 134         u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
 135         if (xspi->rx_ptr) {
 136                 *(u32 *)(xspi->rx_ptr) = data;
 137                 xspi->rx_ptr += 4;
 138         }
 139 }
 140
 141 static void xspi_init_hw(struct xilinx_spi *xspi)
 142 {
 143         void __iomem *regs_base = xspi->regs;
 144
 145         /* Reset the SPI device */
 146         xspi->write_fn(XIPIF_V123B_RESET_MASK,
 147                 regs_base + XIPIF_V123B_RESETR_OFFSET);
 148         /* Disable all the interrupts just in case */
 149         xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
 150         /* Enable the global IPIF interrupt */
 151         xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
 152                 regs_base + XIPIF_V123B_DGIER_OFFSET);
 153         /* Deselect the slave on the SPI bus */
 154         xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
 155         /* Disable the transmitter, enable Manual Slave Select Assertion,
 156          * put SPI controller into master mode, and enable it */
 157         xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
 158                 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
 159                 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
 160 }
 161
 162 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
 163 {
 164         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
 165
 166         if (is_on == BITBANG_CS_INACTIVE) {
 167                 /* Deselect the slave on the SPI bus */
 168                 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
 169         } else if (is_on == BITBANG_CS_ACTIVE) {
 170                 /* Set the SPI clock phase and polarity */
 171                 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
 172                          & ~XSPI_CR_MODE_MASK;
 173                 if (spi->mode & SPI_CPHA)
 174                         cr |= XSPI_CR_CPHA;
 175                 if (spi->mode & SPI_CPOL)
 176                         cr |= XSPI_CR_CPOL;
 177                 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
 178
 179                 /* We do not check spi->max_speed_hz here as the SPI clock
 180                  * frequency is not software programmable (the IP block design
 181                  * parameter)
 182                  */
 183
 184                 /* Activate the chip select */
 185                 xspi->write_fn(~(0x0001 << spi->chip_select),
 186                         xspi->regs + XSPI_SSR_OFFSET);
 187         }
 188 }
 189
 190 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
 191  * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
 192  * supports 8 or 16 bits per word which cannot be changed in software.
 193  * SPI clock can't be changed in software either.
 194  * Check for correct bits per word. Chip select delay calculations could be
 195  * added here as soon as bitbang_work() can be made aware of the delay value.
 196  */
 197 static int xilinx_spi_setup_transfer(struct spi_device *spi,
 198                 struct spi_transfer *t)
 199 {
 200         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
 201         u8 bits_per_word;
 202
 203         bits_per_word = (t && t->bits_per_word)
 204                          ? t->bits_per_word : spi->bits_per_word;
 205         if (bits_per_word != xspi->bits_per_word) {
 206                 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 207                         __func__, bits_per_word);
 208                 return -EINVAL;
 209         }
 210
 211         return 0;
 212 }
 213
 214 static int xilinx_spi_setup(struct spi_device *spi)
 215 {
 216         /* always return 0, we can not check the number of bits.
 217          * There are cases when SPI setup is called before any driver is
 218          * there, in that case the SPI core defaults to 8 bits, which we
 219          * do not support in some cases. But if we return an error, the
 220          * SPI device would not be registered and no driver can get hold of it
 221          * When the driver is there, it will call SPI setup again with the
 222          * correct number of bits per transfer.
 223          * If a driver setups with the wrong bit number, it will fail when
 224          * it tries to do a transfer
 225          */
 226         return 0;
 227 }
 228
 229 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
 230 {
 231         u8 sr;
 232
 233         /* Fill the Tx FIFO with as many bytes as possible */
 234         sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
 235         while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
 236                 if (xspi->tx_ptr)
 237                         xspi->tx_fn(xspi);
 238                 else
 239                         xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
 240                 xspi->remaining_bytes -= xspi->bits_per_word / 8;
 241                 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
 242         }
 243 }
 244
 245 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 246 {
 247         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
 248         u32 ipif_ier;
 249         u16 cr;
 250
 251         /* We get here with transmitter inhibited */
 252
 253         xspi->tx_ptr = t->tx_buf;
 254         xspi->rx_ptr = t->rx_buf;
 255         xspi->remaining_bytes = t->len;
 256         INIT_COMPLETION(xspi->done);
 257
 258         xilinx_spi_fill_tx_fifo(xspi);
 259
 260         /* Enable the transmit empty interrupt, which we use to determine
 261          * progress on the transmission.
 262          */
 263         ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
 264         xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
 265                 xspi->regs + XIPIF_V123B_IIER_OFFSET);
 266
 267         /* Start the transfer by not inhibiting the transmitter any longer */
 268         cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
 269                 ~XSPI_CR_TRANS_INHIBIT;
 270         xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
 271
 272         wait_for_completion(&xspi->done);
 273
 274         /* Disable the transmit empty interrupt */
 275         xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
 276
 277         return t->len - xspi->remaining_bytes;
 278 }
 279
 280
 281 /* This driver supports single master mode only. Hence Tx FIFO Empty
 282  * is the only interrupt we care about.
 283  * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
 284  * Fault are not to happen.
 285  */
 286 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
 287 {
 288         struct xilinx_spi *xspi = dev_id;
 289         u32 ipif_isr;
 290
 291         /* Get the IPIF interrupts, and clear them immediately */
 292         ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
 293         xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
 294
 295         if (ipif_isr & XSPI_INTR_TX_EMPTY) {    /* Transmission completed */
 296                 u16 cr;
 297                 u8 sr;
 298
 299                 /* A transmit has just completed. Process received data and
 300                  * check for more data to transmit. Always inhibit the
 301                  * transmitter while the Isr refills the transmit register/FIFO,
 302                  * or make sure it is stopped if we're done.
 303                  */
 304                 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
 305                 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
 306                         xspi->regs + XSPI_CR_OFFSET);
 307
 308                 /* Read out all the data from the Rx FIFO */
 309                 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
 310                 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
 311                         xspi->rx_fn(xspi);
 312                         sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
 313                 }
 314
 315                 /* See if there is more data to send */
 316                 if (xspi->remaining_bytes > 0) {
 317                         xilinx_spi_fill_tx_fifo(xspi);
 318                         /* Start the transfer by not inhibiting the
 319                          * transmitter any longer
 320                          */
 321                         xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
 322                 } else {
 323                         /* No more data to send.
 324                          * Indicate the transfer is completed.
 325                          */
 326                         complete(&xspi->done);
 327                 }
 328         }
 329
 330         return IRQ_HANDLED;
 331 }
 332
 333 struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
 334         u32 irq, s16 bus_num)
 335 {
 336         struct spi_master *master;
 337         struct xilinx_spi *xspi;
 338         struct xspi_platform_data *pdata = dev->platform_data;
 339         int ret;
 340
 341         if (!pdata) {
 342                 dev_err(dev, "No platform data attached\n");
 343                 return NULL;
 344         }
 345
 346         master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
 347         if (!master)
 348                 return NULL;
 349
 350         /* the spi->mode bits understood by this driver: */
 351         master->mode_bits = SPI_CPOL | SPI_CPHA;
 352
 353         xspi = spi_master_get_devdata(master);
 354         xspi->bitbang.master = spi_master_get(master);
 355         xspi->bitbang.chipselect = xilinx_spi_chipselect;
 356         xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
 357         xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
 358         xspi->bitbang.master->setup = xilinx_spi_setup;
 359         init_completion(&xspi->done);
 360
 361         if (!request_mem_region(mem->start, resource_size(mem),
 362                 XILINX_SPI_NAME))
 363                 goto put_master;
 364
 365         xspi->regs = ioremap(mem->start, resource_size(mem));
 366         if (xspi->regs == NULL) {
 367                 dev_warn(dev, "ioremap failure\n");
 368                 goto map_failed;
 369         }
 370
 371         master->bus_num = bus_num;
 372         master->num_chipselect = pdata->num_chipselect;
 373
 374         xspi->mem = *mem;
 375         xspi->irq = irq;
 376         if (pdata->little_endian) {
 377                 xspi->read_fn = ioread32;
 378                 xspi->write_fn = iowrite32;
 379         } else {
 380                 xspi->read_fn = ioread32be;
 381                 xspi->write_fn = iowrite32be;
 382         }
 383         xspi->bits_per_word = pdata->bits_per_word;
 384         if (xspi->bits_per_word == 8) {
 385                 xspi->tx_fn = xspi_tx8;
 386                 xspi->rx_fn = xspi_rx8;
 387         } else if (xspi->bits_per_word == 16) {
 388                 xspi->tx_fn = xspi_tx16;
 389                 xspi->rx_fn = xspi_rx16;
 390         } else if (xspi->bits_per_word == 32) {
 391                 xspi->tx_fn = xspi_tx32;
 392                 xspi->rx_fn = xspi_rx32;
 393         } else
 394                 goto unmap_io;
 395
 396
 397         /* SPI controller initializations */
 398         xspi_init_hw(xspi);
 399
 400         /* Register for SPI Interrupt */
 401         ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
 402         if (ret)
 403                 goto unmap_io;
 404
 405         ret = spi_bitbang_start(&xspi->bitbang);
 406         if (ret) {
 407                 dev_err(dev, "spi_bitbang_start FAILED\n");
 408                 goto free_irq;
 409         }
 410
 411         dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
 412                 (unsigned long long)mem->start, xspi->regs, xspi->irq);
 413         return master;
 414
 415 free_irq:
 416         free_irq(xspi->irq, xspi);
 417 unmap_io:
 418         iounmap(xspi->regs);
 419 map_failed:
 420         release_mem_region(mem->start, resource_size(mem));
 421 put_master:
 422         spi_master_put(master);
 423         return NULL;
 424 }
 425 EXPORT_SYMBOL(xilinx_spi_init);
 426
 427 void xilinx_spi_deinit(struct spi_master *master)
 428 {
 429         struct xilinx_spi *xspi;
 430
 431         xspi = spi_master_get_devdata(master);
 432
 433         spi_bitbang_stop(&xspi->bitbang);
 434         free_irq(xspi->irq, xspi);
 435         iounmap(xspi->regs);
 436
 437         release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
 438         spi_master_put(xspi->bitbang.master);
 439 }
 440 EXPORT_SYMBOL(xilinx_spi_deinit);
 441
 442 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
 443 MODULE_DESCRIPTION("Xilinx SPI driver");
 444 MODULE_LICENSE("GPL");