2 * Alpha specific irq code.
5 #include <linux/init.h>
6 #include <linux/sched.h>
8 #include <linux/kernel_stat.h>
10 #include <asm/machvec.h>
16 /* Hack minimum IPL during interrupt processing for broken hardware. */
17 #ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK
22 * Performance counter hook. A module can override this to
23 * do something useful.
26 dummy_perf(unsigned long vector
, struct pt_regs
*regs
)
29 printk(KERN_CRIT
"Performance counter interrupt!\n");
32 void (*perf_irq
)(unsigned long, struct pt_regs
*) = dummy_perf
;
35 * The main interrupt entry point.
39 do_entInt(unsigned long type
, unsigned long vector
,
40 unsigned long la_ptr
, struct pt_regs
*regs
)
49 printk(KERN_CRIT
"Interprocessor interrupt? "
50 "You must be kidding!\n");
59 smp_percpu_timer_interrupt(regs
);
60 cpu
= smp_processor_id();
61 if (cpu
!= boot_cpuid
) {
62 kstat_cpu(cpu
).irqs
[RTC_IRQ
]++;
64 handle_irq(RTC_IRQ
, regs
);
68 handle_irq(RTC_IRQ
, regs
);
72 alpha_mv
.machine_check(vector
, la_ptr
, regs
);
75 alpha_mv
.device_interrupt(vector
, regs
);
78 perf_irq(la_ptr
, regs
);
81 printk(KERN_CRIT
"Hardware intr %ld %lx? Huh?\n",
84 printk(KERN_CRIT
"PC = %016lx PS=%04lx\n", regs
->pc
, regs
->ps
);
88 common_init_isa_dma(void)
90 outb(0, DMA1_RESET_REG
);
91 outb(0, DMA2_RESET_REG
);
92 outb(0, DMA1_CLR_MASK_REG
);
93 outb(0, DMA2_CLR_MASK_REG
);
99 /* Just in case the platform init_irq() causes interrupts/mchecks
100 (as is the case with RAWHIDE, at least). */
107 * machine error checks
109 #define MCHK_K_TPERR 0x0080
110 #define MCHK_K_TCPERR 0x0082
111 #define MCHK_K_HERR 0x0084
112 #define MCHK_K_ECC_C 0x0086
113 #define MCHK_K_ECC_NC 0x0088
114 #define MCHK_K_OS_BUGCHECK 0x008A
115 #define MCHK_K_PAL_BUGCHECK 0x0090
118 struct mcheck_info __mcheck_info
;
122 process_mcheck_info(unsigned long vector
, unsigned long la_ptr
,
123 struct pt_regs
*regs
, const char *machine
,
126 struct el_common
*mchk_header
;
130 * See if the machine check is due to a badaddr() and if so,
134 #ifdef CONFIG_VERBOSE_MCHECK
135 if (alpha_verbose_mcheck
> 1) {
136 printk(KERN_CRIT
"%s machine check %s\n", machine
,
137 expected
? "expected." : "NOT expected!!!");
142 int cpu
= smp_processor_id();
143 mcheck_expected(cpu
) = 0;
144 mcheck_taken(cpu
) = 1;
148 mchk_header
= (struct el_common
*)la_ptr
;
150 printk(KERN_CRIT
"%s machine check: vector=0x%lx pc=0x%lx code=0x%x\n",
151 machine
, vector
, regs
->pc
, mchk_header
->code
);
153 switch (mchk_header
->code
) {
154 /* Machine check reasons. Defined according to PALcode sources. */
155 case 0x80: reason
= "tag parity error"; break;
156 case 0x82: reason
= "tag control parity error"; break;
157 case 0x84: reason
= "generic hard error"; break;
158 case 0x86: reason
= "correctable ECC error"; break;
159 case 0x88: reason
= "uncorrectable ECC error"; break;
160 case 0x8A: reason
= "OS-specific PAL bugcheck"; break;
161 case 0x90: reason
= "callsys in kernel mode"; break;
162 case 0x96: reason
= "i-cache read retryable error"; break;
163 case 0x98: reason
= "processor detected hard error"; break;
165 /* System specific (these are for Alcor, at least): */
166 case 0x202: reason
= "system detected hard error"; break;
167 case 0x203: reason
= "system detected uncorrectable ECC error"; break;
168 case 0x204: reason
= "SIO SERR occurred on PCI bus"; break;
169 case 0x205: reason
= "parity error detected by core logic"; break;
170 case 0x206: reason
= "SIO IOCHK occurred on ISA bus"; break;
171 case 0x207: reason
= "non-existent memory error"; break;
172 case 0x208: reason
= "MCHK_K_DCSR"; break;
173 case 0x209: reason
= "PCI SERR detected"; break;
174 case 0x20b: reason
= "PCI data parity error detected"; break;
175 case 0x20d: reason
= "PCI address parity error detected"; break;
176 case 0x20f: reason
= "PCI master abort error"; break;
177 case 0x211: reason
= "PCI target abort error"; break;
178 case 0x213: reason
= "scatter/gather PTE invalid error"; break;
179 case 0x215: reason
= "flash ROM write error"; break;
180 case 0x217: reason
= "IOA timeout detected"; break;
181 case 0x219: reason
= "IOCHK#, EISA add-in board parity or other catastrophic error"; break;
182 case 0x21b: reason
= "EISA fail-safe timer timeout"; break;
183 case 0x21d: reason
= "EISA bus time-out"; break;
184 case 0x21f: reason
= "EISA software generated NMI"; break;
185 case 0x221: reason
= "unexpected ev5 IRQ[3] interrupt"; break;
186 default: reason
= "unknown"; break;
189 printk(KERN_CRIT
"machine check type: %s%s\n",
190 reason
, mchk_header
->retry
? " (retryable)" : "");
192 dik_show_regs(regs
, NULL
);
194 #ifdef CONFIG_VERBOSE_MCHECK
195 if (alpha_verbose_mcheck
> 1) {
196 /* Dump the logout area to give all info. */
197 unsigned long *ptr
= (unsigned long *)la_ptr
;
199 for (i
= 0; i
< mchk_header
->size
/ sizeof(long); i
+= 2) {
200 printk(KERN_CRIT
" +%8lx %016lx %016lx\n",
201 i
*sizeof(long), ptr
[i
], ptr
[i
+1]);
204 #endif /* CONFIG_VERBOSE_MCHECK */
208 * The special RTC interrupt type. The interrupt itself was
209 * processed by PALcode, and comes in via entInt vector 1.
212 static void rtc_enable_disable(unsigned int irq
) { }
213 static unsigned int rtc_startup(unsigned int irq
) { return 0; }
215 struct irqaction timer_irqaction
= {
216 .handler
= timer_interrupt
,
217 .flags
= IRQF_DISABLED
,
221 static struct hw_interrupt_type rtc_irq_type
= {
223 .startup
= rtc_startup
,
224 .shutdown
= rtc_enable_disable
,
225 .enable
= rtc_enable_disable
,
226 .disable
= rtc_enable_disable
,
227 .ack
= rtc_enable_disable
,
228 .end
= rtc_enable_disable
,
234 irq_desc
[RTC_IRQ
].status
= IRQ_DISABLED
;
235 irq_desc
[RTC_IRQ
].chip
= &rtc_irq_type
;
236 setup_irq(RTC_IRQ
, &timer_irqaction
);
239 /* Dummy irqactions. */
240 struct irqaction isa_cascade_irqaction
= {
241 .handler
= no_action
,
242 .name
= "isa-cascade"
245 struct irqaction timer_cascade_irqaction
= {
246 .handler
= no_action
,
247 .name
= "timer-cascade"
250 struct irqaction halt_switch_irqaction
= {
251 .handler
= no_action
,
252 .name
= "halt-switch"