drivers/mmc/sdhci.h

   1 /*
   2  *  linux/drivers/mmc/sdhci.h - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 /*
  12  * PCI registers
  13  */
  14
  15 #define PCI_SDHCI_IFPIO                 0x00
  16 #define PCI_SDHCI_IFDMA                 0x01
  17 #define PCI_SDHCI_IFVENDOR              0x02
  18
  19 #define PCI_SLOT_INFO                   0x40    /* 8 bits */
  20 #define  PCI_SLOT_INFO_SLOTS(x)         ((x >> 4) & 7)
  21 #define  PCI_SLOT_INFO_FIRST_BAR_MASK   0x07
  22
  23 /*
  24  * Controller registers
  25  */
  26
  27 #define SDHCI_DMA_ADDRESS       0x00
  28
  29 #define SDHCI_BLOCK_SIZE        0x04
  30 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  31
  32 #define SDHCI_BLOCK_COUNT       0x06
  33
  34 #define SDHCI_ARGUMENT          0x08
  35
  36 #define SDHCI_TRANSFER_MODE     0x0C
  37 #define  SDHCI_TRNS_DMA         0x01
  38 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
  39 #define  SDHCI_TRNS_ACMD12      0x04
  40 #define  SDHCI_TRNS_READ        0x10
  41 #define  SDHCI_TRNS_MULTI       0x20
  42
  43 #define SDHCI_COMMAND           0x0E
  44 #define  SDHCI_CMD_RESP_MASK    0x03
  45 #define  SDHCI_CMD_CRC          0x08
  46 #define  SDHCI_CMD_INDEX        0x10
  47 #define  SDHCI_CMD_DATA         0x20
  48
  49 #define  SDHCI_CMD_RESP_NONE    0x00
  50 #define  SDHCI_CMD_RESP_LONG    0x01
  51 #define  SDHCI_CMD_RESP_SHORT   0x02
  52 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  53
  54 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  55
  56 #define SDHCI_RESPONSE          0x10
  57
  58 #define SDHCI_BUFFER            0x20
  59
  60 #define SDHCI_PRESENT_STATE     0x24
  61 #define  SDHCI_CMD_INHIBIT      0x00000001
  62 #define  SDHCI_DATA_INHIBIT     0x00000002
  63 #define  SDHCI_DOING_WRITE      0x00000100
  64 #define  SDHCI_DOING_READ       0x00000200
  65 #define  SDHCI_SPACE_AVAILABLE  0x00000400
  66 #define  SDHCI_DATA_AVAILABLE   0x00000800
  67 #define  SDHCI_CARD_PRESENT     0x00010000
  68 #define  SDHCI_WRITE_PROTECT    0x00080000
  69
  70 #define SDHCI_HOST_CONTROL      0x28
  71 #define  SDHCI_CTRL_LED         0x01
  72 #define  SDHCI_CTRL_4BITBUS     0x02
  73
  74 #define SDHCI_POWER_CONTROL     0x29
  75 #define  SDHCI_POWER_ON         0x01
  76 #define  SDHCI_POWER_180        0x0A
  77 #define  SDHCI_POWER_300        0x0C
  78 #define  SDHCI_POWER_330        0x0E
  79
  80 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  81
  82 #define SDHCI_WALK_UP_CONTROL   0x2B
  83
  84 #define SDHCI_CLOCK_CONTROL     0x2C
  85 #define  SDHCI_DIVIDER_SHIFT    8
  86 #define  SDHCI_CLOCK_CARD_EN    0x0004
  87 #define  SDHCI_CLOCK_INT_STABLE 0x0002
  88 #define  SDHCI_CLOCK_INT_EN     0x0001
  89
  90 #define SDHCI_TIMEOUT_CONTROL   0x2E
  91
  92 #define SDHCI_SOFTWARE_RESET    0x2F
  93 #define  SDHCI_RESET_ALL        0x01
  94 #define  SDHCI_RESET_CMD        0x02
  95 #define  SDHCI_RESET_DATA       0x04
  96
  97 #define SDHCI_INT_STATUS        0x30
  98 #define SDHCI_INT_ENABLE        0x34
  99 #define SDHCI_SIGNAL_ENABLE     0x38
 100 #define  SDHCI_INT_RESPONSE     0x00000001
 101 #define  SDHCI_INT_DATA_END     0x00000002
 102 #define  SDHCI_INT_DMA_END      0x00000008
 103 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
 104 #define  SDHCI_INT_DATA_AVAIL   0x00000020
 105 #define  SDHCI_INT_CARD_INSERT  0x00000040
 106 #define  SDHCI_INT_CARD_REMOVE  0x00000080
 107 #define  SDHCI_INT_CARD_INT     0x00000100
 108 #define  SDHCI_INT_TIMEOUT      0x00010000
 109 #define  SDHCI_INT_CRC          0x00020000
 110 #define  SDHCI_INT_END_BIT      0x00040000
 111 #define  SDHCI_INT_INDEX        0x00080000
 112 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
 113 #define  SDHCI_INT_DATA_CRC     0x00200000
 114 #define  SDHCI_INT_DATA_END_BIT 0x00400000
 115 #define  SDHCI_INT_BUS_POWER    0x00800000
 116 #define  SDHCI_INT_ACMD12ERR    0x01000000
 117
 118 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 119 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 120
 121 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 122                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 123 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 124                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 125                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 126                 SDHCI_INT_DATA_END_BIT)
 127
 128 #define SDHCI_ACMD12_ERR        0x3C
 129
 130 /* 3E-3F reserved */
 131
 132 #define SDHCI_CAPABILITIES      0x40
 133 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 134 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 135 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 136 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 137 #define  SDHCI_CLOCK_BASE_SHIFT 8
 138 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 139 #define  SDHCI_MAX_BLOCK_SHIFT  16
 140 #define  SDHCI_CAN_DO_DMA       0x00400000
 141 #define  SDHCI_CAN_VDD_330      0x01000000
 142 #define  SDHCI_CAN_VDD_300      0x02000000
 143 #define  SDHCI_CAN_VDD_180      0x04000000
 144
 145 /* 44-47 reserved for more caps */
 146
 147 #define SDHCI_MAX_CURRENT       0x48
 148
 149 /* 4C-4F reserved for more max current */
 150
 151 /* 50-FB reserved */
 152
 153 #define SDHCI_SLOT_INT_STATUS   0xFC
 154
 155 #define SDHCI_HOST_VERSION      0xFE
 156 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 157 #define  SDHCI_VENDOR_VER_SHIFT 8
 158 #define  SDHCI_SPEC_VER_MASK    0x00FF
 159 #define  SDHCI_SPEC_VER_SHIFT   0
 160
 161 struct sdhci_chip;
 162
 163 struct sdhci_host {
 164         struct sdhci_chip       *chip;
 165         struct mmc_host         *mmc;           /* MMC structure */
 166
 167         spinlock_t              lock;           /* Mutex */
 168
 169         int                     flags;          /* Host attributes */
 170 #define SDHCI_USE_DMA           (1<<0)
 171
 172         unsigned int            max_clk;        /* Max possible freq (MHz) */
 173         unsigned int            timeout_clk;    /* Timeout freq (KHz) */
 174         unsigned int            max_block;      /* Max block size (bytes) */
 175
 176         unsigned int            clock;          /* Current clock (MHz) */
 177         unsigned short          power;          /* Current voltage */
 178
 179         struct mmc_request      *mrq;           /* Current request */
 180         struct mmc_command      *cmd;           /* Current command */
 181         struct mmc_data         *data;          /* Current data request */
 182
 183         struct scatterlist      *cur_sg;        /* We're working on this */
 184         char                    *mapped_sg;     /* This is where it's mapped */
 185         int                     num_sg;         /* Entries left */
 186         int                     offset;         /* Offset into current sg */
 187         int                     remain;         /* Bytes left in current */
 188
 189         int                     size;           /* Remaining bytes in transfer */
 190
 191         char                    slot_descr[20]; /* Name for reservations */
 192
 193         int                     irq;            /* Device IRQ */
 194         int                     bar;            /* PCI BAR index */
 195         unsigned long           addr;           /* Bus address */
 196         void __iomem *          ioaddr;         /* Mapped address */
 197
 198         struct tasklet_struct   card_tasklet;   /* Tasklet structures */
 199         struct tasklet_struct   finish_tasklet;
 200
 201         struct timer_list       timer;          /* Timer for timeouts */
 202 };
 203
 204 struct sdhci_chip {
 205         struct pci_dev          *pdev;
 206
 207         unsigned long           quirks;
 208
 209         int                     num_slots;      /* Slots on controller */
 210         struct sdhci_host       *hosts[0];      /* Pointers to hosts */
 211 };