Linux 2.6.39-rc2
[pohmelfs.git] / arch / blackfin / include / asm / cache.h
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1 /*
2 * Copyright 2004-2009 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
5 */
7 #ifndef __ARCH_BLACKFIN_CACHE_H
8 #define __ARCH_BLACKFIN_CACHE_H
10 #include <linux/linkage.h> /* for asmlinkage */
13 * Bytes per L1 cache line
14 * Blackfin loads 32 bytes for cache
16 #define L1_CACHE_SHIFT 5
17 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
18 #define SMP_CACHE_BYTES L1_CACHE_BYTES
20 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
22 #ifdef CONFIG_SMP
23 #define __cacheline_aligned
24 #else
25 #define ____cacheline_aligned
28 * Put cacheline_aliged data to L1 data memory
30 #ifdef CONFIG_CACHELINE_ALIGNED_L1
31 #define __cacheline_aligned \
32 __attribute__((__aligned__(L1_CACHE_BYTES), \
33 __section__(".data_l1.cacheline_aligned")))
34 #endif
36 #endif
39 * largest L1 which this arch supports
41 #define L1_CACHE_SHIFT_MAX 5
43 #if defined(CONFIG_SMP) && \
44 !defined(CONFIG_BFIN_CACHE_COHERENT)
45 # if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
46 # define __ARCH_SYNC_CORE_ICACHE
47 # endif
48 # if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
49 # define __ARCH_SYNC_CORE_DCACHE
50 # endif
51 #ifndef __ASSEMBLY__
52 asmlinkage void __raw_smp_mark_barrier_asm(void);
53 asmlinkage void __raw_smp_check_barrier_asm(void);
55 static inline void smp_mark_barrier(void)
57 __raw_smp_mark_barrier_asm();
59 static inline void smp_check_barrier(void)
61 __raw_smp_check_barrier_asm();
64 void resync_core_dcache(void);
65 void resync_core_icache(void);
66 #endif
67 #endif
70 #endif