arch/blackfin/include/asm/cacheflush.h

   1 /*
   2  * Blackfin low-level cache routines
   3  *
   4  * Copyright 2004-2009 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #ifndef _BLACKFIN_CACHEFLUSH_H
  10 #define _BLACKFIN_CACHEFLUSH_H
  11
  12 #include <asm/blackfin.h>       /* for SSYNC() */
  13 #include <asm/sections.h>       /* for _ramend */
  14 #ifdef CONFIG_SMP
  15 #include <asm/smp.h>
  16 #endif
  17
  18 extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
  19 extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
  20 extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
  21 extern void blackfin_dflush_page(void *page);
  22 extern void blackfin_invalidate_entire_dcache(void);
  23 extern void blackfin_invalidate_entire_icache(void);
  24
  25 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
  26 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
  27 #define flush_cache_mm(mm)                      do { } while (0)
  28 #define flush_cache_range(vma, start, end)      do { } while (0)
  29 #define flush_cache_page(vma, vmaddr)           do { } while (0)
  30 #define flush_cache_vmap(start, end)            do { } while (0)
  31 #define flush_cache_vunmap(start, end)          do { } while (0)
  32
  33 #ifdef CONFIG_SMP
  34 #define flush_icache_range_others(start, end)   \
  35         smp_icache_flush_range_others((start), (end))
  36 #else
  37 #define flush_icache_range_others(start, end)   do { } while (0)
  38 #endif
  39
  40 static inline void flush_icache_range(unsigned start, unsigned end)
  41 {
  42 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
  43         blackfin_dcache_flush_range(start, end);
  44 #endif
  45
  46         /* Make sure all write buffers in the data side of the core
  47          * are flushed before trying to invalidate the icache.  This
  48          * needs to be after the data flush and before the icache
  49          * flush so that the SSYNC does the right thing in preventing
  50          * the instruction prefetcher from hitting things in cached
  51          * memory at the wrong time -- it runs much further ahead than
  52          * the pipeline.
  53          */
  54         SSYNC();
  55 #if defined(CONFIG_BFIN_ICACHE)
  56         blackfin_icache_flush_range(start, end);
  57         flush_icache_range_others(start, end);
  58 #endif
  59 }
  60
  61 #define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
  62 do { memcpy(dst, src, len);                                             \
  63      flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len));    \
  64 } while (0)
  65
  66 #define copy_from_user_page(vma, page, vaddr, dst, src, len)    memcpy(dst, src, len)
  67
  68 #if defined(CONFIG_BFIN_DCACHE)
  69 # define invalidate_dcache_range(start,end)     blackfin_dcache_invalidate_range((start), (end))
  70 #else
  71 # define invalidate_dcache_range(start,end)     do { } while (0)
  72 #endif
  73 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
  74 # define flush_dcache_range(start,end)          blackfin_dcache_flush_range((start), (end))
  75 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
  76 # define flush_dcache_page(page)                blackfin_dflush_page(page_address(page))
  77 #else
  78 # define flush_dcache_range(start,end)          do { } while (0)
  79 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
  80 # define flush_dcache_page(page)                do { } while (0)
  81 #endif
  82
  83 extern unsigned long reserved_mem_dcache_on;
  84 extern unsigned long reserved_mem_icache_on;
  85
  86 static inline int bfin_addr_dcacheable(unsigned long addr)
  87 {
  88 #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
  89         if (addr < (_ramend - DMA_UNCACHED_REGION))
  90                 return 1;
  91 #endif
  92
  93         if (reserved_mem_dcache_on &&
  94                 addr >= _ramend && addr < physical_mem_end)
  95                 return 1;
  96
  97 #ifdef CONFIG_BFIN_L2_DCACHEABLE
  98         if (addr >= L2_START && addr < L2_START + L2_LENGTH)
  99                 return 1;
 100 #endif
 101
 102         return 0;
 103 }
 104
 105 #endif                          /* _BLACKFIN_ICACHEFLUSH_H */