arch/microblaze/include/asm/cpuinfo.h

   1 /*
   2  * Generic support for queying CPU info
   3  *
   4  * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
   5  * Copyright (C) 2007-2009 PetaLogix
   6  * Copyright (C) 2007 John Williams <jwilliams@itee.uq.edu.au>
   7  *
   8  * This file is subject to the terms and conditions of the GNU General
   9  * Public License. See the file COPYING in the main directory of this
  10  * archive for more details.
  11  */
  12
  13 #ifndef _ASM_MICROBLAZE_CPUINFO_H
  14 #define _ASM_MICROBLAZE_CPUINFO_H
  15
  16 #include <asm/prom.h>
  17
  18 /* CPU Version and FPGA Family code conversion table type */
  19 struct cpu_ver_key {
  20         const char *s;
  21         const unsigned k;
  22 };
  23
  24 extern const struct cpu_ver_key cpu_ver_lookup[];
  25
  26 struct family_string_key {
  27         const char *s;
  28         const unsigned k;
  29 };
  30
  31 extern const struct family_string_key family_string_lookup[];
  32
  33 struct cpuinfo {
  34         /* Core CPU configuration */
  35         u32 use_instr;
  36         u32 use_mult;
  37         u32 use_fpu;
  38         u32 use_exc;
  39         u32 ver_code;
  40         u32 mmu;
  41         u32 endian;
  42
  43         /* CPU caches */
  44         u32 use_icache;
  45         u32 icache_tagbits;
  46         u32 icache_write;
  47         u32 icache_line_length;
  48         u32 icache_size;
  49         unsigned long icache_base;
  50         unsigned long icache_high;
  51
  52         u32 use_dcache;
  53         u32 dcache_tagbits;
  54         u32 dcache_write;
  55         u32 dcache_line_length;
  56         u32 dcache_size;
  57         u32 dcache_wb;
  58         unsigned long dcache_base;
  59         unsigned long dcache_high;
  60
  61         /* Bus connections */
  62         u32 use_dopb;
  63         u32 use_iopb;
  64         u32 use_dlmb;
  65         u32 use_ilmb;
  66         u32 num_fsl;
  67
  68         /* CPU interrupt line info */
  69         u32 irq_edge;
  70         u32 irq_positive;
  71
  72         u32 area_optimised;
  73
  74         /* HW debug support */
  75         u32 hw_debug;
  76         u32 num_pc_brk;
  77         u32 num_rd_brk;
  78         u32 num_wr_brk;
  79         u32 cpu_clock_freq; /* store real freq of cpu */
  80
  81         /* FPGA family */
  82         u32 fpga_family_code;
  83
  84         /* User define */
  85         u32 pvr_user1;
  86         u32 pvr_user2;
  87 };
  88
  89 extern struct cpuinfo cpuinfo;
  90
  91 /* fwd declarations of the various CPUinfo populators */
  92 void setup_cpuinfo(void);
  93
  94 void set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu);
  95 void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu);
  96
  97 static inline unsigned int fcpu(struct device_node *cpu, char *n)
  98 {
  99         const __be32 *val;
 100         return (val = of_get_property(cpu, n, NULL)) ?
 101                                                         be32_to_cpup(val) : 0;
 102 }
 103
 104 #endif /* _ASM_MICROBLAZE_CPUINFO_H */