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[pohmelfs.git] / arch / arm / mach-omap2 / gpmc-onenand.c
blob5cdce10d61835d50f9ebca84d108f6b31509cb5b
1 /*
2 * linux/arch/arm/mach-omap2/gpmc-onenand.c
3 *
4 * Copyright (C) 2006 - 2009 Nokia Corporation
5 * Contacts: Juha Yrjola
6 * Tony Lindgren
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/string.h>
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/mtd/onenand_regs.h>
17 #include <linux/io.h>
18
19 #include <asm/mach/flash.h>
20
21 #include <plat/onenand.h>
22 #include <plat/board.h>
23 #include <plat/gpmc.h>
24
25 static struct omap_onenand_platform_data *gpmc_onenand_data;
26
27 static struct platform_device gpmc_onenand_device = {
28 .name = "omap2-onenand",
29 .id = -1,
30 };
31
32 static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
33 {
34 struct gpmc_timings t;
35 u32 reg;
36 int err;
37
38 const int t_cer = 15;
39 const int t_avdp = 12;
40 const int t_aavdh = 7;
41 const int t_ce = 76;
42 const int t_aa = 76;
43 const int t_oe = 20;
44 const int t_cez = 20; /* max of t_cez, t_oez */
45 const int t_ds = 30;
46 const int t_wpl = 40;
47 const int t_wph = 30;
48
49 /* Ensure sync read and sync write are disabled */
50 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
51 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
52 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
53
54 memset(&t, 0, sizeof(t));
55 t.sync_clk = 0;
56 t.cs_on = 0;
57 t.adv_on = 0;
58
59 /* Read */
60 t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
61 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
62 t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
63 t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
64 t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
65 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
66 t.cs_rd_off = t.oe_off;
67 t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
68
69 /* Write */
70 t.adv_wr_off = t.adv_rd_off;
71 t.we_on = t.oe_on;
72 if (cpu_is_omap34xx()) {
73 t.wr_data_mux_bus = t.we_on;
74 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
75 }
76 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
77 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
78 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
79
80 /* Configure GPMC for asynchronous read */
81 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
82 GPMC_CONFIG1_DEVICESIZE_16 |
83 GPMC_CONFIG1_MUXADDDATA);
84
85 err = gpmc_cs_set_timings(cs, &t);
86 if (err)
87 return err;
88
89 /* Ensure sync read and sync write are disabled */
90 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
91 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
92 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
93
94 return 0;
95 }
96
97 static void set_onenand_cfg(void __iomem *onenand_base, int latency,
98 int sync_read, int sync_write, int hf, int vhf)
99 {
100 u32 reg;
101
102 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
103 reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
104 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
105 ONENAND_SYS_CFG1_BL_16;
106 if (sync_read)
107 reg |= ONENAND_SYS_CFG1_SYNC_READ;
108 else
109 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
110 if (sync_write)
111 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
112 else
113 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
114 if (hf)
115 reg |= ONENAND_SYS_CFG1_HF;
116 else
117 reg &= ~ONENAND_SYS_CFG1_HF;
118 if (vhf)
119 reg |= ONENAND_SYS_CFG1_VHF;
120 else
121 reg &= ~ONENAND_SYS_CFG1_VHF;
122 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
123 }
124
125 static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
126 void __iomem *onenand_base, bool *clk_dep)
127 {
128 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
129 int freq = 0;
130
131 if (cfg->get_freq) {
132 struct onenand_freq_info fi;
133
134 fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
135 fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
136 fi.ver_id = ver;
137 freq = cfg->get_freq(&fi, clk_dep);
138 if (freq)
139 return freq;
140 }
141
142 switch ((ver >> 4) & 0xf) {
143 case 0:
144 freq = 40;
145 break;
146 case 1:
147 freq = 54;
148 break;
149 case 2:
150 freq = 66;
151 break;
152 case 3:
153 freq = 83;
154 break;
155 case 4:
156 freq = 104;
157 break;
158 default:
159 freq = 54;
160 break;
161 }
162
163 return freq;
164 }
165
166 static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
167 void __iomem *onenand_base,
168 int *freq_ptr)
169 {
170 struct gpmc_timings t;
171 const int t_cer = 15;
172 const int t_avdp = 12;
173 const int t_cez = 20; /* max of t_cez, t_oez */
174 const int t_ds = 30;
175 const int t_wpl = 40;
176 const int t_wph = 30;
177 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
178 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
179 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
180 int err, ticks_cez;
181 int cs = cfg->cs, freq = *freq_ptr;
182 u32 reg;
183 bool clk_dep = false;
184
185 if (cfg->flags & ONENAND_SYNC_READ) {
186 sync_read = 1;
187 } else if (cfg->flags & ONENAND_SYNC_READWRITE) {
188 sync_read = 1;
189 sync_write = 1;
190 } else
191 return omap2_onenand_set_async_mode(cs, onenand_base);
192
193 if (!freq) {
194 /* Very first call freq is not known */
195 err = omap2_onenand_set_async_mode(cs, onenand_base);
196 if (err)
197 return err;
198 freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
199 first_time = 1;
200 }
201
202 switch (freq) {
203 case 104:
204 min_gpmc_clk_period = 9600; /* 104 MHz */
205 t_ces = 3;
206 t_avds = 4;
207 t_avdh = 2;
208 t_ach = 3;
209 t_aavdh = 6;
210 t_rdyo = 6;
211 break;
212 case 83:
213 min_gpmc_clk_period = 12000; /* 83 MHz */
214 t_ces = 5;
215 t_avds = 4;
216 t_avdh = 2;
217 t_ach = 6;
218 t_aavdh = 6;
219 t_rdyo = 9;
220 break;
221 case 66:
222 min_gpmc_clk_period = 15000; /* 66 MHz */
223 t_ces = 6;
224 t_avds = 5;
225 t_avdh = 2;
226 t_ach = 6;
227 t_aavdh = 6;
228 t_rdyo = 11;
229 break;
230 default:
231 min_gpmc_clk_period = 18500; /* 54 MHz */
232 t_ces = 7;
233 t_avds = 7;
234 t_avdh = 7;
235 t_ach = 9;
236 t_aavdh = 7;
237 t_rdyo = 15;
238 sync_write = 0;
239 break;
240 }
241
242 tick_ns = gpmc_ticks_to_ns(1);
243 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
244 gpmc_clk_ns = gpmc_ticks_to_ns(div);
245 if (gpmc_clk_ns < 15) /* >66Mhz */
246 hf = 1;
247 if (gpmc_clk_ns < 12) /* >83Mhz */
248 vhf = 1;
249 if (vhf)
250 latency = 8;
251 else if (hf)
252 latency = 6;
253 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
254 latency = 3;
255 else
256 latency = 4;
257
258 if (clk_dep) {
259 if (gpmc_clk_ns < 12) { /* >83Mhz */
260 t_ces = 3;
261 t_avds = 4;
262 } else if (gpmc_clk_ns < 15) { /* >66Mhz */
263 t_ces = 5;
264 t_avds = 4;
265 } else if (gpmc_clk_ns < 25) { /* >40Mhz */
266 t_ces = 6;
267 t_avds = 5;
268 } else {
269 t_ces = 7;
270 t_avds = 7;
271 }
272 }
273
274 if (first_time)
275 set_onenand_cfg(onenand_base, latency,
276 sync_read, sync_write, hf, vhf);
277
278 if (div == 1) {
279 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
280 reg |= (1 << 7);
281 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
282 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
283 reg |= (1 << 7);
284 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
285 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
286 reg |= (1 << 7);
287 reg |= (1 << 23);
288 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
289 } else {
290 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
291 reg &= ~(1 << 7);
292 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
293 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
294 reg &= ~(1 << 7);
295 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
296 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
297 reg &= ~(1 << 7);
298 reg &= ~(1 << 23);
299 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
300 }
301
302 /* Set synchronous read timings */
303 memset(&t, 0, sizeof(t));
304 t.sync_clk = min_gpmc_clk_period;
305 t.cs_on = 0;
306 t.adv_on = 0;
307 fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
308 fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
309 t.page_burst_access = gpmc_clk_ns;
310
311 /* Read */
312 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
313 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
314 /* Force at least 1 clk between AVD High to OE Low */
315 if (t.oe_on <= t.adv_rd_off)
316 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
317 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
318 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
319 t.cs_rd_off = t.oe_off;
320 ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;
321 t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
322 ticks_cez);
323
324 /* Write */
325 if (sync_write) {
326 t.adv_wr_off = t.adv_rd_off;
327 t.we_on = 0;
328 t.we_off = t.cs_rd_off;
329 t.cs_wr_off = t.cs_rd_off;
330 t.wr_cycle = t.rd_cycle;
331 if (cpu_is_omap34xx()) {
332 t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
333 gpmc_ps_to_ticks(min_gpmc_clk_period +
334 t_rdyo * 1000));
335 t.wr_access = t.access;
336 }
337 } else {
338 t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int,
339 t_avdp, t_cer));
340 t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);
341 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
342 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
343 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
344 if (cpu_is_omap34xx()) {
345 t.wr_data_mux_bus = t.we_on;
346 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
347 }
348 }
349
350 /* Configure GPMC for synchronous read */
351 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
352 GPMC_CONFIG1_WRAPBURST_SUPP |
353 GPMC_CONFIG1_READMULTIPLE_SUPP |
354 (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
355 (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
356 (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
357 GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
358 GPMC_CONFIG1_PAGE_LEN(2) |
359 (cpu_is_omap34xx() ? 0 :
360 (GPMC_CONFIG1_WAIT_READ_MON |
361 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
362 GPMC_CONFIG1_DEVICESIZE_16 |
363 GPMC_CONFIG1_DEVICETYPE_NOR |
364 GPMC_CONFIG1_MUXADDDATA);
365
366 err = gpmc_cs_set_timings(cs, &t);
367 if (err)
368 return err;
369
370 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
371
372 *freq_ptr = freq;
373
374 return 0;
375 }
376
377 static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
378 {
379 struct device *dev = &gpmc_onenand_device.dev;
380
381 /* Set sync timings in GPMC */
382 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
383 freq_ptr) < 0) {
384 dev_err(dev, "Unable to set synchronous mode\n");
385 return -EINVAL;
386 }
387
388 return 0;
389 }
390
391 void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
392 {
393 gpmc_onenand_data = _onenand_data;
394 gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
395 gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
396
397 if (cpu_is_omap24xx() &&
398 (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
399 printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
400 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
401 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
402 }
403
404 if (platform_device_register(&gpmc_onenand_device) < 0) {
405 printk(KERN_ERR "Unable to register OneNAND device\n");
406 return;
407 }
408 }