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[pohmelfs.git] / arch / arm / mach-omap2 / omap_hwmod_2430_data.c
blobc4f56cb60d7d676ddda36e232c8b385a58fef6ba
1 /*
2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14 #include <plat/omap_hwmod.h>
15 #include <mach/irqs.h>
16 #include <plat/cpu.h>
17 #include <plat/dma.h>
18 #include <plat/serial.h>
19 #include <plat/i2c.h>
20 #include <plat/gpio.h>
21 #include <plat/mcbsp.h>
22 #include <plat/mcspi.h>
23 #include <plat/dmtimer.h>
24 #include <plat/mmc.h>
25 #include <plat/l3_2xxx.h>
26
27 #include "omap_hwmod_common_data.h"
28
29 #include "prm-regbits-24xx.h"
30 #include "cm-regbits-24xx.h"
31 #include "wd_timer.h"
32
33 /*
34 * OMAP2430 hardware module integration data
35 *
36 * ALl of the data in this section should be autogeneratable from the
37 * TI hardware database or other technical documentation. Data that
38 * is driver-specific or driver-kernel integration-specific belongs
39 * elsewhere.
40 */
41
42 static struct omap_hwmod omap2430_mpu_hwmod;
43 static struct omap_hwmod omap2430_iva_hwmod;
44 static struct omap_hwmod omap2430_l3_main_hwmod;
45 static struct omap_hwmod omap2430_l4_core_hwmod;
46 static struct omap_hwmod omap2430_dss_core_hwmod;
47 static struct omap_hwmod omap2430_dss_dispc_hwmod;
48 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
49 static struct omap_hwmod omap2430_dss_venc_hwmod;
50 static struct omap_hwmod omap2430_wd_timer2_hwmod;
51 static struct omap_hwmod omap2430_gpio1_hwmod;
52 static struct omap_hwmod omap2430_gpio2_hwmod;
53 static struct omap_hwmod omap2430_gpio3_hwmod;
54 static struct omap_hwmod omap2430_gpio4_hwmod;
55 static struct omap_hwmod omap2430_gpio5_hwmod;
56 static struct omap_hwmod omap2430_dma_system_hwmod;
57 static struct omap_hwmod omap2430_mcbsp1_hwmod;
58 static struct omap_hwmod omap2430_mcbsp2_hwmod;
59 static struct omap_hwmod omap2430_mcbsp3_hwmod;
60 static struct omap_hwmod omap2430_mcbsp4_hwmod;
61 static struct omap_hwmod omap2430_mcbsp5_hwmod;
62 static struct omap_hwmod omap2430_mcspi1_hwmod;
63 static struct omap_hwmod omap2430_mcspi2_hwmod;
64 static struct omap_hwmod omap2430_mcspi3_hwmod;
65 static struct omap_hwmod omap2430_mmc1_hwmod;
66 static struct omap_hwmod omap2430_mmc2_hwmod;
67
68 /* L3 -> L4_CORE interface */
69 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
70 .master = &omap2430_l3_main_hwmod,
71 .slave = &omap2430_l4_core_hwmod,
72 .user = OCP_USER_MPU | OCP_USER_SDMA,
73 };
74
75 /* MPU -> L3 interface */
76 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
77 .master = &omap2430_mpu_hwmod,
78 .slave = &omap2430_l3_main_hwmod,
79 .user = OCP_USER_MPU,
80 };
81
82 /* Slave interfaces on the L3 interconnect */
83 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
84 &omap2430_mpu__l3_main,
85 };
86
87 /* DSS -> l3 */
88 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
89 .master = &omap2430_dss_core_hwmod,
90 .slave = &omap2430_l3_main_hwmod,
91 .fw = {
92 .omap2 = {
93 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
94 .flags = OMAP_FIREWALL_L3,
95 }
96 },
97 .user = OCP_USER_MPU | OCP_USER_SDMA,
98 };
99
100 /* Master interfaces on the L3 interconnect */
101 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
102 &omap2430_l3_main__l4_core,
103 };
104
105 /* L3 */
106 static struct omap_hwmod omap2430_l3_main_hwmod = {
107 .name = "l3_main",
108 .class = &l3_hwmod_class,
109 .masters = omap2430_l3_main_masters,
110 .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters),
111 .slaves = omap2430_l3_main_slaves,
112 .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves),
113 .flags = HWMOD_NO_IDLEST,
114 };
115
116 static struct omap_hwmod omap2430_l4_wkup_hwmod;
117 static struct omap_hwmod omap2430_uart1_hwmod;
118 static struct omap_hwmod omap2430_uart2_hwmod;
119 static struct omap_hwmod omap2430_uart3_hwmod;
120 static struct omap_hwmod omap2430_i2c1_hwmod;
121 static struct omap_hwmod omap2430_i2c2_hwmod;
122
123 static struct omap_hwmod omap2430_usbhsotg_hwmod;
124
125 /* l3_core -> usbhsotg interface */
126 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
127 .master = &omap2430_usbhsotg_hwmod,
128 .slave = &omap2430_l3_main_hwmod,
129 .clk = "core_l3_ck",
130 .user = OCP_USER_MPU,
131 };
132
133 /* L4 CORE -> I2C1 interface */
134 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
135 .master = &omap2430_l4_core_hwmod,
136 .slave = &omap2430_i2c1_hwmod,
137 .clk = "i2c1_ick",
138 .addr = omap2_i2c1_addr_space,
139 .user = OCP_USER_MPU | OCP_USER_SDMA,
140 };
141
142 /* L4 CORE -> I2C2 interface */
143 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
144 .master = &omap2430_l4_core_hwmod,
145 .slave = &omap2430_i2c2_hwmod,
146 .clk = "i2c2_ick",
147 .addr = omap2_i2c2_addr_space,
148 .user = OCP_USER_MPU | OCP_USER_SDMA,
149 };
150
151 /* L4_CORE -> L4_WKUP interface */
152 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
153 .master = &omap2430_l4_core_hwmod,
154 .slave = &omap2430_l4_wkup_hwmod,
155 .user = OCP_USER_MPU | OCP_USER_SDMA,
156 };
157
158 /* L4 CORE -> UART1 interface */
159 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
160 .master = &omap2430_l4_core_hwmod,
161 .slave = &omap2430_uart1_hwmod,
162 .clk = "uart1_ick",
163 .addr = omap2xxx_uart1_addr_space,
164 .user = OCP_USER_MPU | OCP_USER_SDMA,
165 };
166
167 /* L4 CORE -> UART2 interface */
168 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
169 .master = &omap2430_l4_core_hwmod,
170 .slave = &omap2430_uart2_hwmod,
171 .clk = "uart2_ick",
172 .addr = omap2xxx_uart2_addr_space,
173 .user = OCP_USER_MPU | OCP_USER_SDMA,
174 };
175
176 /* L4 PER -> UART3 interface */
177 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
178 .master = &omap2430_l4_core_hwmod,
179 .slave = &omap2430_uart3_hwmod,
180 .clk = "uart3_ick",
181 .addr = omap2xxx_uart3_addr_space,
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
183 };
184
185 /*
186 * usbhsotg interface data
187 */
188 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
189 {
190 .pa_start = OMAP243X_HS_BASE,
191 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
192 .flags = ADDR_TYPE_RT
193 },
194 { }
195 };
196
197 /* l4_core ->usbhsotg interface */
198 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
199 .master = &omap2430_l4_core_hwmod,
200 .slave = &omap2430_usbhsotg_hwmod,
201 .clk = "usb_l4_ick",
202 .addr = omap2430_usbhsotg_addrs,
203 .user = OCP_USER_MPU,
204 };
205
206 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
207 &omap2430_usbhsotg__l3,
208 };
209
210 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
211 &omap2430_l4_core__usbhsotg,
212 };
213
214 /* L4 CORE -> MMC1 interface */
215 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
216 .master = &omap2430_l4_core_hwmod,
217 .slave = &omap2430_mmc1_hwmod,
218 .clk = "mmchs1_ick",
219 .addr = omap2430_mmc1_addr_space,
220 .user = OCP_USER_MPU | OCP_USER_SDMA,
221 };
222
223 /* L4 CORE -> MMC2 interface */
224 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
225 .master = &omap2430_l4_core_hwmod,
226 .slave = &omap2430_mmc2_hwmod,
227 .clk = "mmchs2_ick",
228 .addr = omap2430_mmc2_addr_space,
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
230 };
231
232 /* Slave interfaces on the L4_CORE interconnect */
233 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
234 &omap2430_l3_main__l4_core,
235 };
236
237 /* Master interfaces on the L4_CORE interconnect */
238 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
239 &omap2430_l4_core__l4_wkup,
240 &omap2430_l4_core__mmc1,
241 &omap2430_l4_core__mmc2,
242 };
243
244 /* L4 CORE */
245 static struct omap_hwmod omap2430_l4_core_hwmod = {
246 .name = "l4_core",
247 .class = &l4_hwmod_class,
248 .masters = omap2430_l4_core_masters,
249 .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
250 .slaves = omap2430_l4_core_slaves,
251 .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
252 .flags = HWMOD_NO_IDLEST,
253 };
254
255 /* Slave interfaces on the L4_WKUP interconnect */
256 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
257 &omap2430_l4_core__l4_wkup,
258 &omap2_l4_core__uart1,
259 &omap2_l4_core__uart2,
260 &omap2_l4_core__uart3,
261 };
262
263 /* Master interfaces on the L4_WKUP interconnect */
264 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
265 };
266
267 /* l4 core -> mcspi1 interface */
268 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
269 .master = &omap2430_l4_core_hwmod,
270 .slave = &omap2430_mcspi1_hwmod,
271 .clk = "mcspi1_ick",
272 .addr = omap2_mcspi1_addr_space,
273 .user = OCP_USER_MPU | OCP_USER_SDMA,
274 };
275
276 /* l4 core -> mcspi2 interface */
277 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
278 .master = &omap2430_l4_core_hwmod,
279 .slave = &omap2430_mcspi2_hwmod,
280 .clk = "mcspi2_ick",
281 .addr = omap2_mcspi2_addr_space,
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
283 };
284
285 /* l4 core -> mcspi3 interface */
286 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
287 .master = &omap2430_l4_core_hwmod,
288 .slave = &omap2430_mcspi3_hwmod,
289 .clk = "mcspi3_ick",
290 .addr = omap2430_mcspi3_addr_space,
291 .user = OCP_USER_MPU | OCP_USER_SDMA,
292 };
293
294 /* L4 WKUP */
295 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
296 .name = "l4_wkup",
297 .class = &l4_hwmod_class,
298 .masters = omap2430_l4_wkup_masters,
299 .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
300 .slaves = omap2430_l4_wkup_slaves,
301 .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
302 .flags = HWMOD_NO_IDLEST,
303 };
304
305 /* Master interfaces on the MPU device */
306 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
307 &omap2430_mpu__l3_main,
308 };
309
310 /* MPU */
311 static struct omap_hwmod omap2430_mpu_hwmod = {
312 .name = "mpu",
313 .class = &mpu_hwmod_class,
314 .main_clk = "mpu_ck",
315 .masters = omap2430_mpu_masters,
316 .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
317 };
318
319 /*
320 * IVA2_1 interface data
321 */
322
323 /* IVA2 <- L3 interface */
324 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
325 .master = &omap2430_l3_main_hwmod,
326 .slave = &omap2430_iva_hwmod,
327 .clk = "dsp_fck",
328 .user = OCP_USER_MPU | OCP_USER_SDMA,
329 };
330
331 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
332 &omap2430_l3__iva,
333 };
334
335 /*
336 * IVA2 (IVA2)
337 */
338
339 static struct omap_hwmod omap2430_iva_hwmod = {
340 .name = "iva",
341 .class = &iva_hwmod_class,
342 .masters = omap2430_iva_masters,
343 .masters_cnt = ARRAY_SIZE(omap2430_iva_masters),
344 };
345
346 /* always-on timers dev attribute */
347 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
348 .timer_capability = OMAP_TIMER_ALWON,
349 };
350
351 /* pwm timers dev attribute */
352 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
353 .timer_capability = OMAP_TIMER_HAS_PWM,
354 };
355
356 /* timer1 */
357 static struct omap_hwmod omap2430_timer1_hwmod;
358
359 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
360 {
361 .pa_start = 0x49018000,
362 .pa_end = 0x49018000 + SZ_1K - 1,
363 .flags = ADDR_TYPE_RT
364 },
365 { }
366 };
367
368 /* l4_wkup -> timer1 */
369 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
370 .master = &omap2430_l4_wkup_hwmod,
371 .slave = &omap2430_timer1_hwmod,
372 .clk = "gpt1_ick",
373 .addr = omap2430_timer1_addrs,
374 .user = OCP_USER_MPU | OCP_USER_SDMA,
375 };
376
377 /* timer1 slave port */
378 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
379 &omap2430_l4_wkup__timer1,
380 };
381
382 /* timer1 hwmod */
383 static struct omap_hwmod omap2430_timer1_hwmod = {
384 .name = "timer1",
385 .mpu_irqs = omap2_timer1_mpu_irqs,
386 .main_clk = "gpt1_fck",
387 .prcm = {
388 .omap2 = {
389 .prcm_reg_id = 1,
390 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
391 .module_offs = WKUP_MOD,
392 .idlest_reg_id = 1,
393 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
394 },
395 },
396 .dev_attr = &capability_alwon_dev_attr,
397 .slaves = omap2430_timer1_slaves,
398 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
399 .class = &omap2xxx_timer_hwmod_class,
400 };
401
402 /* timer2 */
403 static struct omap_hwmod omap2430_timer2_hwmod;
404
405 /* l4_core -> timer2 */
406 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
407 .master = &omap2430_l4_core_hwmod,
408 .slave = &omap2430_timer2_hwmod,
409 .clk = "gpt2_ick",
410 .addr = omap2xxx_timer2_addrs,
411 .user = OCP_USER_MPU | OCP_USER_SDMA,
412 };
413
414 /* timer2 slave port */
415 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
416 &omap2430_l4_core__timer2,
417 };
418
419 /* timer2 hwmod */
420 static struct omap_hwmod omap2430_timer2_hwmod = {
421 .name = "timer2",
422 .mpu_irqs = omap2_timer2_mpu_irqs,
423 .main_clk = "gpt2_fck",
424 .prcm = {
425 .omap2 = {
426 .prcm_reg_id = 1,
427 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
428 .module_offs = CORE_MOD,
429 .idlest_reg_id = 1,
430 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
431 },
432 },
433 .dev_attr = &capability_alwon_dev_attr,
434 .slaves = omap2430_timer2_slaves,
435 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
436 .class = &omap2xxx_timer_hwmod_class,
437 };
438
439 /* timer3 */
440 static struct omap_hwmod omap2430_timer3_hwmod;
441
442 /* l4_core -> timer3 */
443 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
444 .master = &omap2430_l4_core_hwmod,
445 .slave = &omap2430_timer3_hwmod,
446 .clk = "gpt3_ick",
447 .addr = omap2xxx_timer3_addrs,
448 .user = OCP_USER_MPU | OCP_USER_SDMA,
449 };
450
451 /* timer3 slave port */
452 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
453 &omap2430_l4_core__timer3,
454 };
455
456 /* timer3 hwmod */
457 static struct omap_hwmod omap2430_timer3_hwmod = {
458 .name = "timer3",
459 .mpu_irqs = omap2_timer3_mpu_irqs,
460 .main_clk = "gpt3_fck",
461 .prcm = {
462 .omap2 = {
463 .prcm_reg_id = 1,
464 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
465 .module_offs = CORE_MOD,
466 .idlest_reg_id = 1,
467 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
468 },
469 },
470 .dev_attr = &capability_alwon_dev_attr,
471 .slaves = omap2430_timer3_slaves,
472 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
473 .class = &omap2xxx_timer_hwmod_class,
474 };
475
476 /* timer4 */
477 static struct omap_hwmod omap2430_timer4_hwmod;
478
479 /* l4_core -> timer4 */
480 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
481 .master = &omap2430_l4_core_hwmod,
482 .slave = &omap2430_timer4_hwmod,
483 .clk = "gpt4_ick",
484 .addr = omap2xxx_timer4_addrs,
485 .user = OCP_USER_MPU | OCP_USER_SDMA,
486 };
487
488 /* timer4 slave port */
489 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
490 &omap2430_l4_core__timer4,
491 };
492
493 /* timer4 hwmod */
494 static struct omap_hwmod omap2430_timer4_hwmod = {
495 .name = "timer4",
496 .mpu_irqs = omap2_timer4_mpu_irqs,
497 .main_clk = "gpt4_fck",
498 .prcm = {
499 .omap2 = {
500 .prcm_reg_id = 1,
501 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
502 .module_offs = CORE_MOD,
503 .idlest_reg_id = 1,
504 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
505 },
506 },
507 .dev_attr = &capability_alwon_dev_attr,
508 .slaves = omap2430_timer4_slaves,
509 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
510 .class = &omap2xxx_timer_hwmod_class,
511 };
512
513 /* timer5 */
514 static struct omap_hwmod omap2430_timer5_hwmod;
515
516 /* l4_core -> timer5 */
517 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
518 .master = &omap2430_l4_core_hwmod,
519 .slave = &omap2430_timer5_hwmod,
520 .clk = "gpt5_ick",
521 .addr = omap2xxx_timer5_addrs,
522 .user = OCP_USER_MPU | OCP_USER_SDMA,
523 };
524
525 /* timer5 slave port */
526 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
527 &omap2430_l4_core__timer5,
528 };
529
530 /* timer5 hwmod */
531 static struct omap_hwmod omap2430_timer5_hwmod = {
532 .name = "timer5",
533 .mpu_irqs = omap2_timer5_mpu_irqs,
534 .main_clk = "gpt5_fck",
535 .prcm = {
536 .omap2 = {
537 .prcm_reg_id = 1,
538 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
539 .module_offs = CORE_MOD,
540 .idlest_reg_id = 1,
541 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
542 },
543 },
544 .dev_attr = &capability_alwon_dev_attr,
545 .slaves = omap2430_timer5_slaves,
546 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
547 .class = &omap2xxx_timer_hwmod_class,
548 };
549
550 /* timer6 */
551 static struct omap_hwmod omap2430_timer6_hwmod;
552
553 /* l4_core -> timer6 */
554 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
555 .master = &omap2430_l4_core_hwmod,
556 .slave = &omap2430_timer6_hwmod,
557 .clk = "gpt6_ick",
558 .addr = omap2xxx_timer6_addrs,
559 .user = OCP_USER_MPU | OCP_USER_SDMA,
560 };
561
562 /* timer6 slave port */
563 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
564 &omap2430_l4_core__timer6,
565 };
566
567 /* timer6 hwmod */
568 static struct omap_hwmod omap2430_timer6_hwmod = {
569 .name = "timer6",
570 .mpu_irqs = omap2_timer6_mpu_irqs,
571 .main_clk = "gpt6_fck",
572 .prcm = {
573 .omap2 = {
574 .prcm_reg_id = 1,
575 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
576 .module_offs = CORE_MOD,
577 .idlest_reg_id = 1,
578 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
579 },
580 },
581 .dev_attr = &capability_alwon_dev_attr,
582 .slaves = omap2430_timer6_slaves,
583 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
584 .class = &omap2xxx_timer_hwmod_class,
585 };
586
587 /* timer7 */
588 static struct omap_hwmod omap2430_timer7_hwmod;
589
590 /* l4_core -> timer7 */
591 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
592 .master = &omap2430_l4_core_hwmod,
593 .slave = &omap2430_timer7_hwmod,
594 .clk = "gpt7_ick",
595 .addr = omap2xxx_timer7_addrs,
596 .user = OCP_USER_MPU | OCP_USER_SDMA,
597 };
598
599 /* timer7 slave port */
600 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
601 &omap2430_l4_core__timer7,
602 };
603
604 /* timer7 hwmod */
605 static struct omap_hwmod omap2430_timer7_hwmod = {
606 .name = "timer7",
607 .mpu_irqs = omap2_timer7_mpu_irqs,
608 .main_clk = "gpt7_fck",
609 .prcm = {
610 .omap2 = {
611 .prcm_reg_id = 1,
612 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
613 .module_offs = CORE_MOD,
614 .idlest_reg_id = 1,
615 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
616 },
617 },
618 .dev_attr = &capability_alwon_dev_attr,
619 .slaves = omap2430_timer7_slaves,
620 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
621 .class = &omap2xxx_timer_hwmod_class,
622 };
623
624 /* timer8 */
625 static struct omap_hwmod omap2430_timer8_hwmod;
626
627 /* l4_core -> timer8 */
628 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
629 .master = &omap2430_l4_core_hwmod,
630 .slave = &omap2430_timer8_hwmod,
631 .clk = "gpt8_ick",
632 .addr = omap2xxx_timer8_addrs,
633 .user = OCP_USER_MPU | OCP_USER_SDMA,
634 };
635
636 /* timer8 slave port */
637 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
638 &omap2430_l4_core__timer8,
639 };
640
641 /* timer8 hwmod */
642 static struct omap_hwmod omap2430_timer8_hwmod = {
643 .name = "timer8",
644 .mpu_irqs = omap2_timer8_mpu_irqs,
645 .main_clk = "gpt8_fck",
646 .prcm = {
647 .omap2 = {
648 .prcm_reg_id = 1,
649 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
650 .module_offs = CORE_MOD,
651 .idlest_reg_id = 1,
652 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
653 },
654 },
655 .dev_attr = &capability_alwon_dev_attr,
656 .slaves = omap2430_timer8_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
658 .class = &omap2xxx_timer_hwmod_class,
659 };
660
661 /* timer9 */
662 static struct omap_hwmod omap2430_timer9_hwmod;
663
664 /* l4_core -> timer9 */
665 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
666 .master = &omap2430_l4_core_hwmod,
667 .slave = &omap2430_timer9_hwmod,
668 .clk = "gpt9_ick",
669 .addr = omap2xxx_timer9_addrs,
670 .user = OCP_USER_MPU | OCP_USER_SDMA,
671 };
672
673 /* timer9 slave port */
674 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
675 &omap2430_l4_core__timer9,
676 };
677
678 /* timer9 hwmod */
679 static struct omap_hwmod omap2430_timer9_hwmod = {
680 .name = "timer9",
681 .mpu_irqs = omap2_timer9_mpu_irqs,
682 .main_clk = "gpt9_fck",
683 .prcm = {
684 .omap2 = {
685 .prcm_reg_id = 1,
686 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
687 .module_offs = CORE_MOD,
688 .idlest_reg_id = 1,
689 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
690 },
691 },
692 .dev_attr = &capability_pwm_dev_attr,
693 .slaves = omap2430_timer9_slaves,
694 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
695 .class = &omap2xxx_timer_hwmod_class,
696 };
697
698 /* timer10 */
699 static struct omap_hwmod omap2430_timer10_hwmod;
700
701 /* l4_core -> timer10 */
702 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
703 .master = &omap2430_l4_core_hwmod,
704 .slave = &omap2430_timer10_hwmod,
705 .clk = "gpt10_ick",
706 .addr = omap2_timer10_addrs,
707 .user = OCP_USER_MPU | OCP_USER_SDMA,
708 };
709
710 /* timer10 slave port */
711 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
712 &omap2430_l4_core__timer10,
713 };
714
715 /* timer10 hwmod */
716 static struct omap_hwmod omap2430_timer10_hwmod = {
717 .name = "timer10",
718 .mpu_irqs = omap2_timer10_mpu_irqs,
719 .main_clk = "gpt10_fck",
720 .prcm = {
721 .omap2 = {
722 .prcm_reg_id = 1,
723 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
724 .module_offs = CORE_MOD,
725 .idlest_reg_id = 1,
726 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
727 },
728 },
729 .dev_attr = &capability_pwm_dev_attr,
730 .slaves = omap2430_timer10_slaves,
731 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
732 .class = &omap2xxx_timer_hwmod_class,
733 };
734
735 /* timer11 */
736 static struct omap_hwmod omap2430_timer11_hwmod;
737
738 /* l4_core -> timer11 */
739 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
740 .master = &omap2430_l4_core_hwmod,
741 .slave = &omap2430_timer11_hwmod,
742 .clk = "gpt11_ick",
743 .addr = omap2_timer11_addrs,
744 .user = OCP_USER_MPU | OCP_USER_SDMA,
745 };
746
747 /* timer11 slave port */
748 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
749 &omap2430_l4_core__timer11,
750 };
751
752 /* timer11 hwmod */
753 static struct omap_hwmod omap2430_timer11_hwmod = {
754 .name = "timer11",
755 .mpu_irqs = omap2_timer11_mpu_irqs,
756 .main_clk = "gpt11_fck",
757 .prcm = {
758 .omap2 = {
759 .prcm_reg_id = 1,
760 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
761 .module_offs = CORE_MOD,
762 .idlest_reg_id = 1,
763 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
764 },
765 },
766 .dev_attr = &capability_pwm_dev_attr,
767 .slaves = omap2430_timer11_slaves,
768 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
769 .class = &omap2xxx_timer_hwmod_class,
770 };
771
772 /* timer12 */
773 static struct omap_hwmod omap2430_timer12_hwmod;
774
775 /* l4_core -> timer12 */
776 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
777 .master = &omap2430_l4_core_hwmod,
778 .slave = &omap2430_timer12_hwmod,
779 .clk = "gpt12_ick",
780 .addr = omap2xxx_timer12_addrs,
781 .user = OCP_USER_MPU | OCP_USER_SDMA,
782 };
783
784 /* timer12 slave port */
785 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
786 &omap2430_l4_core__timer12,
787 };
788
789 /* timer12 hwmod */
790 static struct omap_hwmod omap2430_timer12_hwmod = {
791 .name = "timer12",
792 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
793 .main_clk = "gpt12_fck",
794 .prcm = {
795 .omap2 = {
796 .prcm_reg_id = 1,
797 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
798 .module_offs = CORE_MOD,
799 .idlest_reg_id = 1,
800 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
801 },
802 },
803 .dev_attr = &capability_pwm_dev_attr,
804 .slaves = omap2430_timer12_slaves,
805 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
806 .class = &omap2xxx_timer_hwmod_class,
807 };
808
809 /* l4_wkup -> wd_timer2 */
810 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
811 {
812 .pa_start = 0x49016000,
813 .pa_end = 0x4901607f,
814 .flags = ADDR_TYPE_RT
815 },
816 { }
817 };
818
819 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
820 .master = &omap2430_l4_wkup_hwmod,
821 .slave = &omap2430_wd_timer2_hwmod,
822 .clk = "mpu_wdt_ick",
823 .addr = omap2430_wd_timer2_addrs,
824 .user = OCP_USER_MPU | OCP_USER_SDMA,
825 };
826
827 /* wd_timer2 */
828 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
829 &omap2430_l4_wkup__wd_timer2,
830 };
831
832 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
833 .name = "wd_timer2",
834 .class = &omap2xxx_wd_timer_hwmod_class,
835 .main_clk = "mpu_wdt_fck",
836 .prcm = {
837 .omap2 = {
838 .prcm_reg_id = 1,
839 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
840 .module_offs = WKUP_MOD,
841 .idlest_reg_id = 1,
842 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
843 },
844 },
845 .slaves = omap2430_wd_timer2_slaves,
846 .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
847 };
848
849 /* UART1 */
850
851 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
852 &omap2_l4_core__uart1,
853 };
854
855 static struct omap_hwmod omap2430_uart1_hwmod = {
856 .name = "uart1",
857 .mpu_irqs = omap2_uart1_mpu_irqs,
858 .sdma_reqs = omap2_uart1_sdma_reqs,
859 .main_clk = "uart1_fck",
860 .prcm = {
861 .omap2 = {
862 .module_offs = CORE_MOD,
863 .prcm_reg_id = 1,
864 .module_bit = OMAP24XX_EN_UART1_SHIFT,
865 .idlest_reg_id = 1,
866 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
867 },
868 },
869 .slaves = omap2430_uart1_slaves,
870 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
871 .class = &omap2_uart_class,
872 };
873
874 /* UART2 */
875
876 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
877 &omap2_l4_core__uart2,
878 };
879
880 static struct omap_hwmod omap2430_uart2_hwmod = {
881 .name = "uart2",
882 .mpu_irqs = omap2_uart2_mpu_irqs,
883 .sdma_reqs = omap2_uart2_sdma_reqs,
884 .main_clk = "uart2_fck",
885 .prcm = {
886 .omap2 = {
887 .module_offs = CORE_MOD,
888 .prcm_reg_id = 1,
889 .module_bit = OMAP24XX_EN_UART2_SHIFT,
890 .idlest_reg_id = 1,
891 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
892 },
893 },
894 .slaves = omap2430_uart2_slaves,
895 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
896 .class = &omap2_uart_class,
897 };
898
899 /* UART3 */
900
901 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
902 &omap2_l4_core__uart3,
903 };
904
905 static struct omap_hwmod omap2430_uart3_hwmod = {
906 .name = "uart3",
907 .mpu_irqs = omap2_uart3_mpu_irqs,
908 .sdma_reqs = omap2_uart3_sdma_reqs,
909 .main_clk = "uart3_fck",
910 .prcm = {
911 .omap2 = {
912 .module_offs = CORE_MOD,
913 .prcm_reg_id = 2,
914 .module_bit = OMAP24XX_EN_UART3_SHIFT,
915 .idlest_reg_id = 2,
916 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
917 },
918 },
919 .slaves = omap2430_uart3_slaves,
920 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
921 .class = &omap2_uart_class,
922 };
923
924 /* dss */
925 /* dss master ports */
926 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
927 &omap2430_dss__l3,
928 };
929
930 /* l4_core -> dss */
931 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
932 .master = &omap2430_l4_core_hwmod,
933 .slave = &omap2430_dss_core_hwmod,
934 .clk = "dss_ick",
935 .addr = omap2_dss_addrs,
936 .user = OCP_USER_MPU | OCP_USER_SDMA,
937 };
938
939 /* dss slave ports */
940 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
941 &omap2430_l4_core__dss,
942 };
943
944 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
945 /*
946 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
947 * driver does not use these clocks.
948 */
949 { .role = "tv_clk", .clk = "dss_54m_fck" },
950 { .role = "sys_clk", .clk = "dss2_fck" },
951 };
952
953 static struct omap_hwmod omap2430_dss_core_hwmod = {
954 .name = "dss_core",
955 .class = &omap2_dss_hwmod_class,
956 .main_clk = "dss1_fck", /* instead of dss_fck */
957 .sdma_reqs = omap2xxx_dss_sdma_chs,
958 .prcm = {
959 .omap2 = {
960 .prcm_reg_id = 1,
961 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
962 .module_offs = CORE_MOD,
963 .idlest_reg_id = 1,
964 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
965 },
966 },
967 .opt_clks = dss_opt_clks,
968 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
969 .slaves = omap2430_dss_slaves,
970 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
971 .masters = omap2430_dss_masters,
972 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
973 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
974 };
975
976 /* l4_core -> dss_dispc */
977 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
978 .master = &omap2430_l4_core_hwmod,
979 .slave = &omap2430_dss_dispc_hwmod,
980 .clk = "dss_ick",
981 .addr = omap2_dss_dispc_addrs,
982 .user = OCP_USER_MPU | OCP_USER_SDMA,
983 };
984
985 /* dss_dispc slave ports */
986 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
987 &omap2430_l4_core__dss_dispc,
988 };
989
990 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
991 .name = "dss_dispc",
992 .class = &omap2_dispc_hwmod_class,
993 .mpu_irqs = omap2_dispc_irqs,
994 .main_clk = "dss1_fck",
995 .prcm = {
996 .omap2 = {
997 .prcm_reg_id = 1,
998 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
999 .module_offs = CORE_MOD,
1000 .idlest_reg_id = 1,
1001 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1002 },
1003 },
1004 .slaves = omap2430_dss_dispc_slaves,
1005 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1006 .flags = HWMOD_NO_IDLEST,
1007 .dev_attr = &omap2_3_dss_dispc_dev_attr
1008 };
1009
1010 /* l4_core -> dss_rfbi */
1011 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1012 .master = &omap2430_l4_core_hwmod,
1013 .slave = &omap2430_dss_rfbi_hwmod,
1014 .clk = "dss_ick",
1015 .addr = omap2_dss_rfbi_addrs,
1016 .user = OCP_USER_MPU | OCP_USER_SDMA,
1017 };
1018
1019 /* dss_rfbi slave ports */
1020 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1021 &omap2430_l4_core__dss_rfbi,
1022 };
1023
1024 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1025 { .role = "ick", .clk = "dss_ick" },
1026 };
1027
1028 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1029 .name = "dss_rfbi",
1030 .class = &omap2_rfbi_hwmod_class,
1031 .main_clk = "dss1_fck",
1032 .prcm = {
1033 .omap2 = {
1034 .prcm_reg_id = 1,
1035 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1036 .module_offs = CORE_MOD,
1037 },
1038 },
1039 .opt_clks = dss_rfbi_opt_clks,
1040 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1041 .slaves = omap2430_dss_rfbi_slaves,
1042 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1043 .flags = HWMOD_NO_IDLEST,
1044 };
1045
1046 /* l4_core -> dss_venc */
1047 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1048 .master = &omap2430_l4_core_hwmod,
1049 .slave = &omap2430_dss_venc_hwmod,
1050 .clk = "dss_ick",
1051 .addr = omap2_dss_venc_addrs,
1052 .flags = OCPIF_SWSUP_IDLE,
1053 .user = OCP_USER_MPU | OCP_USER_SDMA,
1054 };
1055
1056 /* dss_venc slave ports */
1057 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1058 &omap2430_l4_core__dss_venc,
1059 };
1060
1061 static struct omap_hwmod omap2430_dss_venc_hwmod = {
1062 .name = "dss_venc",
1063 .class = &omap2_venc_hwmod_class,
1064 .main_clk = "dss_54m_fck",
1065 .prcm = {
1066 .omap2 = {
1067 .prcm_reg_id = 1,
1068 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1069 .module_offs = CORE_MOD,
1070 },
1071 },
1072 .slaves = omap2430_dss_venc_slaves,
1073 .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves),
1074 .flags = HWMOD_NO_IDLEST,
1075 };
1076
1077 /* I2C common */
1078 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1079 .rev_offs = 0x00,
1080 .sysc_offs = 0x20,
1081 .syss_offs = 0x10,
1082 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1083 SYSS_HAS_RESET_STATUS),
1084 .sysc_fields = &omap_hwmod_sysc_type1,
1085 };
1086
1087 static struct omap_hwmod_class i2c_class = {
1088 .name = "i2c",
1089 .sysc = &i2c_sysc,
1090 .rev = OMAP_I2C_IP_VERSION_1,
1091 .reset = &omap_i2c_reset,
1092 };
1093
1094 static struct omap_i2c_dev_attr i2c_dev_attr = {
1095 .fifo_depth = 8, /* bytes */
1096 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1097 OMAP_I2C_FLAG_BUS_SHIFT_2 |
1098 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1099 };
1100
1101 /* I2C1 */
1102
1103 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1104 &omap2430_l4_core__i2c1,
1105 };
1106
1107 static struct omap_hwmod omap2430_i2c1_hwmod = {
1108 .name = "i2c1",
1109 .flags = HWMOD_16BIT_REG,
1110 .mpu_irqs = omap2_i2c1_mpu_irqs,
1111 .sdma_reqs = omap2_i2c1_sdma_reqs,
1112 .main_clk = "i2chs1_fck",
1113 .prcm = {
1114 .omap2 = {
1115 /*
1116 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1117 * I2CHS IP's do not follow the usual pattern.
1118 * prcm_reg_id alone cannot be used to program
1119 * the iclk and fclk. Needs to be handled using
1120 * additional flags when clk handling is moved
1121 * to hwmod framework.
1122 */
1123 .module_offs = CORE_MOD,
1124 .prcm_reg_id = 1,
1125 .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1126 .idlest_reg_id = 1,
1127 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1128 },
1129 },
1130 .slaves = omap2430_i2c1_slaves,
1131 .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
1132 .class = &i2c_class,
1133 .dev_attr = &i2c_dev_attr,
1134 };
1135
1136 /* I2C2 */
1137
1138 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1139 &omap2430_l4_core__i2c2,
1140 };
1141
1142 static struct omap_hwmod omap2430_i2c2_hwmod = {
1143 .name = "i2c2",
1144 .flags = HWMOD_16BIT_REG,
1145 .mpu_irqs = omap2_i2c2_mpu_irqs,
1146 .sdma_reqs = omap2_i2c2_sdma_reqs,
1147 .main_clk = "i2chs2_fck",
1148 .prcm = {
1149 .omap2 = {
1150 .module_offs = CORE_MOD,
1151 .prcm_reg_id = 1,
1152 .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1153 .idlest_reg_id = 1,
1154 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1155 },
1156 },
1157 .slaves = omap2430_i2c2_slaves,
1158 .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
1159 .class = &i2c_class,
1160 .dev_attr = &i2c_dev_attr,
1161 };
1162
1163 /* l4_wkup -> gpio1 */
1164 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1165 {
1166 .pa_start = 0x4900C000,
1167 .pa_end = 0x4900C1ff,
1168 .flags = ADDR_TYPE_RT
1169 },
1170 { }
1171 };
1172
1173 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1174 .master = &omap2430_l4_wkup_hwmod,
1175 .slave = &omap2430_gpio1_hwmod,
1176 .clk = "gpios_ick",
1177 .addr = omap2430_gpio1_addr_space,
1178 .user = OCP_USER_MPU | OCP_USER_SDMA,
1179 };
1180
1181 /* l4_wkup -> gpio2 */
1182 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1183 {
1184 .pa_start = 0x4900E000,
1185 .pa_end = 0x4900E1ff,
1186 .flags = ADDR_TYPE_RT
1187 },
1188 { }
1189 };
1190
1191 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1192 .master = &omap2430_l4_wkup_hwmod,
1193 .slave = &omap2430_gpio2_hwmod,
1194 .clk = "gpios_ick",
1195 .addr = omap2430_gpio2_addr_space,
1196 .user = OCP_USER_MPU | OCP_USER_SDMA,
1197 };
1198
1199 /* l4_wkup -> gpio3 */
1200 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1201 {
1202 .pa_start = 0x49010000,
1203 .pa_end = 0x490101ff,
1204 .flags = ADDR_TYPE_RT
1205 },
1206 { }
1207 };
1208
1209 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1210 .master = &omap2430_l4_wkup_hwmod,
1211 .slave = &omap2430_gpio3_hwmod,
1212 .clk = "gpios_ick",
1213 .addr = omap2430_gpio3_addr_space,
1214 .user = OCP_USER_MPU | OCP_USER_SDMA,
1215 };
1216
1217 /* l4_wkup -> gpio4 */
1218 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1219 {
1220 .pa_start = 0x49012000,
1221 .pa_end = 0x490121ff,
1222 .flags = ADDR_TYPE_RT
1223 },
1224 { }
1225 };
1226
1227 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1228 .master = &omap2430_l4_wkup_hwmod,
1229 .slave = &omap2430_gpio4_hwmod,
1230 .clk = "gpios_ick",
1231 .addr = omap2430_gpio4_addr_space,
1232 .user = OCP_USER_MPU | OCP_USER_SDMA,
1233 };
1234
1235 /* l4_core -> gpio5 */
1236 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1237 {
1238 .pa_start = 0x480B6000,
1239 .pa_end = 0x480B61ff,
1240 .flags = ADDR_TYPE_RT
1241 },
1242 { }
1243 };
1244
1245 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1246 .master = &omap2430_l4_core_hwmod,
1247 .slave = &omap2430_gpio5_hwmod,
1248 .clk = "gpio5_ick",
1249 .addr = omap2430_gpio5_addr_space,
1250 .user = OCP_USER_MPU | OCP_USER_SDMA,
1251 };
1252
1253 /* gpio dev_attr */
1254 static struct omap_gpio_dev_attr gpio_dev_attr = {
1255 .bank_width = 32,
1256 .dbck_flag = false,
1257 };
1258
1259 /* gpio1 */
1260 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1261 &omap2430_l4_wkup__gpio1,
1262 };
1263
1264 static struct omap_hwmod omap2430_gpio1_hwmod = {
1265 .name = "gpio1",
1266 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1267 .mpu_irqs = omap2_gpio1_irqs,
1268 .main_clk = "gpios_fck",
1269 .prcm = {
1270 .omap2 = {
1271 .prcm_reg_id = 1,
1272 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1273 .module_offs = WKUP_MOD,
1274 .idlest_reg_id = 1,
1275 .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1276 },
1277 },
1278 .slaves = omap2430_gpio1_slaves,
1279 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
1280 .class = &omap2xxx_gpio_hwmod_class,
1281 .dev_attr = &gpio_dev_attr,
1282 };
1283
1284 /* gpio2 */
1285 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1286 &omap2430_l4_wkup__gpio2,
1287 };
1288
1289 static struct omap_hwmod omap2430_gpio2_hwmod = {
1290 .name = "gpio2",
1291 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1292 .mpu_irqs = omap2_gpio2_irqs,
1293 .main_clk = "gpios_fck",
1294 .prcm = {
1295 .omap2 = {
1296 .prcm_reg_id = 1,
1297 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1298 .module_offs = WKUP_MOD,
1299 .idlest_reg_id = 1,
1300 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1301 },
1302 },
1303 .slaves = omap2430_gpio2_slaves,
1304 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
1305 .class = &omap2xxx_gpio_hwmod_class,
1306 .dev_attr = &gpio_dev_attr,
1307 };
1308
1309 /* gpio3 */
1310 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1311 &omap2430_l4_wkup__gpio3,
1312 };
1313
1314 static struct omap_hwmod omap2430_gpio3_hwmod = {
1315 .name = "gpio3",
1316 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1317 .mpu_irqs = omap2_gpio3_irqs,
1318 .main_clk = "gpios_fck",
1319 .prcm = {
1320 .omap2 = {
1321 .prcm_reg_id = 1,
1322 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1323 .module_offs = WKUP_MOD,
1324 .idlest_reg_id = 1,
1325 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1326 },
1327 },
1328 .slaves = omap2430_gpio3_slaves,
1329 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
1330 .class = &omap2xxx_gpio_hwmod_class,
1331 .dev_attr = &gpio_dev_attr,
1332 };
1333
1334 /* gpio4 */
1335 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1336 &omap2430_l4_wkup__gpio4,
1337 };
1338
1339 static struct omap_hwmod omap2430_gpio4_hwmod = {
1340 .name = "gpio4",
1341 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1342 .mpu_irqs = omap2_gpio4_irqs,
1343 .main_clk = "gpios_fck",
1344 .prcm = {
1345 .omap2 = {
1346 .prcm_reg_id = 1,
1347 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1348 .module_offs = WKUP_MOD,
1349 .idlest_reg_id = 1,
1350 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1351 },
1352 },
1353 .slaves = omap2430_gpio4_slaves,
1354 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
1355 .class = &omap2xxx_gpio_hwmod_class,
1356 .dev_attr = &gpio_dev_attr,
1357 };
1358
1359 /* gpio5 */
1360 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1361 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1362 { .irq = -1 }
1363 };
1364
1365 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1366 &omap2430_l4_core__gpio5,
1367 };
1368
1369 static struct omap_hwmod omap2430_gpio5_hwmod = {
1370 .name = "gpio5",
1371 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1372 .mpu_irqs = omap243x_gpio5_irqs,
1373 .main_clk = "gpio5_fck",
1374 .prcm = {
1375 .omap2 = {
1376 .prcm_reg_id = 2,
1377 .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1378 .module_offs = CORE_MOD,
1379 .idlest_reg_id = 2,
1380 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1381 },
1382 },
1383 .slaves = omap2430_gpio5_slaves,
1384 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
1385 .class = &omap2xxx_gpio_hwmod_class,
1386 .dev_attr = &gpio_dev_attr,
1387 };
1388
1389 /* dma attributes */
1390 static struct omap_dma_dev_attr dma_dev_attr = {
1391 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1392 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1393 .lch_count = 32,
1394 };
1395
1396 /* dma_system -> L3 */
1397 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1398 .master = &omap2430_dma_system_hwmod,
1399 .slave = &omap2430_l3_main_hwmod,
1400 .clk = "core_l3_ck",
1401 .user = OCP_USER_MPU | OCP_USER_SDMA,
1402 };
1403
1404 /* dma_system master ports */
1405 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1406 &omap2430_dma_system__l3,
1407 };
1408
1409 /* l4_core -> dma_system */
1410 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1411 .master = &omap2430_l4_core_hwmod,
1412 .slave = &omap2430_dma_system_hwmod,
1413 .clk = "sdma_ick",
1414 .addr = omap2_dma_system_addrs,
1415 .user = OCP_USER_MPU | OCP_USER_SDMA,
1416 };
1417
1418 /* dma_system slave ports */
1419 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1420 &omap2430_l4_core__dma_system,
1421 };
1422
1423 static struct omap_hwmod omap2430_dma_system_hwmod = {
1424 .name = "dma",
1425 .class = &omap2xxx_dma_hwmod_class,
1426 .mpu_irqs = omap2_dma_system_irqs,
1427 .main_clk = "core_l3_ck",
1428 .slaves = omap2430_dma_system_slaves,
1429 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
1430 .masters = omap2430_dma_system_masters,
1431 .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
1432 .dev_attr = &dma_dev_attr,
1433 .flags = HWMOD_NO_IDLEST,
1434 };
1435
1436 /* mailbox */
1437 static struct omap_hwmod omap2430_mailbox_hwmod;
1438 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1439 { .irq = 26 },
1440 { .irq = -1 }
1441 };
1442
1443 /* l4_core -> mailbox */
1444 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
1445 .master = &omap2430_l4_core_hwmod,
1446 .slave = &omap2430_mailbox_hwmod,
1447 .addr = omap2_mailbox_addrs,
1448 .user = OCP_USER_MPU | OCP_USER_SDMA,
1449 };
1450
1451 /* mailbox slave ports */
1452 static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
1453 &omap2430_l4_core__mailbox,
1454 };
1455
1456 static struct omap_hwmod omap2430_mailbox_hwmod = {
1457 .name = "mailbox",
1458 .class = &omap2xxx_mailbox_hwmod_class,
1459 .mpu_irqs = omap2430_mailbox_irqs,
1460 .main_clk = "mailboxes_ick",
1461 .prcm = {
1462 .omap2 = {
1463 .prcm_reg_id = 1,
1464 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1465 .module_offs = CORE_MOD,
1466 .idlest_reg_id = 1,
1467 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1468 },
1469 },
1470 .slaves = omap2430_mailbox_slaves,
1471 .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
1472 };
1473
1474 /* mcspi1 */
1475 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1476 &omap2430_l4_core__mcspi1,
1477 };
1478
1479 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1480 .num_chipselect = 4,
1481 };
1482
1483 static struct omap_hwmod omap2430_mcspi1_hwmod = {
1484 .name = "mcspi1_hwmod",
1485 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1486 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1487 .main_clk = "mcspi1_fck",
1488 .prcm = {
1489 .omap2 = {
1490 .module_offs = CORE_MOD,
1491 .prcm_reg_id = 1,
1492 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1493 .idlest_reg_id = 1,
1494 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1495 },
1496 },
1497 .slaves = omap2430_mcspi1_slaves,
1498 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
1499 .class = &omap2xxx_mcspi_class,
1500 .dev_attr = &omap_mcspi1_dev_attr,
1501 };
1502
1503 /* mcspi2 */
1504 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1505 &omap2430_l4_core__mcspi2,
1506 };
1507
1508 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1509 .num_chipselect = 2,
1510 };
1511
1512 static struct omap_hwmod omap2430_mcspi2_hwmod = {
1513 .name = "mcspi2_hwmod",
1514 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1515 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1516 .main_clk = "mcspi2_fck",
1517 .prcm = {
1518 .omap2 = {
1519 .module_offs = CORE_MOD,
1520 .prcm_reg_id = 1,
1521 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1522 .idlest_reg_id = 1,
1523 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1524 },
1525 },
1526 .slaves = omap2430_mcspi2_slaves,
1527 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
1528 .class = &omap2xxx_mcspi_class,
1529 .dev_attr = &omap_mcspi2_dev_attr,
1530 };
1531
1532 /* mcspi3 */
1533 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
1534 { .irq = 91 },
1535 { .irq = -1 }
1536 };
1537
1538 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
1539 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
1540 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
1541 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
1542 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
1543 { .dma_req = -1 }
1544 };
1545
1546 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
1547 &omap2430_l4_core__mcspi3,
1548 };
1549
1550 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1551 .num_chipselect = 2,
1552 };
1553
1554 static struct omap_hwmod omap2430_mcspi3_hwmod = {
1555 .name = "mcspi3_hwmod",
1556 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
1557 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
1558 .main_clk = "mcspi3_fck",
1559 .prcm = {
1560 .omap2 = {
1561 .module_offs = CORE_MOD,
1562 .prcm_reg_id = 2,
1563 .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
1564 .idlest_reg_id = 2,
1565 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
1566 },
1567 },
1568 .slaves = omap2430_mcspi3_slaves,
1569 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
1570 .class = &omap2xxx_mcspi_class,
1571 .dev_attr = &omap_mcspi3_dev_attr,
1572 };
1573
1574 /*
1575 * usbhsotg
1576 */
1577 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
1578 .rev_offs = 0x0400,
1579 .sysc_offs = 0x0404,
1580 .syss_offs = 0x0408,
1581 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1582 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1583 SYSC_HAS_AUTOIDLE),
1584 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1585 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1586 .sysc_fields = &omap_hwmod_sysc_type1,
1587 };
1588
1589 static struct omap_hwmod_class usbotg_class = {
1590 .name = "usbotg",
1591 .sysc = &omap2430_usbhsotg_sysc,
1592 };
1593
1594 /* usb_otg_hs */
1595 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
1596
1597 { .name = "mc", .irq = 92 },
1598 { .name = "dma", .irq = 93 },
1599 { .irq = -1 }
1600 };
1601
1602 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1603 .name = "usb_otg_hs",
1604 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
1605 .main_clk = "usbhs_ick",
1606 .prcm = {
1607 .omap2 = {
1608 .prcm_reg_id = 1,
1609 .module_bit = OMAP2430_EN_USBHS_MASK,
1610 .module_offs = CORE_MOD,
1611 .idlest_reg_id = 1,
1612 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1613 },
1614 },
1615 .masters = omap2430_usbhsotg_masters,
1616 .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
1617 .slaves = omap2430_usbhsotg_slaves,
1618 .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1619 .class = &usbotg_class,
1620 /*
1621 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1622 * broken when autoidle is enabled
1623 * workaround is to disable the autoidle bit at module level.
1624 */
1625 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1626 | HWMOD_SWSUP_MSTANDBY,
1627 };
1628
1629 /*
1630 * 'mcbsp' class
1631 * multi channel buffered serial port controller
1632 */
1633
1634 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
1635 .rev_offs = 0x007C,
1636 .sysc_offs = 0x008C,
1637 .sysc_flags = (SYSC_HAS_SOFTRESET),
1638 .sysc_fields = &omap_hwmod_sysc_type1,
1639 };
1640
1641 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
1642 .name = "mcbsp",
1643 .sysc = &omap2430_mcbsp_sysc,
1644 .rev = MCBSP_CONFIG_TYPE2,
1645 };
1646
1647 /* mcbsp1 */
1648 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
1649 { .name = "tx", .irq = 59 },
1650 { .name = "rx", .irq = 60 },
1651 { .name = "ovr", .irq = 61 },
1652 { .name = "common", .irq = 64 },
1653 { .irq = -1 }
1654 };
1655
1656 /* l4_core -> mcbsp1 */
1657 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
1658 .master = &omap2430_l4_core_hwmod,
1659 .slave = &omap2430_mcbsp1_hwmod,
1660 .clk = "mcbsp1_ick",
1661 .addr = omap2_mcbsp1_addrs,
1662 .user = OCP_USER_MPU | OCP_USER_SDMA,
1663 };
1664
1665 /* mcbsp1 slave ports */
1666 static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
1667 &omap2430_l4_core__mcbsp1,
1668 };
1669
1670 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
1671 .name = "mcbsp1",
1672 .class = &omap2430_mcbsp_hwmod_class,
1673 .mpu_irqs = omap2430_mcbsp1_irqs,
1674 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1675 .main_clk = "mcbsp1_fck",
1676 .prcm = {
1677 .omap2 = {
1678 .prcm_reg_id = 1,
1679 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1680 .module_offs = CORE_MOD,
1681 .idlest_reg_id = 1,
1682 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1683 },
1684 },
1685 .slaves = omap2430_mcbsp1_slaves,
1686 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
1687 };
1688
1689 /* mcbsp2 */
1690 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
1691 { .name = "tx", .irq = 62 },
1692 { .name = "rx", .irq = 63 },
1693 { .name = "common", .irq = 16 },
1694 { .irq = -1 }
1695 };
1696
1697 /* l4_core -> mcbsp2 */
1698 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
1699 .master = &omap2430_l4_core_hwmod,
1700 .slave = &omap2430_mcbsp2_hwmod,
1701 .clk = "mcbsp2_ick",
1702 .addr = omap2xxx_mcbsp2_addrs,
1703 .user = OCP_USER_MPU | OCP_USER_SDMA,
1704 };
1705
1706 /* mcbsp2 slave ports */
1707 static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
1708 &omap2430_l4_core__mcbsp2,
1709 };
1710
1711 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
1712 .name = "mcbsp2",
1713 .class = &omap2430_mcbsp_hwmod_class,
1714 .mpu_irqs = omap2430_mcbsp2_irqs,
1715 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1716 .main_clk = "mcbsp2_fck",
1717 .prcm = {
1718 .omap2 = {
1719 .prcm_reg_id = 1,
1720 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1721 .module_offs = CORE_MOD,
1722 .idlest_reg_id = 1,
1723 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1724 },
1725 },
1726 .slaves = omap2430_mcbsp2_slaves,
1727 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
1728 };
1729
1730 /* mcbsp3 */
1731 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
1732 { .name = "tx", .irq = 89 },
1733 { .name = "rx", .irq = 90 },
1734 { .name = "common", .irq = 17 },
1735 { .irq = -1 }
1736 };
1737
1738 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
1739 {
1740 .name = "mpu",
1741 .pa_start = 0x4808C000,
1742 .pa_end = 0x4808C0ff,
1743 .flags = ADDR_TYPE_RT
1744 },
1745 { }
1746 };
1747
1748 /* l4_core -> mcbsp3 */
1749 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
1750 .master = &omap2430_l4_core_hwmod,
1751 .slave = &omap2430_mcbsp3_hwmod,
1752 .clk = "mcbsp3_ick",
1753 .addr = omap2430_mcbsp3_addrs,
1754 .user = OCP_USER_MPU | OCP_USER_SDMA,
1755 };
1756
1757 /* mcbsp3 slave ports */
1758 static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
1759 &omap2430_l4_core__mcbsp3,
1760 };
1761
1762 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
1763 .name = "mcbsp3",
1764 .class = &omap2430_mcbsp_hwmod_class,
1765 .mpu_irqs = omap2430_mcbsp3_irqs,
1766 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1767 .main_clk = "mcbsp3_fck",
1768 .prcm = {
1769 .omap2 = {
1770 .prcm_reg_id = 1,
1771 .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
1772 .module_offs = CORE_MOD,
1773 .idlest_reg_id = 2,
1774 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
1775 },
1776 },
1777 .slaves = omap2430_mcbsp3_slaves,
1778 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
1779 };
1780
1781 /* mcbsp4 */
1782 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
1783 { .name = "tx", .irq = 54 },
1784 { .name = "rx", .irq = 55 },
1785 { .name = "common", .irq = 18 },
1786 { .irq = -1 }
1787 };
1788
1789 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
1790 { .name = "rx", .dma_req = 20 },
1791 { .name = "tx", .dma_req = 19 },
1792 { .dma_req = -1 }
1793 };
1794
1795 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
1796 {
1797 .name = "mpu",
1798 .pa_start = 0x4808E000,
1799 .pa_end = 0x4808E0ff,
1800 .flags = ADDR_TYPE_RT
1801 },
1802 { }
1803 };
1804
1805 /* l4_core -> mcbsp4 */
1806 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
1807 .master = &omap2430_l4_core_hwmod,
1808 .slave = &omap2430_mcbsp4_hwmod,
1809 .clk = "mcbsp4_ick",
1810 .addr = omap2430_mcbsp4_addrs,
1811 .user = OCP_USER_MPU | OCP_USER_SDMA,
1812 };
1813
1814 /* mcbsp4 slave ports */
1815 static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
1816 &omap2430_l4_core__mcbsp4,
1817 };
1818
1819 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
1820 .name = "mcbsp4",
1821 .class = &omap2430_mcbsp_hwmod_class,
1822 .mpu_irqs = omap2430_mcbsp4_irqs,
1823 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
1824 .main_clk = "mcbsp4_fck",
1825 .prcm = {
1826 .omap2 = {
1827 .prcm_reg_id = 1,
1828 .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
1829 .module_offs = CORE_MOD,
1830 .idlest_reg_id = 2,
1831 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
1832 },
1833 },
1834 .slaves = omap2430_mcbsp4_slaves,
1835 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
1836 };
1837
1838 /* mcbsp5 */
1839 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
1840 { .name = "tx", .irq = 81 },
1841 { .name = "rx", .irq = 82 },
1842 { .name = "common", .irq = 19 },
1843 { .irq = -1 }
1844 };
1845
1846 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
1847 { .name = "rx", .dma_req = 22 },
1848 { .name = "tx", .dma_req = 21 },
1849 { .dma_req = -1 }
1850 };
1851
1852 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
1853 {
1854 .name = "mpu",
1855 .pa_start = 0x48096000,
1856 .pa_end = 0x480960ff,
1857 .flags = ADDR_TYPE_RT
1858 },
1859 { }
1860 };
1861
1862 /* l4_core -> mcbsp5 */
1863 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
1864 .master = &omap2430_l4_core_hwmod,
1865 .slave = &omap2430_mcbsp5_hwmod,
1866 .clk = "mcbsp5_ick",
1867 .addr = omap2430_mcbsp5_addrs,
1868 .user = OCP_USER_MPU | OCP_USER_SDMA,
1869 };
1870
1871 /* mcbsp5 slave ports */
1872 static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
1873 &omap2430_l4_core__mcbsp5,
1874 };
1875
1876 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
1877 .name = "mcbsp5",
1878 .class = &omap2430_mcbsp_hwmod_class,
1879 .mpu_irqs = omap2430_mcbsp5_irqs,
1880 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
1881 .main_clk = "mcbsp5_fck",
1882 .prcm = {
1883 .omap2 = {
1884 .prcm_reg_id = 1,
1885 .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
1886 .module_offs = CORE_MOD,
1887 .idlest_reg_id = 2,
1888 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
1889 },
1890 },
1891 .slaves = omap2430_mcbsp5_slaves,
1892 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
1893 };
1894
1895 /* MMC/SD/SDIO common */
1896
1897 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
1898 .rev_offs = 0x1fc,
1899 .sysc_offs = 0x10,
1900 .syss_offs = 0x14,
1901 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1902 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1903 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1904 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1905 .sysc_fields = &omap_hwmod_sysc_type1,
1906 };
1907
1908 static struct omap_hwmod_class omap2430_mmc_class = {
1909 .name = "mmc",
1910 .sysc = &omap2430_mmc_sysc,
1911 };
1912
1913 /* MMC/SD/SDIO1 */
1914
1915 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
1916 { .irq = 83 },
1917 { .irq = -1 }
1918 };
1919
1920 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
1921 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
1922 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
1923 { .dma_req = -1 }
1924 };
1925
1926 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
1927 { .role = "dbck", .clk = "mmchsdb1_fck" },
1928 };
1929
1930 static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
1931 &omap2430_l4_core__mmc1,
1932 };
1933
1934 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1935 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1936 };
1937
1938 static struct omap_hwmod omap2430_mmc1_hwmod = {
1939 .name = "mmc1",
1940 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1941 .mpu_irqs = omap2430_mmc1_mpu_irqs,
1942 .sdma_reqs = omap2430_mmc1_sdma_reqs,
1943 .opt_clks = omap2430_mmc1_opt_clks,
1944 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
1945 .main_clk = "mmchs1_fck",
1946 .prcm = {
1947 .omap2 = {
1948 .module_offs = CORE_MOD,
1949 .prcm_reg_id = 2,
1950 .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
1951 .idlest_reg_id = 2,
1952 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
1953 },
1954 },
1955 .dev_attr = &mmc1_dev_attr,
1956 .slaves = omap2430_mmc1_slaves,
1957 .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
1958 .class = &omap2430_mmc_class,
1959 };
1960
1961 /* MMC/SD/SDIO2 */
1962
1963 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
1964 { .irq = 86 },
1965 { .irq = -1 }
1966 };
1967
1968 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
1969 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
1970 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
1971 { .dma_req = -1 }
1972 };
1973
1974 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
1975 { .role = "dbck", .clk = "mmchsdb2_fck" },
1976 };
1977
1978 static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
1979 &omap2430_l4_core__mmc2,
1980 };
1981
1982 static struct omap_hwmod omap2430_mmc2_hwmod = {
1983 .name = "mmc2",
1984 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1985 .mpu_irqs = omap2430_mmc2_mpu_irqs,
1986 .sdma_reqs = omap2430_mmc2_sdma_reqs,
1987 .opt_clks = omap2430_mmc2_opt_clks,
1988 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
1989 .main_clk = "mmchs2_fck",
1990 .prcm = {
1991 .omap2 = {
1992 .module_offs = CORE_MOD,
1993 .prcm_reg_id = 2,
1994 .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
1995 .idlest_reg_id = 2,
1996 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
1997 },
1998 },
1999 .slaves = omap2430_mmc2_slaves,
2000 .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
2001 .class = &omap2430_mmc_class,
2002 };
2003
2004 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2005 &omap2430_l3_main_hwmod,
2006 &omap2430_l4_core_hwmod,
2007 &omap2430_l4_wkup_hwmod,
2008 &omap2430_mpu_hwmod,
2009 &omap2430_iva_hwmod,
2010
2011 &omap2430_timer1_hwmod,
2012 &omap2430_timer2_hwmod,
2013 &omap2430_timer3_hwmod,
2014 &omap2430_timer4_hwmod,
2015 &omap2430_timer5_hwmod,
2016 &omap2430_timer6_hwmod,
2017 &omap2430_timer7_hwmod,
2018 &omap2430_timer8_hwmod,
2019 &omap2430_timer9_hwmod,
2020 &omap2430_timer10_hwmod,
2021 &omap2430_timer11_hwmod,
2022 &omap2430_timer12_hwmod,
2023
2024 &omap2430_wd_timer2_hwmod,
2025 &omap2430_uart1_hwmod,
2026 &omap2430_uart2_hwmod,
2027 &omap2430_uart3_hwmod,
2028 /* dss class */
2029 &omap2430_dss_core_hwmod,
2030 &omap2430_dss_dispc_hwmod,
2031 &omap2430_dss_rfbi_hwmod,
2032 &omap2430_dss_venc_hwmod,
2033 /* i2c class */
2034 &omap2430_i2c1_hwmod,
2035 &omap2430_i2c2_hwmod,
2036 &omap2430_mmc1_hwmod,
2037 &omap2430_mmc2_hwmod,
2038
2039 /* gpio class */
2040 &omap2430_gpio1_hwmod,
2041 &omap2430_gpio2_hwmod,
2042 &omap2430_gpio3_hwmod,
2043 &omap2430_gpio4_hwmod,
2044 &omap2430_gpio5_hwmod,
2045
2046 /* dma_system class*/
2047 &omap2430_dma_system_hwmod,
2048
2049 /* mcbsp class */
2050 &omap2430_mcbsp1_hwmod,
2051 &omap2430_mcbsp2_hwmod,
2052 &omap2430_mcbsp3_hwmod,
2053 &omap2430_mcbsp4_hwmod,
2054 &omap2430_mcbsp5_hwmod,
2055
2056 /* mailbox class */
2057 &omap2430_mailbox_hwmod,
2058
2059 /* mcspi class */
2060 &omap2430_mcspi1_hwmod,
2061 &omap2430_mcspi2_hwmod,
2062 &omap2430_mcspi3_hwmod,
2063
2064 /* usbotg class*/
2065 &omap2430_usbhsotg_hwmod,
2066
2067 NULL,
2068 };
2069
2070 int __init omap2430_hwmod_init(void)
2071 {
2072 return omap_hwmod_register(omap2430_hwmods);
2073 }