arch/blackfin/include/asm/bfin_serial.h

   1 /*
   2  * bfin_serial.h - Blackfin UART/Serial definitions
   3  *
   4  * Copyright 2006-2010 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #ifndef __BFIN_ASM_SERIAL_H__
  10 #define __BFIN_ASM_SERIAL_H__
  11
  12 #include <linux/serial_core.h>
  13 #include <linux/spinlock.h>
  14 #include <mach/anomaly.h>
  15 #include <mach/bfin_serial.h>
  16
  17 #if defined(CONFIG_BFIN_UART0_CTSRTS) || \
  18     defined(CONFIG_BFIN_UART1_CTSRTS) || \
  19     defined(CONFIG_BFIN_UART2_CTSRTS) || \
  20     defined(CONFIG_BFIN_UART3_CTSRTS)
  21 # ifdef BFIN_UART_BF54X_STYLE
  22 #  define CONFIG_SERIAL_BFIN_HARD_CTSRTS
  23 # else
  24 #  define CONFIG_SERIAL_BFIN_CTSRTS
  25 # endif
  26 #endif
  27
  28 struct circ_buf;
  29 struct timer_list;
  30 struct work_struct;
  31
  32 struct bfin_serial_port {
  33         struct uart_port port;
  34         unsigned int old_status;
  35         int tx_irq;
  36         int rx_irq;
  37         int status_irq;
  38 #ifndef BFIN_UART_BF54X_STYLE
  39         unsigned int lsr;
  40 #endif
  41 #ifdef CONFIG_SERIAL_BFIN_DMA
  42         int tx_done;
  43         int tx_count;
  44         struct circ_buf rx_dma_buf;
  45         struct timer_list rx_dma_timer;
  46         int rx_dma_nrows;
  47         spinlock_t rx_lock;
  48         unsigned int tx_dma_channel;
  49         unsigned int rx_dma_channel;
  50         struct work_struct tx_dma_workqueue;
  51 #elif ANOMALY_05000363
  52         unsigned int anomaly_threshold;
  53 #endif
  54 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
  55         defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
  56         int cts_pin;
  57         int rts_pin;
  58 #endif
  59 };
  60
  61 /* UART_LCR Masks */
  62 #define WLS(x)                   (((x)-5) & 0x03)  /* Word Length Select */
  63 #define STB                      0x04  /* Stop Bits */
  64 #define PEN                      0x08  /* Parity Enable */
  65 #define EPS                      0x10  /* Even Parity Select */
  66 #define STP                      0x20  /* Stick Parity */
  67 #define SB                       0x40  /* Set Break */
  68 #define DLAB                     0x80  /* Divisor Latch Access */
  69
  70 /* UART_LSR Masks */
  71 #define DR                       0x01  /* Data Ready */
  72 #define OE                       0x02  /* Overrun Error */
  73 #define PE                       0x04  /* Parity Error */
  74 #define FE                       0x08  /* Framing Error */
  75 #define BI                       0x10  /* Break Interrupt */
  76 #define THRE                     0x20  /* THR Empty */
  77 #define TEMT                     0x40  /* TSR and UART_THR Empty */
  78 #define TFI                      0x80  /* Transmission Finished Indicator */
  79
  80 /* UART_IER Masks */
  81 #define ERBFI                    0x01  /* Enable Receive Buffer Full Interrupt */
  82 #define ETBEI                    0x02  /* Enable Transmit Buffer Empty Interrupt */
  83 #define ELSI                     0x04  /* Enable RX Status Interrupt */
  84 #define EDSSI                    0x08  /* Enable Modem Status Interrupt */
  85 #define EDTPTI                   0x10  /* Enable DMA Transmit PIRQ Interrupt */
  86 #define ETFI                     0x20  /* Enable Transmission Finished Interrupt */
  87 #define ERFCI                    0x40  /* Enable Receive FIFO Count Interrupt */
  88
  89 /* UART_MCR Masks */
  90 #define XOFF                     0x01  /* Transmitter Off */
  91 #define MRTS                     0x02  /* Manual Request To Send */
  92 #define RFIT                     0x04  /* Receive FIFO IRQ Threshold */
  93 #define RFRT                     0x08  /* Receive FIFO RTS Threshold */
  94 #define LOOP_ENA                 0x10  /* Loopback Mode Enable */
  95 #define FCPOL                    0x20  /* Flow Control Pin Polarity */
  96 #define ARTS                     0x40  /* Automatic Request To Send */
  97 #define ACTS                     0x80  /* Automatic Clear To Send */
  98
  99 /* UART_MSR Masks */
 100 #define SCTS                     0x01  /* Sticky CTS */
 101 #define CTS                      0x10  /* Clear To Send */
 102 #define RFCS                     0x20  /* Receive FIFO Count Status */
 103
 104 /* UART_GCTL Masks */
 105 #define UCEN                     0x01  /* Enable UARTx Clocks */
 106 #define IREN                     0x02  /* Enable IrDA Mode */
 107 #define TPOLC                    0x04  /* IrDA TX Polarity Change */
 108 #define RPOLC                    0x08  /* IrDA RX Polarity Change */
 109 #define FPE                      0x10  /* Force Parity Error On Transmit */
 110 #define FFE                      0x20  /* Force Framing Error On Transmit */
 111
 112 #ifdef BFIN_UART_BF54X_STYLE
 113 # define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)        */
 114 # define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)       */
 115 # define OFFSET_GCTL             0x08  /* Global Control Register         */
 116 # define OFFSET_LCR              0x0C  /* Line Control Register           */
 117 # define OFFSET_MCR              0x10  /* Modem Control Register          */
 118 # define OFFSET_LSR              0x14  /* Line Status Register            */
 119 # define OFFSET_MSR              0x18  /* Modem Status Register           */
 120 # define OFFSET_SCR              0x1C  /* SCR Scratch Register            */
 121 # define OFFSET_IER_SET          0x20  /* Set Interrupt Enable Register   */
 122 # define OFFSET_IER_CLEAR        0x24  /* Clear Interrupt Enable Register */
 123 # define OFFSET_THR              0x28  /* Transmit Holding register       */
 124 # define OFFSET_RBR              0x2C  /* Receive Buffer register         */
 125 #else /* BF533 style */
 126 # define OFFSET_THR              0x00  /* Transmit Holding register         */
 127 # define OFFSET_RBR              0x00  /* Receive Buffer register           */
 128 # define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)          */
 129 # define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)         */
 130 # define OFFSET_IER              0x04  /* Interrupt Enable Register         */
 131 # define OFFSET_IIR              0x08  /* Interrupt Identification Register */
 132 # define OFFSET_LCR              0x0C  /* Line Control Register             */
 133 # define OFFSET_MCR              0x10  /* Modem Control Register            */
 134 # define OFFSET_LSR              0x14  /* Line Status Register              */
 135 # define OFFSET_MSR              0x18  /* Modem Status Register             */
 136 # define OFFSET_SCR              0x1C  /* SCR Scratch Register              */
 137 # define OFFSET_GCTL             0x24  /* Global Control Register           */
 138 /* code should not need IIR, so force build error if they use it */
 139 # undef OFFSET_IIR
 140 #endif
 141
 142 /*
 143  * All Blackfin system MMRs are padded to 32bits even if the register
 144  * itself is only 16bits.  So use a helper macro to streamline this.
 145  */
 146 #define __BFP(m) u16 m; u16 __pad_##m
 147 struct bfin_uart_regs {
 148 #ifdef BFIN_UART_BF54X_STYLE
 149         __BFP(dll);
 150         __BFP(dlh);
 151         __BFP(gctl);
 152         __BFP(lcr);
 153         __BFP(mcr);
 154         __BFP(lsr);
 155         __BFP(msr);
 156         __BFP(scr);
 157         __BFP(ier_set);
 158         __BFP(ier_clear);
 159         __BFP(thr);
 160         __BFP(rbr);
 161 #else
 162         union {
 163                 u16 dll;
 164                 u16 thr;
 165                 const u16 rbr;
 166         };
 167         const u16 __pad0;
 168         union {
 169                 u16 dlh;
 170                 u16 ier;
 171         };
 172         const u16 __pad1;
 173         const __BFP(iir);
 174         __BFP(lcr);
 175         __BFP(mcr);
 176         __BFP(lsr);
 177         __BFP(msr);
 178         __BFP(scr);
 179         const u32 __pad2;
 180         __BFP(gctl);
 181 #endif
 182 };
 183 #undef __BFP
 184
 185 #ifndef port_membase
 186 # define port_membase(p) 0
 187 #endif
 188
 189 #define UART_GET_CHAR(p)      bfin_read16(port_membase(p) + OFFSET_RBR)
 190 #define UART_GET_DLL(p)       bfin_read16(port_membase(p) + OFFSET_DLL)
 191 #define UART_GET_DLH(p)       bfin_read16(port_membase(p) + OFFSET_DLH)
 192 #define UART_GET_GCTL(p)      bfin_read16(port_membase(p) + OFFSET_GCTL)
 193 #define UART_GET_LCR(p)       bfin_read16(port_membase(p) + OFFSET_LCR)
 194 #define UART_GET_MCR(p)       bfin_read16(port_membase(p) + OFFSET_MCR)
 195 #define UART_GET_MSR(p)       bfin_read16(port_membase(p) + OFFSET_MSR)
 196
 197 #define UART_PUT_CHAR(p, v)   bfin_write16(port_membase(p) + OFFSET_THR, v)
 198 #define UART_PUT_DLL(p, v)    bfin_write16(port_membase(p) + OFFSET_DLL, v)
 199 #define UART_PUT_DLH(p, v)    bfin_write16(port_membase(p) + OFFSET_DLH, v)
 200 #define UART_PUT_GCTL(p, v)   bfin_write16(port_membase(p) + OFFSET_GCTL, v)
 201 #define UART_PUT_LCR(p, v)    bfin_write16(port_membase(p) + OFFSET_LCR, v)
 202 #define UART_PUT_MCR(p, v)    bfin_write16(port_membase(p) + OFFSET_MCR, v)
 203
 204 #ifdef BFIN_UART_BF54X_STYLE
 205
 206 #define UART_CLEAR_IER(p, v)  bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
 207 #define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER_SET)
 208 #define UART_SET_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
 209
 210 #define UART_CLEAR_DLAB(p)    /* MMRs not muxed on BF54x */
 211 #define UART_SET_DLAB(p)      /* MMRs not muxed on BF54x */
 212
 213 #define UART_CLEAR_LSR(p)     bfin_write16(port_membase(p) + OFFSET_LSR, -1)
 214 #define UART_GET_LSR(p)       bfin_read16(port_membase(p) + OFFSET_LSR)
 215 #define UART_PUT_LSR(p, v)    bfin_write16(port_membase(p) + OFFSET_LSR, v)
 216
 217 /* This handles hard CTS/RTS */
 218 #define BFIN_UART_CTSRTS_HARD
 219 #define UART_CLEAR_SCTS(p)      bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
 220 #define UART_GET_CTS(x)         (UART_GET_MSR(x) & CTS)
 221 #define UART_DISABLE_RTS(x)     UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
 222 #define UART_ENABLE_RTS(x)      UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
 223 #define UART_ENABLE_INTS(x, v)  UART_SET_IER(x, v)
 224 #define UART_DISABLE_INTS(x)    UART_CLEAR_IER(x, 0xF)
 225
 226 #else /* BF533 style */
 227
 228 #define UART_CLEAR_IER(p, v)  UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
 229 #define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER)
 230 #define UART_PUT_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER, v)
 231 #define UART_SET_IER(p, v)    UART_PUT_IER(p, UART_GET_IER(p) | (v))
 232
 233 #define UART_CLEAR_DLAB(p)    do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
 234 #define UART_SET_DLAB(p)      do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
 235
 236 #ifndef put_lsr_cache
 237 # define put_lsr_cache(p, v)
 238 #endif
 239 #ifndef get_lsr_cache
 240 # define get_lsr_cache(p) 0
 241 #endif
 242
 243 /* The hardware clears the LSR bits upon read, so we need to cache
 244  * some of the more fun bits in software so they don't get lost
 245  * when checking the LSR in other code paths (TX).
 246  */
 247 static inline void UART_CLEAR_LSR(void *p)
 248 {
 249         put_lsr_cache(p, 0);
 250         bfin_write16(port_membase(p) + OFFSET_LSR, -1);
 251 }
 252 static inline unsigned int UART_GET_LSR(void *p)
 253 {
 254         unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
 255         put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
 256         return lsr | get_lsr_cache(p);
 257 }
 258 static inline void UART_PUT_LSR(void *p, uint16_t val)
 259 {
 260         put_lsr_cache(p, get_lsr_cache(p) & ~val);
 261 }
 262
 263 /* This handles soft CTS/RTS */
 264 #define UART_GET_CTS(x)        gpio_get_value((x)->cts_pin)
 265 #define UART_DISABLE_RTS(x)    gpio_set_value((x)->rts_pin, 1)
 266 #define UART_ENABLE_RTS(x)     gpio_set_value((x)->rts_pin, 0)
 267 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
 268 #define UART_DISABLE_INTS(x)   UART_PUT_IER(x, 0)
 269
 270 #endif
 271
 272 #ifndef BFIN_UART_TX_FIFO_SIZE
 273 # define BFIN_UART_TX_FIFO_SIZE 2
 274 #endif
 275
 276 #endif /* __BFIN_ASM_SERIAL_H__ */