arch/microblaze/kernel/intc.c

   1 /*
   2  * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2007-2009 PetaLogix
   4  * Copyright (C) 2006 Atmark Techno, Inc.
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License. See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/irq.h>
  13 #include <asm/page.h>
  14 #include <linux/io.h>
  15 #include <linux/bug.h>
  16
  17 #include <asm/prom.h>
  18 #include <asm/irq.h>
  19
  20 #ifdef CONFIG_SELFMOD_INTC
  21 #include <asm/selfmod.h>
  22 #define INTC_BASE       BARRIER_BASE_ADDR
  23 #else
  24 static unsigned int intc_baseaddr;
  25 #define INTC_BASE       intc_baseaddr
  26 #endif
  27
  28 unsigned int nr_irq;
  29
  30 /* No one else should require these constants, so define them locally here. */
  31 #define ISR 0x00                        /* Interrupt Status Register */
  32 #define IPR 0x04                        /* Interrupt Pending Register */
  33 #define IER 0x08                        /* Interrupt Enable Register */
  34 #define IAR 0x0c                        /* Interrupt Acknowledge Register */
  35 #define SIE 0x10                        /* Set Interrupt Enable bits */
  36 #define CIE 0x14                        /* Clear Interrupt Enable bits */
  37 #define IVR 0x18                        /* Interrupt Vector Register */
  38 #define MER 0x1c                        /* Master Enable Register */
  39
  40 #define MER_ME (1<<0)
  41 #define MER_HIE (1<<1)
  42
  43 static void intc_enable_or_unmask(struct irq_data *d)
  44 {
  45         unsigned long mask = 1 << d->hwirq;
  46
  47         pr_debug("enable_or_unmask: %ld\n", d->hwirq);
  48         out_be32(INTC_BASE + SIE, mask);
  49
  50         /* ack level irqs because they can't be acked during
  51          * ack function since the handle_level_irq function
  52          * acks the irq before calling the interrupt handler
  53          */
  54         if (irqd_is_level_type(d))
  55                 out_be32(INTC_BASE + IAR, mask);
  56 }
  57
  58 static void intc_disable_or_mask(struct irq_data *d)
  59 {
  60         pr_debug("disable: %ld\n", d->hwirq);
  61         out_be32(INTC_BASE + CIE, 1 << d->hwirq);
  62 }
  63
  64 static void intc_ack(struct irq_data *d)
  65 {
  66         pr_debug("ack: %ld\n", d->hwirq);
  67         out_be32(INTC_BASE + IAR, 1 << d->hwirq);
  68 }
  69
  70 static void intc_mask_ack(struct irq_data *d)
  71 {
  72         unsigned long mask = 1 << d->hwirq;
  73
  74         pr_debug("disable_and_ack: %ld\n", d->hwirq);
  75         out_be32(INTC_BASE + CIE, mask);
  76         out_be32(INTC_BASE + IAR, mask);
  77 }
  78
  79 static struct irq_chip intc_dev = {
  80         .name = "Xilinx INTC",
  81         .irq_unmask = intc_enable_or_unmask,
  82         .irq_mask = intc_disable_or_mask,
  83         .irq_ack = intc_ack,
  84         .irq_mask_ack = intc_mask_ack,
  85 };
  86
  87 unsigned int get_irq(struct pt_regs *regs)
  88 {
  89         int irq;
  90
  91         /*
  92          * NOTE: This function is the one that needs to be improved in
  93          * order to handle multiple interrupt controllers. It currently
  94          * is hardcoded to check for interrupts only on the first INTC.
  95          */
  96         irq = in_be32(INTC_BASE + IVR) + NO_IRQ_OFFSET;
  97         pr_debug("get_irq: %d\n", irq);
  98
  99         return irq;
 100 }
 101
 102 void __init init_IRQ(void)
 103 {
 104         u32 i, intr_mask;
 105         struct device_node *intc = NULL;
 106 #ifdef CONFIG_SELFMOD_INTC
 107         unsigned int intc_baseaddr = 0;
 108         static int arr_func[] = {
 109                                 (int)&get_irq,
 110                                 (int)&intc_enable_or_unmask,
 111                                 (int)&intc_disable_or_mask,
 112                                 (int)&intc_mask_ack,
 113                                 (int)&intc_ack,
 114                                 (int)&intc_end,
 115                                 0
 116                         };
 117 #endif
 118         intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a");
 119         BUG_ON(!intc);
 120
 121         intc_baseaddr = be32_to_cpup(of_get_property(intc, "reg", NULL));
 122         intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
 123         nr_irq = be32_to_cpup(of_get_property(intc,
 124                                                 "xlnx,num-intr-inputs", NULL));
 125
 126         intr_mask =
 127                 be32_to_cpup(of_get_property(intc, "xlnx,kind-of-intr", NULL));
 128         if (intr_mask > (u32)((1ULL << nr_irq) - 1))
 129                 printk(KERN_INFO " ERROR: Mismatch in kind-of-intr param\n");
 130
 131 #ifdef CONFIG_SELFMOD_INTC
 132         selfmod_function((int *) arr_func, intc_baseaddr);
 133 #endif
 134         printk(KERN_INFO "XPS intc #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
 135                 intc_baseaddr, nr_irq, intr_mask);
 136
 137         /*
 138          * Disable all external interrupts until they are
 139          * explicity requested.
 140          */
 141         out_be32(intc_baseaddr + IER, 0);
 142
 143         /* Acknowledge any pending interrupts just in case. */
 144         out_be32(intc_baseaddr + IAR, 0xffffffff);
 145
 146         /* Turn on the Master Enable. */
 147         out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);
 148
 149         for (i = IRQ_OFFSET; i < (nr_irq + IRQ_OFFSET); ++i) {
 150                 if (intr_mask & (0x00000001 << (i - IRQ_OFFSET))) {
 151                         irq_set_chip_and_handler_name(i, &intc_dev,
 152                                 handle_edge_irq, "edge");
 153                         irq_clear_status_flags(i, IRQ_LEVEL);
 154                 } else {
 155                         irq_set_chip_and_handler_name(i, &intc_dev,
 156                                 handle_level_irq, "level");
 157                         irq_set_status_flags(i, IRQ_LEVEL);
 158                 }
 159                 irq_get_irq_data(i)->hwirq = i - IRQ_OFFSET;
 160         }
 161 }