arch/parisc/include/asm/assembly.h

   1 /*
   2  * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
   3  * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
   4  * Copyright (C) 1999 SuSE GmbH
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; either version 2, or (at your option)
   9  *    any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  *
  16  *    You should have received a copy of the GNU General Public License
  17  *    along with this program; if not, write to the Free Software
  18  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef _PARISC_ASSEMBLY_H
  22 #define _PARISC_ASSEMBLY_H
  23
  24 #define CALLEE_FLOAT_FRAME_SIZE 80
  25
  26 #ifdef CONFIG_64BIT
  27 #define LDREG   ldd
  28 #define STREG   std
  29 #define LDREGX  ldd,s
  30 #define LDREGM  ldd,mb
  31 #define STREGM  std,ma
  32 #define SHRREG  shrd
  33 #define SHLREG  shld
  34 #define ANDCM   andcm,*
  35 #define COND(x) * ## x
  36 #define RP_OFFSET       16
  37 #define FRAME_SIZE      128
  38 #define CALLEE_REG_FRAME_SIZE   144
  39 #define ASM_ULONG_INSN  .dword
  40 #else   /* CONFIG_64BIT */
  41 #define LDREG   ldw
  42 #define STREG   stw
  43 #define LDREGX  ldwx,s
  44 #define LDREGM  ldwm
  45 #define STREGM  stwm
  46 #define SHRREG  shr
  47 #define SHLREG  shlw
  48 #define ANDCM   andcm
  49 #define COND(x) x
  50 #define RP_OFFSET       20
  51 #define FRAME_SIZE      64
  52 #define CALLEE_REG_FRAME_SIZE   128
  53 #define ASM_ULONG_INSN  .word
  54 #endif
  55
  56 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
  57
  58 #ifdef CONFIG_PA20
  59 #define LDCW            ldcw,co
  60 #define BL              b,l
  61 # ifdef CONFIG_64BIT
  62 #  define LEVEL         2.0w
  63 # else
  64 #  define LEVEL         2.0
  65 # endif
  66 #else
  67 #define LDCW            ldcw
  68 #define BL              bl
  69 #define LEVEL           1.1
  70 #endif
  71
  72 #ifdef __ASSEMBLY__
  73
  74 #ifdef CONFIG_64BIT
  75 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
  76  * work around that for now... */
  77         .level 2.0w
  78 #endif
  79
  80 #include <asm/asm-offsets.h>
  81 #include <asm/page.h>
  82 #include <asm/types.h>
  83
  84 #include <asm/asmregs.h>
  85
  86         sp      =       30
  87         gp      =       27
  88         ipsw    =       22
  89
  90         /*
  91          * We provide two versions of each macro to convert from physical
  92          * to virtual and vice versa. The "_r1" versions take one argument
  93          * register, but trashes r1 to do the conversion. The other
  94          * version takes two arguments: a src and destination register.
  95          * However, the source and destination registers can not be
  96          * the same register.
  97          */
  98
  99         .macro  tophys  grvirt, grphys
 100         ldil    L%(__PAGE_OFFSET), \grphys
 101         sub     \grvirt, \grphys, \grphys
 102         .endm
 103
 104         .macro  tovirt  grphys, grvirt
 105         ldil    L%(__PAGE_OFFSET), \grvirt
 106         add     \grphys, \grvirt, \grvirt
 107         .endm
 108
 109         .macro  tophys_r1  gr
 110         ldil    L%(__PAGE_OFFSET), %r1
 111         sub     \gr, %r1, \gr
 112         .endm
 113
 114         .macro  tovirt_r1  gr
 115         ldil    L%(__PAGE_OFFSET), %r1
 116         add     \gr, %r1, \gr
 117         .endm
 118
 119         .macro delay value
 120         ldil    L%\value, 1
 121         ldo     R%\value(1), 1
 122         addib,UV,n -1,1,.
 123         addib,NUV,n -1,1,.+8
 124         nop
 125         .endm
 126
 127         .macro  debug value
 128         .endm
 129
 130
 131         /* Shift Left - note the r and t can NOT be the same! */
 132         .macro shl r, sa, t
 133         dep,z   \r, 31-(\sa), 32-(\sa), \t
 134         .endm
 135
 136         /* The PA 2.0 shift left */
 137         .macro shlw r, sa, t
 138         depw,z  \r, 31-(\sa), 32-(\sa), \t
 139         .endm
 140
 141         /* And the PA 2.0W shift left */
 142         .macro shld r, sa, t
 143         depd,z  \r, 63-(\sa), 64-(\sa), \t
 144         .endm
 145
 146         /* Shift Right - note the r and t can NOT be the same! */
 147         .macro shr r, sa, t
 148         extru \r, 31-(\sa), 32-(\sa), \t
 149         .endm
 150
 151         /* pa20w version of shift right */
 152         .macro shrd r, sa, t
 153         extrd,u \r, 63-(\sa), 64-(\sa), \t
 154         .endm
 155
 156         /* load 32-bit 'value' into 'reg' compensating for the ldil
 157          * sign-extension when running in wide mode.
 158          * WARNING!! neither 'value' nor 'reg' can be expressions
 159          * containing '.'!!!! */
 160         .macro  load32 value, reg
 161         ldil    L%\value, \reg
 162         ldo     R%\value(\reg), \reg
 163         .endm
 164
 165         .macro loadgp
 166 #ifdef CONFIG_64BIT
 167         ldil            L%__gp, %r27
 168         ldo             R%__gp(%r27), %r27
 169 #else
 170         ldil            L%$global$, %r27
 171         ldo             R%$global$(%r27), %r27
 172 #endif
 173         .endm
 174
 175 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
 176 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
 177 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
 178 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
 179
 180         .macro  save_general    regs
 181         STREG %r1, PT_GR1 (\regs)
 182         STREG %r2, PT_GR2 (\regs)
 183         STREG %r3, PT_GR3 (\regs)
 184         STREG %r4, PT_GR4 (\regs)
 185         STREG %r5, PT_GR5 (\regs)
 186         STREG %r6, PT_GR6 (\regs)
 187         STREG %r7, PT_GR7 (\regs)
 188         STREG %r8, PT_GR8 (\regs)
 189         STREG %r9, PT_GR9 (\regs)
 190         STREG %r10, PT_GR10(\regs)
 191         STREG %r11, PT_GR11(\regs)
 192         STREG %r12, PT_GR12(\regs)
 193         STREG %r13, PT_GR13(\regs)
 194         STREG %r14, PT_GR14(\regs)
 195         STREG %r15, PT_GR15(\regs)
 196         STREG %r16, PT_GR16(\regs)
 197         STREG %r17, PT_GR17(\regs)
 198         STREG %r18, PT_GR18(\regs)
 199         STREG %r19, PT_GR19(\regs)
 200         STREG %r20, PT_GR20(\regs)
 201         STREG %r21, PT_GR21(\regs)
 202         STREG %r22, PT_GR22(\regs)
 203         STREG %r23, PT_GR23(\regs)
 204         STREG %r24, PT_GR24(\regs)
 205         STREG %r25, PT_GR25(\regs)
 206         /* r26 is saved in get_stack and used to preserve a value across virt_map */
 207         STREG %r27, PT_GR27(\regs)
 208         STREG %r28, PT_GR28(\regs)
 209         /* r29 is saved in get_stack and used to point to saved registers */
 210         /* r30 stack pointer saved in get_stack */
 211         STREG %r31, PT_GR31(\regs)
 212         .endm
 213
 214         .macro  rest_general    regs
 215         /* r1 used as a temp in rest_stack and is restored there */
 216         LDREG PT_GR2 (\regs), %r2
 217         LDREG PT_GR3 (\regs), %r3
 218         LDREG PT_GR4 (\regs), %r4
 219         LDREG PT_GR5 (\regs), %r5
 220         LDREG PT_GR6 (\regs), %r6
 221         LDREG PT_GR7 (\regs), %r7
 222         LDREG PT_GR8 (\regs), %r8
 223         LDREG PT_GR9 (\regs), %r9
 224         LDREG PT_GR10(\regs), %r10
 225         LDREG PT_GR11(\regs), %r11
 226         LDREG PT_GR12(\regs), %r12
 227         LDREG PT_GR13(\regs), %r13
 228         LDREG PT_GR14(\regs), %r14
 229         LDREG PT_GR15(\regs), %r15
 230         LDREG PT_GR16(\regs), %r16
 231         LDREG PT_GR17(\regs), %r17
 232         LDREG PT_GR18(\regs), %r18
 233         LDREG PT_GR19(\regs), %r19
 234         LDREG PT_GR20(\regs), %r20
 235         LDREG PT_GR21(\regs), %r21
 236         LDREG PT_GR22(\regs), %r22
 237         LDREG PT_GR23(\regs), %r23
 238         LDREG PT_GR24(\regs), %r24
 239         LDREG PT_GR25(\regs), %r25
 240         LDREG PT_GR26(\regs), %r26
 241         LDREG PT_GR27(\regs), %r27
 242         LDREG PT_GR28(\regs), %r28
 243         /* r29 points to register save area, and is restored in rest_stack */
 244         /* r30 stack pointer restored in rest_stack */
 245         LDREG PT_GR31(\regs), %r31
 246         .endm
 247
 248         .macro  save_fp         regs
 249         fstd,ma  %fr0, 8(\regs)
 250         fstd,ma  %fr1, 8(\regs)
 251         fstd,ma  %fr2, 8(\regs)
 252         fstd,ma  %fr3, 8(\regs)
 253         fstd,ma  %fr4, 8(\regs)
 254         fstd,ma  %fr5, 8(\regs)
 255         fstd,ma  %fr6, 8(\regs)
 256         fstd,ma  %fr7, 8(\regs)
 257         fstd,ma  %fr8, 8(\regs)
 258         fstd,ma  %fr9, 8(\regs)
 259         fstd,ma %fr10, 8(\regs)
 260         fstd,ma %fr11, 8(\regs)
 261         fstd,ma %fr12, 8(\regs)
 262         fstd,ma %fr13, 8(\regs)
 263         fstd,ma %fr14, 8(\regs)
 264         fstd,ma %fr15, 8(\regs)
 265         fstd,ma %fr16, 8(\regs)
 266         fstd,ma %fr17, 8(\regs)
 267         fstd,ma %fr18, 8(\regs)
 268         fstd,ma %fr19, 8(\regs)
 269         fstd,ma %fr20, 8(\regs)
 270         fstd,ma %fr21, 8(\regs)
 271         fstd,ma %fr22, 8(\regs)
 272         fstd,ma %fr23, 8(\regs)
 273         fstd,ma %fr24, 8(\regs)
 274         fstd,ma %fr25, 8(\regs)
 275         fstd,ma %fr26, 8(\regs)
 276         fstd,ma %fr27, 8(\regs)
 277         fstd,ma %fr28, 8(\regs)
 278         fstd,ma %fr29, 8(\regs)
 279         fstd,ma %fr30, 8(\regs)
 280         fstd    %fr31, 0(\regs)
 281         .endm
 282
 283         .macro  rest_fp         regs
 284         fldd    0(\regs),        %fr31
 285         fldd,mb -8(\regs),       %fr30
 286         fldd,mb -8(\regs),       %fr29
 287         fldd,mb -8(\regs),       %fr28
 288         fldd,mb -8(\regs),       %fr27
 289         fldd,mb -8(\regs),       %fr26
 290         fldd,mb -8(\regs),       %fr25
 291         fldd,mb -8(\regs),       %fr24
 292         fldd,mb -8(\regs),       %fr23
 293         fldd,mb -8(\regs),       %fr22
 294         fldd,mb -8(\regs),       %fr21
 295         fldd,mb -8(\regs),       %fr20
 296         fldd,mb -8(\regs),       %fr19
 297         fldd,mb -8(\regs),       %fr18
 298         fldd,mb -8(\regs),       %fr17
 299         fldd,mb -8(\regs),       %fr16
 300         fldd,mb -8(\regs),       %fr15
 301         fldd,mb -8(\regs),       %fr14
 302         fldd,mb -8(\regs),       %fr13
 303         fldd,mb -8(\regs),       %fr12
 304         fldd,mb -8(\regs),       %fr11
 305         fldd,mb -8(\regs),       %fr10
 306         fldd,mb -8(\regs),       %fr9
 307         fldd,mb -8(\regs),       %fr8
 308         fldd,mb -8(\regs),       %fr7
 309         fldd,mb -8(\regs),       %fr6
 310         fldd,mb -8(\regs),       %fr5
 311         fldd,mb -8(\regs),       %fr4
 312         fldd,mb -8(\regs),       %fr3
 313         fldd,mb -8(\regs),       %fr2
 314         fldd,mb -8(\regs),       %fr1
 315         fldd,mb -8(\regs),       %fr0
 316         .endm
 317
 318         .macro  callee_save_float
 319         fstd,ma  %fr12, 8(%r30)
 320         fstd,ma  %fr13, 8(%r30)
 321         fstd,ma  %fr14, 8(%r30)
 322         fstd,ma  %fr15, 8(%r30)
 323         fstd,ma  %fr16, 8(%r30)
 324         fstd,ma  %fr17, 8(%r30)
 325         fstd,ma  %fr18, 8(%r30)
 326         fstd,ma  %fr19, 8(%r30)
 327         fstd,ma  %fr20, 8(%r30)
 328         fstd,ma  %fr21, 8(%r30)
 329         .endm
 330
 331         .macro  callee_rest_float
 332         fldd,mb -8(%r30),   %fr21
 333         fldd,mb -8(%r30),   %fr20
 334         fldd,mb -8(%r30),   %fr19
 335         fldd,mb -8(%r30),   %fr18
 336         fldd,mb -8(%r30),   %fr17
 337         fldd,mb -8(%r30),   %fr16
 338         fldd,mb -8(%r30),   %fr15
 339         fldd,mb -8(%r30),   %fr14
 340         fldd,mb -8(%r30),   %fr13
 341         fldd,mb -8(%r30),   %fr12
 342         .endm
 343
 344 #ifdef CONFIG_64BIT
 345         .macro  callee_save
 346         std,ma    %r3,   CALLEE_REG_FRAME_SIZE(%r30)
 347         mfctl     %cr27, %r3
 348         std       %r4,  -136(%r30)
 349         std       %r5,  -128(%r30)
 350         std       %r6,  -120(%r30)
 351         std       %r7,  -112(%r30)
 352         std       %r8,  -104(%r30)
 353         std       %r9,   -96(%r30)
 354         std      %r10,   -88(%r30)
 355         std      %r11,   -80(%r30)
 356         std      %r12,   -72(%r30)
 357         std      %r13,   -64(%r30)
 358         std      %r14,   -56(%r30)
 359         std      %r15,   -48(%r30)
 360         std      %r16,   -40(%r30)
 361         std      %r17,   -32(%r30)
 362         std      %r18,   -24(%r30)
 363         std       %r3,   -16(%r30)
 364         .endm
 365
 366         .macro  callee_rest
 367         ldd      -16(%r30),    %r3
 368         ldd      -24(%r30),   %r18
 369         ldd      -32(%r30),   %r17
 370         ldd      -40(%r30),   %r16
 371         ldd      -48(%r30),   %r15
 372         ldd      -56(%r30),   %r14
 373         ldd      -64(%r30),   %r13
 374         ldd      -72(%r30),   %r12
 375         ldd      -80(%r30),   %r11
 376         ldd      -88(%r30),   %r10
 377         ldd      -96(%r30),    %r9
 378         ldd     -104(%r30),    %r8
 379         ldd     -112(%r30),    %r7
 380         ldd     -120(%r30),    %r6
 381         ldd     -128(%r30),    %r5
 382         ldd     -136(%r30),    %r4
 383         mtctl   %r3, %cr27
 384         ldd,mb  -CALLEE_REG_FRAME_SIZE(%r30),    %r3
 385         .endm
 386
 387 #else /* ! CONFIG_64BIT */
 388
 389         .macro  callee_save
 390         stw,ma   %r3,   CALLEE_REG_FRAME_SIZE(%r30)
 391         mfctl    %cr27, %r3
 392         stw      %r4,   -124(%r30)
 393         stw      %r5,   -120(%r30)
 394         stw      %r6,   -116(%r30)
 395         stw      %r7,   -112(%r30)
 396         stw      %r8,   -108(%r30)
 397         stw      %r9,   -104(%r30)
 398         stw      %r10,  -100(%r30)
 399         stw      %r11,   -96(%r30)
 400         stw      %r12,   -92(%r30)
 401         stw      %r13,   -88(%r30)
 402         stw      %r14,   -84(%r30)
 403         stw      %r15,   -80(%r30)
 404         stw      %r16,   -76(%r30)
 405         stw      %r17,   -72(%r30)
 406         stw      %r18,   -68(%r30)
 407         stw       %r3,   -64(%r30)
 408         .endm
 409
 410         .macro  callee_rest
 411         ldw      -64(%r30),    %r3
 412         ldw      -68(%r30),   %r18
 413         ldw      -72(%r30),   %r17
 414         ldw      -76(%r30),   %r16
 415         ldw      -80(%r30),   %r15
 416         ldw      -84(%r30),   %r14
 417         ldw      -88(%r30),   %r13
 418         ldw      -92(%r30),   %r12
 419         ldw      -96(%r30),   %r11
 420         ldw     -100(%r30),   %r10
 421         ldw     -104(%r30),   %r9
 422         ldw     -108(%r30),   %r8
 423         ldw     -112(%r30),   %r7
 424         ldw     -116(%r30),   %r6
 425         ldw     -120(%r30),   %r5
 426         ldw     -124(%r30),   %r4
 427         mtctl   %r3, %cr27
 428         ldw,mb  -CALLEE_REG_FRAME_SIZE(%r30),   %r3
 429         .endm
 430 #endif /* ! CONFIG_64BIT */
 431
 432         .macro  save_specials   regs
 433
 434         SAVE_SP  (%sr0, PT_SR0 (\regs))
 435         SAVE_SP  (%sr1, PT_SR1 (\regs))
 436         SAVE_SP  (%sr2, PT_SR2 (\regs))
 437         SAVE_SP  (%sr3, PT_SR3 (\regs))
 438         SAVE_SP  (%sr4, PT_SR4 (\regs))
 439         SAVE_SP  (%sr5, PT_SR5 (\regs))
 440         SAVE_SP  (%sr6, PT_SR6 (\regs))
 441         SAVE_SP  (%sr7, PT_SR7 (\regs))
 442
 443         SAVE_CR  (%cr17, PT_IASQ0(\regs))
 444         mtctl    %r0,   %cr17
 445         SAVE_CR  (%cr17, PT_IASQ1(\regs))
 446
 447         SAVE_CR  (%cr18, PT_IAOQ0(\regs))
 448         mtctl    %r0,   %cr18
 449         SAVE_CR  (%cr18, PT_IAOQ1(\regs))
 450
 451 #ifdef CONFIG_64BIT
 452         /* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0
 453          * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
 454          * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise
 455          * we lose the 6th bit on a save/restore over interrupt.
 456          */
 457         mfctl,w  %cr11, %r1
 458         STREG    %r1, PT_SAR (\regs)
 459 #else
 460         SAVE_CR  (%cr11, PT_SAR  (\regs))
 461 #endif
 462         SAVE_CR  (%cr19, PT_IIR  (\regs))
 463
 464         /*
 465          * Code immediately following this macro (in intr_save) relies
 466          * on r8 containing ipsw.
 467          */
 468         mfctl    %cr22, %r8
 469         STREG    %r8,   PT_PSW(\regs)
 470         .endm
 471
 472         .macro  rest_specials   regs
 473
 474         REST_SP  (%sr0, PT_SR0 (\regs))
 475         REST_SP  (%sr1, PT_SR1 (\regs))
 476         REST_SP  (%sr2, PT_SR2 (\regs))
 477         REST_SP  (%sr3, PT_SR3 (\regs))
 478         REST_SP  (%sr4, PT_SR4 (\regs))
 479         REST_SP  (%sr5, PT_SR5 (\regs))
 480         REST_SP  (%sr6, PT_SR6 (\regs))
 481         REST_SP  (%sr7, PT_SR7 (\regs))
 482
 483         REST_CR (%cr17, PT_IASQ0(\regs))
 484         REST_CR (%cr17, PT_IASQ1(\regs))
 485
 486         REST_CR (%cr18, PT_IAOQ0(\regs))
 487         REST_CR (%cr18, PT_IAOQ1(\regs))
 488
 489         REST_CR (%cr11, PT_SAR  (\regs))
 490
 491         REST_CR (%cr22, PT_PSW  (\regs))
 492         .endm
 493
 494
 495         /* First step to create a "relied upon translation"
 496          * See PA 2.0 Arch. page F-4 and F-5.
 497          *
 498          * The ssm was originally necessary due to a "PCxT bug".
 499          * But someone decided it needed to be added to the architecture
 500          * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
 501          * It's been carried forward into PA 2.0 Arch as well. :^(
 502          *
 503          * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
 504          * rsm/ssm prevents the ifetch unit from speculatively fetching
 505          * instructions past this line in the code stream.
 506          * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
 507          */
 508         .macro  pcxt_ssm_bug
 509         rsm     PSW_SM_I,%r0
 510         nop     /* 1 */
 511         nop     /* 2 */
 512         nop     /* 3 */
 513         nop     /* 4 */
 514         nop     /* 5 */
 515         nop     /* 6 */
 516         nop     /* 7 */
 517         .endm
 518
 519 #endif /* __ASSEMBLY__ */
 520 #endif