?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Use dentry_path() to create full path to inode object
[pohmelfs.git] / drivers / isdn / hisax / hfc4s8s_l1.c
blob384d5118e325a992a2c9b9aa2ab56573a3935d84
1 /*************************************************************************/
2 /* $Id: hfc4s8s_l1.c,v 1.10 2005/02/09 16:31:09 martinb1 Exp $ */
3 /* HFC-4S/8S low layer interface for Cologne Chip HFC-4S/8S isdn chips */
4 /* The low layer (L1) is implemented as a loadable module for usage with */
5 /* the HiSax isdn driver for passive cards. */
6 /* */
7 /* Author: Werner Cornelius */
8 /* (C) 2003 Cornelius Consult (werner@cornelius-consult.de) */
9 /* */
10 /* Driver maintained by Cologne Chip */
11 /* - Martin Bachem, support@colognechip.com */
12 /* */
13 /* This driver only works with chip revisions >= 1, older revision 0 */
14 /* engineering samples (only first manufacturer sample cards) will not */
15 /* work and are rejected by the driver. */
16 /* */
17 /* This file distributed under the GNU GPL. */
18 /* */
19 /* See Version History at the end of this file */
20 /* */
21 /*************************************************************************/
22
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/slab.h>
29 #include <linux/timer.h>
30 #include <linux/skbuff.h>
31 #include <linux/wait.h>
32 #include <asm/io.h>
33 #include "hisax_if.h"
34 #include "hfc4s8s_l1.h"
35
36 static const char hfc4s8s_rev[] = "Revision: 1.10";
37
38 /***************************************************************/
39 /* adjustable transparent mode fifo threshold */
40 /* The value defines the used fifo threshold with the equation */
41 /* */
42 /* notify number of bytes = 2 * 2 ^ TRANS_FIFO_THRES */
43 /* */
44 /* The default value is 5 which results in a buffer size of 64 */
45 /* and an interrupt rate of 8ms. */
46 /* The maximum value is 7 due to fifo size restrictions. */
47 /* Values below 3-4 are not recommended due to high interrupt */
48 /* load of the processor. For non critical applications the */
49 /* value should be raised to 7 to reduce any interrupt overhead*/
50 /***************************************************************/
51 #define TRANS_FIFO_THRES 5
52
53 /*************/
54 /* constants */
55 /*************/
56 #define CLOCKMODE_0 0 /* ext. 24.576 MhZ clk freq, int. single clock mode */
57 #define CLOCKMODE_1 1 /* ext. 49.576 MhZ clk freq, int. single clock mode */
58 #define CHIP_ID_SHIFT 4
59 #define HFC_MAX_ST 8
60 #define MAX_D_FRAME_SIZE 270
61 #define MAX_B_FRAME_SIZE 1536
62 #define TRANS_TIMER_MODE (TRANS_FIFO_THRES & 0xf)
63 #define TRANS_FIFO_BYTES (2 << TRANS_FIFO_THRES)
64 #define MAX_F_CNT 0x0f
65
66 #define CLKDEL_NT 0x6c
67 #define CLKDEL_TE 0xf
68 #define CTRL0_NT 4
69 #define CTRL0_TE 0
70
71 #define L1_TIMER_T4 2 /* minimum in jiffies */
72 #define L1_TIMER_T3 (7 * HZ) /* activation timeout */
73 #define L1_TIMER_T1 ((120 * HZ) / 1000) /* NT mode deactivation timeout */
74
75
76 /******************/
77 /* types and vars */
78 /******************/
79 static int card_cnt;
80
81 /* private driver_data */
82 typedef struct {
83 int chip_id;
84 int clock_mode;
85 int max_st_ports;
86 char *device_name;
87 } hfc4s8s_param;
88
89 static struct pci_device_id hfc4s8s_ids[] = {
90 {.vendor = PCI_VENDOR_ID_CCD,
91 .device = PCI_DEVICE_ID_4S,
92 .subvendor = 0x1397,
93 .subdevice = 0x08b4,
94 .driver_data =
95 (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_0, 4,
96 "HFC-4S Evaluation Board"}),
97 },
98 {.vendor = PCI_VENDOR_ID_CCD,
99 .device = PCI_DEVICE_ID_8S,
100 .subvendor = 0x1397,
101 .subdevice = 0x16b8,
102 .driver_data =
103 (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_0, 8,
104 "HFC-8S Evaluation Board"}),
105 },
106 {.vendor = PCI_VENDOR_ID_CCD,
107 .device = PCI_DEVICE_ID_4S,
108 .subvendor = 0x1397,
109 .subdevice = 0xb520,
110 .driver_data =
111 (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_1, 4,
112 "IOB4ST"}),
113 },
114 {.vendor = PCI_VENDOR_ID_CCD,
115 .device = PCI_DEVICE_ID_8S,
116 .subvendor = 0x1397,
117 .subdevice = 0xb522,
118 .driver_data =
119 (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_1, 8,
120 "IOB8ST"}),
121 },
122 {}
123 };
124
125 MODULE_DEVICE_TABLE(pci, hfc4s8s_ids);
126
127 MODULE_AUTHOR("Werner Cornelius, werner@cornelius-consult.de");
128 MODULE_DESCRIPTION("ISDN layer 1 for Cologne Chip HFC-4S/8S chips");
129 MODULE_LICENSE("GPL");
130
131 /***********/
132 /* layer 1 */
133 /***********/
134 struct hfc4s8s_btype {
135 spinlock_t lock;
136 struct hisax_b_if b_if;
137 struct hfc4s8s_l1 *l1p;
138 struct sk_buff_head tx_queue;
139 struct sk_buff *tx_skb;
140 struct sk_buff *rx_skb;
141 __u8 *rx_ptr;
142 int tx_cnt;
143 int bchan;
144 int mode;
145 };
146
147 struct _hfc4s8s_hw;
148
149 struct hfc4s8s_l1 {
150 spinlock_t lock;
151 struct _hfc4s8s_hw *hw; /* pointer to hardware area */
152 int l1_state; /* actual l1 state */
153 struct timer_list l1_timer; /* layer 1 timer structure */
154 int nt_mode; /* set to nt mode */
155 int st_num; /* own index */
156 int enabled; /* interface is enabled */
157 struct sk_buff_head d_tx_queue; /* send queue */
158 int tx_cnt; /* bytes to send */
159 struct hisax_d_if d_if; /* D-channel interface */
160 struct hfc4s8s_btype b_ch[2]; /* B-channel data */
161 struct hisax_b_if *b_table[2];
162 };
163
164 /**********************/
165 /* hardware structure */
166 /**********************/
167 typedef struct _hfc4s8s_hw {
168 spinlock_t lock;
169
170 int cardnum;
171 int ifnum;
172 int iobase;
173 int nt_mode;
174 u_char *membase;
175 u_char *hw_membase;
176 void *pdev;
177 int max_fifo;
178 hfc4s8s_param driver_data;
179 int irq;
180 int fifo_sched_cnt;
181 struct work_struct tqueue;
182 struct hfc4s8s_l1 l1[HFC_MAX_ST];
183 char card_name[60];
184 struct {
185 u_char r_irq_ctrl;
186 u_char r_ctrl0;
187 volatile u_char r_irq_statech; /* active isdn l1 status */
188 u_char r_irqmsk_statchg; /* enabled isdn status ints */
189 u_char r_irq_fifo_blx[8]; /* fifo status registers */
190 u_char fifo_rx_trans_enables[8]; /* mask for enabled transparent rx fifos */
191 u_char fifo_slow_timer_service[8]; /* mask for fifos needing slower timer service */
192 volatile u_char r_irq_oview; /* contents of overview register */
193 volatile u_char timer_irq;
194 int timer_usg_cnt; /* number of channels using timer */
195 } mr;
196 } hfc4s8s_hw;
197
198
199
200 /***************************/
201 /* inline function defines */
202 /***************************/
203 #ifdef HISAX_HFC4S8S_PCIMEM /* inline functions memory mapped */
204
205 /* memory write and dummy IO read to avoid PCI byte merge problems */
206 #define Write_hfc8(a,b,c) {(*((volatile u_char *)(a->membase+b)) = c); inb(a->iobase+4);}
207 /* memory write without dummy IO access for fifo data access */
208 #define fWrite_hfc8(a,b,c) (*((volatile u_char *)(a->membase+b)) = c)
209 #define Read_hfc8(a,b) (*((volatile u_char *)(a->membase+b)))
210 #define Write_hfc16(a,b,c) (*((volatile unsigned short *)(a->membase+b)) = c)
211 #define Read_hfc16(a,b) (*((volatile unsigned short *)(a->membase+b)))
212 #define Write_hfc32(a,b,c) (*((volatile unsigned long *)(a->membase+b)) = c)
213 #define Read_hfc32(a,b) (*((volatile unsigned long *)(a->membase+b)))
214 #define wait_busy(a) {while ((Read_hfc8(a, R_STATUS) & M_BUSY));}
215 #define PCI_ENA_MEMIO 0x03
216
217 #else
218
219 /* inline functions io mapped */
220 static inline void
221 SetRegAddr(hfc4s8s_hw * a, u_char b)
222 {
223 outb(b, (a->iobase) + 4);
224 }
225
226 static inline u_char
227 GetRegAddr(hfc4s8s_hw * a)
228 {
229 return (inb((volatile u_int) (a->iobase + 4)));
230 }
231
232
233 static inline void
234 Write_hfc8(hfc4s8s_hw * a, u_char b, u_char c)
235 {
236 SetRegAddr(a, b);
237 outb(c, a->iobase);
238 }
239
240 static inline void
241 fWrite_hfc8(hfc4s8s_hw * a, u_char c)
242 {
243 outb(c, a->iobase);
244 }
245
246 static inline void
247 Write_hfc16(hfc4s8s_hw * a, u_char b, u_short c)
248 {
249 SetRegAddr(a, b);
250 outw(c, a->iobase);
251 }
252
253 static inline void
254 Write_hfc32(hfc4s8s_hw * a, u_char b, u_long c)
255 {
256 SetRegAddr(a, b);
257 outl(c, a->iobase);
258 }
259
260 static inline void
261 fWrite_hfc32(hfc4s8s_hw * a, u_long c)
262 {
263 outl(c, a->iobase);
264 }
265
266 static inline u_char
267 Read_hfc8(hfc4s8s_hw * a, u_char b)
268 {
269 SetRegAddr(a, b);
270 return (inb((volatile u_int) a->iobase));
271 }
272
273 static inline u_char
274 fRead_hfc8(hfc4s8s_hw * a)
275 {
276 return (inb((volatile u_int) a->iobase));
277 }
278
279
280 static inline u_short
281 Read_hfc16(hfc4s8s_hw * a, u_char b)
282 {
283 SetRegAddr(a, b);
284 return (inw((volatile u_int) a->iobase));
285 }
286
287 static inline u_long
288 Read_hfc32(hfc4s8s_hw * a, u_char b)
289 {
290 SetRegAddr(a, b);
291 return (inl((volatile u_int) a->iobase));
292 }
293
294 static inline u_long
295 fRead_hfc32(hfc4s8s_hw * a)
296 {
297 return (inl((volatile u_int) a->iobase));
298 }
299
300 static inline void
301 wait_busy(hfc4s8s_hw * a)
302 {
303 SetRegAddr(a, R_STATUS);
304 while (inb((volatile u_int) a->iobase) & M_BUSY);
305 }
306
307 #define PCI_ENA_REGIO 0x01
308
309 #endif /* HISAX_HFC4S8S_PCIMEM */
310
311 /******************************************************/
312 /* function to read critical counter registers that */
313 /* may be updated by the chip during read */
314 /******************************************************/
315 static u_char
316 Read_hfc8_stable(hfc4s8s_hw * hw, int reg)
317 {
318 u_char ref8;
319 u_char in8;
320 ref8 = Read_hfc8(hw, reg);
321 while (((in8 = Read_hfc8(hw, reg)) != ref8)) {
322 ref8 = in8;
323 }
324 return in8;
325 }
326
327 static int
328 Read_hfc16_stable(hfc4s8s_hw * hw, int reg)
329 {
330 int ref16;
331 int in16;
332
333 ref16 = Read_hfc16(hw, reg);
334 while (((in16 = Read_hfc16(hw, reg)) != ref16)) {
335 ref16 = in16;
336 }
337 return in16;
338 }
339
340 /*****************************/
341 /* D-channel call from HiSax */
342 /*****************************/
343 static void
344 dch_l2l1(struct hisax_d_if *iface, int pr, void *arg)
345 {
346 struct hfc4s8s_l1 *l1 = iface->ifc.priv;
347 struct sk_buff *skb = (struct sk_buff *) arg;
348 u_long flags;
349
350 switch (pr) {
351
352 case (PH_DATA | REQUEST):
353 if (!l1->enabled) {
354 dev_kfree_skb(skb);
355 break;
356 }
357 spin_lock_irqsave(&l1->lock, flags);
358 skb_queue_tail(&l1->d_tx_queue, skb);
359 if ((skb_queue_len(&l1->d_tx_queue) == 1) &&
360 (l1->tx_cnt <= 0)) {
361 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
362 0x10;
363 spin_unlock_irqrestore(&l1->lock, flags);
364 schedule_work(&l1->hw->tqueue);
365 } else
366 spin_unlock_irqrestore(&l1->lock, flags);
367 break;
368
369 case (PH_ACTIVATE | REQUEST):
370 if (!l1->enabled)
371 break;
372 if (!l1->nt_mode) {
373 if (l1->l1_state < 6) {
374 spin_lock_irqsave(&l1->lock,
375 flags);
376
377 Write_hfc8(l1->hw, R_ST_SEL,
378 l1->st_num);
379 Write_hfc8(l1->hw, A_ST_WR_STA,
380 0x60);
381 mod_timer(&l1->l1_timer,
382 jiffies + L1_TIMER_T3);
383 spin_unlock_irqrestore(&l1->lock,
384 flags);
385 } else if (l1->l1_state == 7)
386 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
387 PH_ACTIVATE |
388 INDICATION,
389 NULL);
390 } else {
391 if (l1->l1_state != 3) {
392 spin_lock_irqsave(&l1->lock,
393 flags);
394 Write_hfc8(l1->hw, R_ST_SEL,
395 l1->st_num);
396 Write_hfc8(l1->hw, A_ST_WR_STA,
397 0x60);
398 spin_unlock_irqrestore(&l1->lock,
399 flags);
400 } else if (l1->l1_state == 3)
401 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
402 PH_ACTIVATE |
403 INDICATION,
404 NULL);
405 }
406 break;
407
408 default:
409 printk(KERN_INFO
410 "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n",
411 pr);
412 break;
413 }
414 if (!l1->enabled)
415 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
416 PH_DEACTIVATE | INDICATION, NULL);
417 } /* dch_l2l1 */
418
419 /*****************************/
420 /* B-channel call from HiSax */
421 /*****************************/
422 static void
423 bch_l2l1(struct hisax_if *ifc, int pr, void *arg)
424 {
425 struct hfc4s8s_btype *bch = ifc->priv;
426 struct hfc4s8s_l1 *l1 = bch->l1p;
427 struct sk_buff *skb = (struct sk_buff *) arg;
428 long mode = (long) arg;
429 u_long flags;
430
431 switch (pr) {
432
433 case (PH_DATA | REQUEST):
434 if (!l1->enabled || (bch->mode == L1_MODE_NULL)) {
435 dev_kfree_skb(skb);
436 break;
437 }
438 spin_lock_irqsave(&l1->lock, flags);
439 skb_queue_tail(&bch->tx_queue, skb);
440 if (!bch->tx_skb && (bch->tx_cnt <= 0)) {
441 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
442 ((bch->bchan == 1) ? 1 : 4);
443 spin_unlock_irqrestore(&l1->lock, flags);
444 schedule_work(&l1->hw->tqueue);
445 } else
446 spin_unlock_irqrestore(&l1->lock, flags);
447 break;
448
449 case (PH_ACTIVATE | REQUEST):
450 case (PH_DEACTIVATE | REQUEST):
451 if (!l1->enabled)
452 break;
453 if (pr == (PH_DEACTIVATE | REQUEST))
454 mode = L1_MODE_NULL;
455
456 switch (mode) {
457 case L1_MODE_HDLC:
458 spin_lock_irqsave(&l1->lock,
459 flags);
460 l1->hw->mr.timer_usg_cnt++;
461 l1->hw->mr.
462 fifo_slow_timer_service[l1->
463 st_num]
464 |=
465 ((bch->bchan ==
466 1) ? 0x2 : 0x8);
467 Write_hfc8(l1->hw, R_FIFO,
468 (l1->st_num * 8 +
469 ((bch->bchan ==
470 1) ? 0 : 2)));
471 wait_busy(l1->hw);
472 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */
473 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
474 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable TX interrupts for hdlc */
475 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
476 wait_busy(l1->hw);
477
478 Write_hfc8(l1->hw, R_FIFO,
479 (l1->st_num * 8 +
480 ((bch->bchan ==
481 1) ? 1 : 3)));
482 wait_busy(l1->hw);
483 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */
484 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
485 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable RX interrupts for hdlc */
486 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
487
488 Write_hfc8(l1->hw, R_ST_SEL,
489 l1->st_num);
490 l1->hw->mr.r_ctrl0 |=
491 (bch->bchan & 3);
492 Write_hfc8(l1->hw, A_ST_CTRL0,
493 l1->hw->mr.r_ctrl0);
494 bch->mode = L1_MODE_HDLC;
495 spin_unlock_irqrestore(&l1->lock,
496 flags);
497
498 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
499 PH_ACTIVATE |
500 INDICATION,
501 NULL);
502 break;
503
504 case L1_MODE_TRANS:
505 spin_lock_irqsave(&l1->lock,
506 flags);
507 l1->hw->mr.
508 fifo_rx_trans_enables[l1->
509 st_num]
510 |=
511 ((bch->bchan ==
512 1) ? 0x2 : 0x8);
513 l1->hw->mr.timer_usg_cnt++;
514 Write_hfc8(l1->hw, R_FIFO,
515 (l1->st_num * 8 +
516 ((bch->bchan ==
517 1) ? 0 : 2)));
518 wait_busy(l1->hw);
519 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */
520 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
521 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */
522 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
523 wait_busy(l1->hw);
524
525 Write_hfc8(l1->hw, R_FIFO,
526 (l1->st_num * 8 +
527 ((bch->bchan ==
528 1) ? 1 : 3)));
529 wait_busy(l1->hw);
530 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */
531 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
532 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */
533 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
534
535 Write_hfc8(l1->hw, R_ST_SEL,
536 l1->st_num);
537 l1->hw->mr.r_ctrl0 |=
538 (bch->bchan & 3);
539 Write_hfc8(l1->hw, A_ST_CTRL0,
540 l1->hw->mr.r_ctrl0);
541 bch->mode = L1_MODE_TRANS;
542 spin_unlock_irqrestore(&l1->lock,
543 flags);
544
545 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
546 PH_ACTIVATE |
547 INDICATION,
548 NULL);
549 break;
550
551 default:
552 if (bch->mode == L1_MODE_NULL)
553 break;
554 spin_lock_irqsave(&l1->lock,
555 flags);
556 l1->hw->mr.
557 fifo_slow_timer_service[l1->
558 st_num]
559 &=
560 ~((bch->bchan ==
561 1) ? 0x3 : 0xc);
562 l1->hw->mr.
563 fifo_rx_trans_enables[l1->
564 st_num]
565 &=
566 ~((bch->bchan ==
567 1) ? 0x3 : 0xc);
568 l1->hw->mr.timer_usg_cnt--;
569 Write_hfc8(l1->hw, R_FIFO,
570 (l1->st_num * 8 +
571 ((bch->bchan ==
572 1) ? 0 : 2)));
573 wait_busy(l1->hw);
574 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */
575 wait_busy(l1->hw);
576 Write_hfc8(l1->hw, R_FIFO,
577 (l1->st_num * 8 +
578 ((bch->bchan ==
579 1) ? 1 : 3)));
580 wait_busy(l1->hw);
581 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */
582 Write_hfc8(l1->hw, R_ST_SEL,
583 l1->st_num);
584 l1->hw->mr.r_ctrl0 &=
585 ~(bch->bchan & 3);
586 Write_hfc8(l1->hw, A_ST_CTRL0,
587 l1->hw->mr.r_ctrl0);
588 spin_unlock_irqrestore(&l1->lock,
589 flags);
590
591 bch->mode = L1_MODE_NULL;
592 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
593 PH_DEACTIVATE |
594 INDICATION,
595 NULL);
596 if (bch->tx_skb) {
597 dev_kfree_skb(bch->tx_skb);
598 bch->tx_skb = NULL;
599 }
600 if (bch->rx_skb) {
601 dev_kfree_skb(bch->rx_skb);
602 bch->rx_skb = NULL;
603 }
604 skb_queue_purge(&bch->tx_queue);
605 bch->tx_cnt = 0;
606 bch->rx_ptr = NULL;
607 break;
608 }
609
610 /* timer is only used when at least one b channel */
611 /* is set up to transparent mode */
612 if (l1->hw->mr.timer_usg_cnt) {
613 Write_hfc8(l1->hw, R_IRQMSK_MISC,
614 M_TI_IRQMSK);
615 } else {
616 Write_hfc8(l1->hw, R_IRQMSK_MISC, 0);
617 }
618
619 break;
620
621 default:
622 printk(KERN_INFO
623 "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n",
624 pr);
625 break;
626 }
627 if (!l1->enabled)
628 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
629 PH_DEACTIVATE | INDICATION, NULL);
630 } /* bch_l2l1 */
631
632 /**************************/
633 /* layer 1 timer function */
634 /**************************/
635 static void
636 hfc_l1_timer(struct hfc4s8s_l1 *l1)
637 {
638 u_long flags;
639
640 if (!l1->enabled)
641 return;
642
643 spin_lock_irqsave(&l1->lock, flags);
644 if (l1->nt_mode) {
645 l1->l1_state = 1;
646 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
647 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11);
648 spin_unlock_irqrestore(&l1->lock, flags);
649 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
650 PH_DEACTIVATE | INDICATION, NULL);
651 spin_lock_irqsave(&l1->lock, flags);
652 l1->l1_state = 1;
653 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1);
654 spin_unlock_irqrestore(&l1->lock, flags);
655 } else {
656 /* activation timed out */
657 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
658 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13);
659 spin_unlock_irqrestore(&l1->lock, flags);
660 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
661 PH_DEACTIVATE | INDICATION, NULL);
662 spin_lock_irqsave(&l1->lock, flags);
663 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
664 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3);
665 spin_unlock_irqrestore(&l1->lock, flags);
666 }
667 } /* hfc_l1_timer */
668
669 /****************************************/
670 /* a complete D-frame has been received */
671 /****************************************/
672 static void
673 rx_d_frame(struct hfc4s8s_l1 *l1p, int ech)
674 {
675 int z1, z2;
676 u_char f1, f2, df;
677 struct sk_buff *skb;
678 u_char *cp;
679
680
681 if (!l1p->enabled)
682 return;
683 do {
684 /* E/D RX fifo */
685 Write_hfc8(l1p->hw, R_FIFO,
686 (l1p->st_num * 8 + ((ech) ? 7 : 5)));
687 wait_busy(l1p->hw);
688
689 f1 = Read_hfc8_stable(l1p->hw, A_F1);
690 f2 = Read_hfc8(l1p->hw, A_F2);
691 df = f1 - f2;
692 if ((f1 - f2) < 0)
693 df = f1 - f2 + MAX_F_CNT + 1;
694
695
696 if (!df) {
697 return; /* no complete frame in fifo */
698 }
699
700 z1 = Read_hfc16_stable(l1p->hw, A_Z1);
701 z2 = Read_hfc16(l1p->hw, A_Z2);
702
703 z1 = z1 - z2 + 1;
704 if (z1 < 0)
705 z1 += 384;
706
707 if (!(skb = dev_alloc_skb(MAX_D_FRAME_SIZE))) {
708 printk(KERN_INFO
709 "HFC-4S/8S: Could not allocate D/E "
710 "channel receive buffer");
711 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
712 wait_busy(l1p->hw);
713 return;
714 }
715
716 if (((z1 < 4) || (z1 > MAX_D_FRAME_SIZE))) {
717 if (skb)
718 dev_kfree_skb(skb);
719 /* remove errornous D frame */
720 if (df == 1) {
721 /* reset fifo */
722 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
723 wait_busy(l1p->hw);
724 return;
725 } else {
726 /* read errornous D frame */
727
728 #ifndef HISAX_HFC4S8S_PCIMEM
729 SetRegAddr(l1p->hw, A_FIFO_DATA0);
730 #endif
731
732 while (z1 >= 4) {
733 #ifdef HISAX_HFC4S8S_PCIMEM
734 Read_hfc32(l1p->hw, A_FIFO_DATA0);
735 #else
736 fRead_hfc32(l1p->hw);
737 #endif
738 z1 -= 4;
739 }
740
741 while (z1--)
742 #ifdef HISAX_HFC4S8S_PCIMEM
743 Read_hfc8(l1p->hw, A_FIFO_DATA0);
744 #else
745 fRead_hfc8(l1p->hw);
746 #endif
747
748 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1);
749 wait_busy(l1p->hw);
750 return;
751 }
752 }
753
754 cp = skb->data;
755
756 #ifndef HISAX_HFC4S8S_PCIMEM
757 SetRegAddr(l1p->hw, A_FIFO_DATA0);
758 #endif
759
760 while (z1 >= 4) {
761 #ifdef HISAX_HFC4S8S_PCIMEM
762 *((unsigned long *) cp) =
763 Read_hfc32(l1p->hw, A_FIFO_DATA0);
764 #else
765 *((unsigned long *) cp) = fRead_hfc32(l1p->hw);
766 #endif
767 cp += 4;
768 z1 -= 4;
769 }
770
771 while (z1--)
772 #ifdef HISAX_HFC4S8S_PCIMEM
773 *cp++ = Read_hfc8(l1p->hw, A_FIFO_DATA0);
774 #else
775 *cp++ = fRead_hfc8(l1p->hw);
776 #endif
777
778 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
779 wait_busy(l1p->hw);
780
781 if (*(--cp)) {
782 dev_kfree_skb(skb);
783 } else {
784 skb->len = (cp - skb->data) - 2;
785 if (ech)
786 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc,
787 PH_DATA_E | INDICATION,
788 skb);
789 else
790 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc,
791 PH_DATA | INDICATION,
792 skb);
793 }
794 } while (1);
795 } /* rx_d_frame */
796
797 /*************************************************************/
798 /* a B-frame has been received (perhaps not fully completed) */
799 /*************************************************************/
800 static void
801 rx_b_frame(struct hfc4s8s_btype *bch)
802 {
803 int z1, z2, hdlc_complete;
804 u_char f1, f2;
805 struct hfc4s8s_l1 *l1 = bch->l1p;
806 struct sk_buff *skb;
807
808 if (!l1->enabled || (bch->mode == L1_MODE_NULL))
809 return;
810
811 do {
812 /* RX Fifo */
813 Write_hfc8(l1->hw, R_FIFO,
814 (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3)));
815 wait_busy(l1->hw);
816
817 if (bch->mode == L1_MODE_HDLC) {
818 f1 = Read_hfc8_stable(l1->hw, A_F1);
819 f2 = Read_hfc8(l1->hw, A_F2);
820 hdlc_complete = ((f1 ^ f2) & MAX_F_CNT);
821 } else
822 hdlc_complete = 0;
823 z1 = Read_hfc16_stable(l1->hw, A_Z1);
824 z2 = Read_hfc16(l1->hw, A_Z2);
825 z1 = (z1 - z2);
826 if (hdlc_complete)
827 z1++;
828 if (z1 < 0)
829 z1 += 384;
830
831 if (!z1)
832 break;
833
834 if (!(skb = bch->rx_skb)) {
835 if (!
836 (skb =
837 dev_alloc_skb((bch->mode ==
838 L1_MODE_TRANS) ? z1
839 : (MAX_B_FRAME_SIZE + 3)))) {
840 printk(KERN_ERR
841 "HFC-4S/8S: Could not allocate B "
842 "channel receive buffer");
843 return;
844 }
845 bch->rx_ptr = skb->data;
846 bch->rx_skb = skb;
847 }
848
849 skb->len = (bch->rx_ptr - skb->data) + z1;
850
851 /* HDLC length check */
852 if ((bch->mode == L1_MODE_HDLC) &&
853 ((hdlc_complete && (skb->len < 4)) ||
854 (skb->len > (MAX_B_FRAME_SIZE + 3)))) {
855
856 skb->len = 0;
857 bch->rx_ptr = skb->data;
858 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
859 wait_busy(l1->hw);
860 return;
861 }
862 #ifndef HISAX_HFC4S8S_PCIMEM
863 SetRegAddr(l1->hw, A_FIFO_DATA0);
864 #endif
865
866 while (z1 >= 4) {
867 #ifdef HISAX_HFC4S8S_PCIMEM
868 *((unsigned long *) bch->rx_ptr) =
869 Read_hfc32(l1->hw, A_FIFO_DATA0);
870 #else
871 *((unsigned long *) bch->rx_ptr) =
872 fRead_hfc32(l1->hw);
873 #endif
874 bch->rx_ptr += 4;
875 z1 -= 4;
876 }
877
878 while (z1--)
879 #ifdef HISAX_HFC4S8S_PCIMEM
880 *(bch->rx_ptr++) = Read_hfc8(l1->hw, A_FIFO_DATA0);
881 #else
882 *(bch->rx_ptr++) = fRead_hfc8(l1->hw);
883 #endif
884
885 if (hdlc_complete) {
886 /* increment f counter */
887 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
888 wait_busy(l1->hw);
889
890 /* hdlc crc check */
891 bch->rx_ptr--;
892 if (*bch->rx_ptr) {
893 skb->len = 0;
894 bch->rx_ptr = skb->data;
895 continue;
896 }
897 skb->len -= 3;
898 }
899 if (hdlc_complete || (bch->mode == L1_MODE_TRANS)) {
900 bch->rx_skb = NULL;
901 bch->rx_ptr = NULL;
902 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
903 PH_DATA | INDICATION, skb);
904 }
905
906 } while (1);
907 } /* rx_b_frame */
908
909 /********************************************/
910 /* a D-frame has been/should be transmitted */
911 /********************************************/
912 static void
913 tx_d_frame(struct hfc4s8s_l1 *l1p)
914 {
915 struct sk_buff *skb;
916 u_char f1, f2;
917 u_char *cp;
918 long cnt;
919
920 if (l1p->l1_state != 7)
921 return;
922
923 /* TX fifo */
924 Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4));
925 wait_busy(l1p->hw);
926
927 f1 = Read_hfc8(l1p->hw, A_F1);
928 f2 = Read_hfc8_stable(l1p->hw, A_F2);
929
930 if ((f1 ^ f2) & MAX_F_CNT)
931 return; /* fifo is still filled */
932
933 if (l1p->tx_cnt > 0) {
934 cnt = l1p->tx_cnt;
935 l1p->tx_cnt = 0;
936 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA | CONFIRM,
937 (void *) cnt);
938 }
939
940 if ((skb = skb_dequeue(&l1p->d_tx_queue))) {
941 cp = skb->data;
942 cnt = skb->len;
943 #ifndef HISAX_HFC4S8S_PCIMEM
944 SetRegAddr(l1p->hw, A_FIFO_DATA0);
945 #endif
946
947 while (cnt >= 4) {
948 #ifdef HISAX_HFC4S8S_PCIMEM
949 fWrite_hfc32(l1p->hw, A_FIFO_DATA0,
950 *(unsigned long *) cp);
951 #else
952 SetRegAddr(l1p->hw, A_FIFO_DATA0);
953 fWrite_hfc32(l1p->hw, *(unsigned long *) cp);
954 #endif
955 cp += 4;
956 cnt -= 4;
957 }
958
959 #ifdef HISAX_HFC4S8S_PCIMEM
960 while (cnt--)
961 fWrite_hfc8(l1p->hw, A_FIFO_DATA0, *cp++);
962 #else
963 while (cnt--)
964 fWrite_hfc8(l1p->hw, *cp++);
965 #endif
966
967 l1p->tx_cnt = skb->truesize;
968 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
969 wait_busy(l1p->hw);
970
971 dev_kfree_skb(skb);
972 }
973 } /* tx_d_frame */
974
975 /******************************************************/
976 /* a B-frame may be transmitted (or is not completed) */
977 /******************************************************/
978 static void
979 tx_b_frame(struct hfc4s8s_btype *bch)
980 {
981 struct sk_buff *skb;
982 struct hfc4s8s_l1 *l1 = bch->l1p;
983 u_char *cp;
984 int cnt, max, hdlc_num;
985 long ack_len = 0;
986
987 if (!l1->enabled || (bch->mode == L1_MODE_NULL))
988 return;
989
990 /* TX fifo */
991 Write_hfc8(l1->hw, R_FIFO,
992 (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2)));
993 wait_busy(l1->hw);
994 do {
995
996 if (bch->mode == L1_MODE_HDLC) {
997 hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT;
998 hdlc_num -=
999 (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT);
1000 if (hdlc_num < 0)
1001 hdlc_num += 16;
1002 if (hdlc_num >= 15)
1003 break; /* fifo still filled up with hdlc frames */
1004 } else
1005 hdlc_num = 0;
1006
1007 if (!(skb = bch->tx_skb)) {
1008 if (!(skb = skb_dequeue(&bch->tx_queue))) {
1009 l1->hw->mr.fifo_slow_timer_service[l1->
1010 st_num]
1011 &= ~((bch->bchan == 1) ? 1 : 4);
1012 break; /* list empty */
1013 }
1014 bch->tx_skb = skb;
1015 bch->tx_cnt = 0;
1016 }
1017
1018 if (!hdlc_num)
1019 l1->hw->mr.fifo_slow_timer_service[l1->st_num] |=
1020 ((bch->bchan == 1) ? 1 : 4);
1021 else
1022 l1->hw->mr.fifo_slow_timer_service[l1->st_num] &=
1023 ~((bch->bchan == 1) ? 1 : 4);
1024
1025 max = Read_hfc16_stable(l1->hw, A_Z2);
1026 max -= Read_hfc16(l1->hw, A_Z1);
1027 if (max <= 0)
1028 max += 384;
1029 max--;
1030
1031 if (max < 16)
1032 break; /* don't write to small amounts of bytes */
1033
1034 cnt = skb->len - bch->tx_cnt;
1035 if (cnt > max)
1036 cnt = max;
1037 cp = skb->data + bch->tx_cnt;
1038 bch->tx_cnt += cnt;
1039
1040 #ifndef HISAX_HFC4S8S_PCIMEM
1041 SetRegAddr(l1->hw, A_FIFO_DATA0);
1042 #endif
1043 while (cnt >= 4) {
1044 #ifdef HISAX_HFC4S8S_PCIMEM
1045 fWrite_hfc32(l1->hw, A_FIFO_DATA0,
1046 *(unsigned long *) cp);
1047 #else
1048 fWrite_hfc32(l1->hw, *(unsigned long *) cp);
1049 #endif
1050 cp += 4;
1051 cnt -= 4;
1052 }
1053
1054 while (cnt--)
1055 #ifdef HISAX_HFC4S8S_PCIMEM
1056 fWrite_hfc8(l1->hw, A_FIFO_DATA0, *cp++);
1057 #else
1058 fWrite_hfc8(l1->hw, *cp++);
1059 #endif
1060
1061 if (bch->tx_cnt >= skb->len) {
1062 if (bch->mode == L1_MODE_HDLC) {
1063 /* increment f counter */
1064 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
1065 }
1066 ack_len += skb->truesize;
1067 bch->tx_skb = NULL;
1068 bch->tx_cnt = 0;
1069 dev_kfree_skb(skb);
1070 } else
1071 /* Re-Select */
1072 Write_hfc8(l1->hw, R_FIFO,
1073 (l1->st_num * 8 +
1074 ((bch->bchan == 1) ? 0 : 2)));
1075 wait_busy(l1->hw);
1076 } while (1);
1077
1078 if (ack_len)
1079 bch->b_if.ifc.l1l2((struct hisax_if *) &bch->b_if,
1080 PH_DATA | CONFIRM, (void *) ack_len);
1081 } /* tx_b_frame */
1082
1083 /*************************************/
1084 /* bottom half handler for interrupt */
1085 /*************************************/
1086 static void
1087 hfc4s8s_bh(struct work_struct *work)
1088 {
1089 hfc4s8s_hw *hw = container_of(work, hfc4s8s_hw, tqueue);
1090 u_char b;
1091 struct hfc4s8s_l1 *l1p;
1092 volatile u_char *fifo_stat;
1093 int idx;
1094
1095 /* handle layer 1 state changes */
1096 b = 1;
1097 l1p = hw->l1;
1098 while (b) {
1099 if ((b & hw->mr.r_irq_statech)) {
1100 /* reset l1 event */
1101 hw->mr.r_irq_statech &= ~b;
1102 if (l1p->enabled) {
1103 if (l1p->nt_mode) {
1104 u_char oldstate = l1p->l1_state;
1105
1106 Write_hfc8(l1p->hw, R_ST_SEL,
1107 l1p->st_num);
1108 l1p->l1_state =
1109 Read_hfc8(l1p->hw,
1110 A_ST_RD_STA) & 0xf;
1111
1112 if ((oldstate == 3)
1113 && (l1p->l1_state != 3))
1114 l1p->d_if.ifc.l1l2(&l1p->
1115 d_if.
1116 ifc,
1117 PH_DEACTIVATE
1118 |
1119 INDICATION,
1120 NULL);
1121
1122 if (l1p->l1_state != 2) {
1123 del_timer(&l1p->l1_timer);
1124 if (l1p->l1_state == 3) {
1125 l1p->d_if.ifc.
1126 l1l2(&l1p->
1127 d_if.ifc,
1128 PH_ACTIVATE
1129 |
1130 INDICATION,
1131 NULL);
1132 }
1133 } else {
1134 /* allow transition */
1135 Write_hfc8(hw, A_ST_WR_STA,
1136 M_SET_G2_G3);
1137 mod_timer(&l1p->l1_timer,
1138 jiffies +
1139 L1_TIMER_T1);
1140 }
1141 printk(KERN_INFO
1142 "HFC-4S/8S: NT ch %d l1 state %d -> %d\n",
1143 l1p->st_num, oldstate,
1144 l1p->l1_state);
1145 } else {
1146 u_char oldstate = l1p->l1_state;
1147
1148 Write_hfc8(l1p->hw, R_ST_SEL,
1149 l1p->st_num);
1150 l1p->l1_state =
1151 Read_hfc8(l1p->hw,
1152 A_ST_RD_STA) & 0xf;
1153
1154 if (((l1p->l1_state == 3) &&
1155 ((oldstate == 7) ||
1156 (oldstate == 8))) ||
1157 ((timer_pending
1158 (&l1p->l1_timer))
1159 && (l1p->l1_state == 8))) {
1160 mod_timer(&l1p->l1_timer,
1161 L1_TIMER_T4 +
1162 jiffies);
1163 } else {
1164 if (l1p->l1_state == 7) {
1165 del_timer(&l1p->
1166 l1_timer);
1167 l1p->d_if.ifc.
1168 l1l2(&l1p->
1169 d_if.ifc,
1170 PH_ACTIVATE
1171 |
1172 INDICATION,
1173 NULL);
1174 tx_d_frame(l1p);
1175 }
1176 if (l1p->l1_state == 3) {
1177 if (oldstate != 3)
1178 l1p->d_if.
1179 ifc.
1180 l1l2
1181 (&l1p->
1182 d_if.
1183 ifc,
1184 PH_DEACTIVATE
1185 |
1186 INDICATION,
1187 NULL);
1188 }
1189 }
1190 printk(KERN_INFO
1191 "HFC-4S/8S: TE %d ch %d l1 state %d -> %d\n",
1192 l1p->hw->cardnum,
1193 l1p->st_num, oldstate,
1194 l1p->l1_state);
1195 }
1196 }
1197 }
1198 b <<= 1;
1199 l1p++;
1200 }
1201
1202 /* now handle the fifos */
1203 idx = 0;
1204 fifo_stat = hw->mr.r_irq_fifo_blx;
1205 l1p = hw->l1;
1206 while (idx < hw->driver_data.max_st_ports) {
1207
1208 if (hw->mr.timer_irq) {
1209 *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx];
1210 if (hw->fifo_sched_cnt <= 0) {
1211 *fifo_stat |=
1212 hw->mr.fifo_slow_timer_service[l1p->
1213 st_num];
1214 }
1215 }
1216 /* ignore fifo 6 (TX E fifo) */
1217 *fifo_stat &= 0xff - 0x40;
1218
1219 while (*fifo_stat) {
1220
1221 if (!l1p->nt_mode) {
1222 /* RX Fifo has data to read */
1223 if ((*fifo_stat & 0x20)) {
1224 *fifo_stat &= ~0x20;
1225 rx_d_frame(l1p, 0);
1226 }
1227 /* E Fifo has data to read */
1228 if ((*fifo_stat & 0x80)) {
1229 *fifo_stat &= ~0x80;
1230 rx_d_frame(l1p, 1);
1231 }
1232 /* TX Fifo completed send */
1233 if ((*fifo_stat & 0x10)) {
1234 *fifo_stat &= ~0x10;
1235 tx_d_frame(l1p);
1236 }
1237 }
1238 /* B1 RX Fifo has data to read */
1239 if ((*fifo_stat & 0x2)) {
1240 *fifo_stat &= ~0x2;
1241 rx_b_frame(l1p->b_ch);
1242 }
1243 /* B1 TX Fifo has send completed */
1244 if ((*fifo_stat & 0x1)) {
1245 *fifo_stat &= ~0x1;
1246 tx_b_frame(l1p->b_ch);
1247 }
1248 /* B2 RX Fifo has data to read */
1249 if ((*fifo_stat & 0x8)) {
1250 *fifo_stat &= ~0x8;
1251 rx_b_frame(l1p->b_ch + 1);
1252 }
1253 /* B2 TX Fifo has send completed */
1254 if ((*fifo_stat & 0x4)) {
1255 *fifo_stat &= ~0x4;
1256 tx_b_frame(l1p->b_ch + 1);
1257 }
1258 }
1259 fifo_stat++;
1260 l1p++;
1261 idx++;
1262 }
1263
1264 if (hw->fifo_sched_cnt <= 0)
1265 hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE));
1266 hw->mr.timer_irq = 0; /* clear requested timer irq */
1267 } /* hfc4s8s_bh */
1268
1269 /*********************/
1270 /* interrupt handler */
1271 /*********************/
1272 static irqreturn_t
1273 hfc4s8s_interrupt(int intno, void *dev_id)
1274 {
1275 hfc4s8s_hw *hw = dev_id;
1276 u_char b, ovr;
1277 volatile u_char *ovp;
1278 int idx;
1279 u_char old_ioreg;
1280
1281 if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN))
1282 return IRQ_NONE;
1283
1284 #ifndef HISAX_HFC4S8S_PCIMEM
1285 /* read current selected regsister */
1286 old_ioreg = GetRegAddr(hw);
1287 #endif
1288
1289 /* Layer 1 State change */
1290 hw->mr.r_irq_statech |=
1291 (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg);
1292 if (!
1293 (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA)))
1294 && !hw->mr.r_irq_statech) {
1295 #ifndef HISAX_HFC4S8S_PCIMEM
1296 SetRegAddr(hw, old_ioreg);
1297 #endif
1298 return IRQ_NONE;
1299 }
1300
1301 /* timer event */
1302 if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) {
1303 hw->mr.timer_irq = 1;
1304 hw->fifo_sched_cnt--;
1305 }
1306
1307 /* FIFO event */
1308 if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) {
1309 hw->mr.r_irq_oview |= ovr;
1310 idx = R_IRQ_FIFO_BL0;
1311 ovp = hw->mr.r_irq_fifo_blx;
1312 while (ovr) {
1313 if ((ovr & 1)) {
1314 *ovp |= Read_hfc8(hw, idx);
1315 }
1316 ovp++;
1317 idx++;
1318 ovr >>= 1;
1319 }
1320 }
1321
1322 /* queue the request to allow other cards to interrupt */
1323 schedule_work(&hw->tqueue);
1324
1325 #ifndef HISAX_HFC4S8S_PCIMEM
1326 SetRegAddr(hw, old_ioreg);
1327 #endif
1328 return IRQ_HANDLED;
1329 } /* hfc4s8s_interrupt */
1330
1331 /***********************************************************************/
1332 /* reset the complete chip, don't release the chips irq but disable it */
1333 /***********************************************************************/
1334 static void
1335 chipreset(hfc4s8s_hw * hw)
1336 {
1337 u_long flags;
1338
1339 spin_lock_irqsave(&hw->lock, flags);
1340 Write_hfc8(hw, R_CTRL, 0); /* use internal RAM */
1341 Write_hfc8(hw, R_RAM_MISC, 0); /* 32k*8 RAM */
1342 Write_hfc8(hw, R_FIFO_MD, 0); /* fifo mode 386 byte/fifo simple mode */
1343 Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */
1344 hw->mr.r_irq_ctrl = 0; /* interrupt is inactive */
1345 spin_unlock_irqrestore(&hw->lock, flags);
1346
1347 udelay(3);
1348 Write_hfc8(hw, R_CIRM, 0); /* disable reset */
1349 wait_busy(hw);
1350
1351 Write_hfc8(hw, R_PCM_MD0, M_PCM_MD); /* master mode */
1352 Write_hfc8(hw, R_RAM_MISC, M_FZ_MD); /* transmit fifo option */
1353 if (hw->driver_data.clock_mode == 1)
1354 Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK); /* PCM clk / 2 */
1355 Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE); /* timer interval */
1356
1357 memset(&hw->mr, 0, sizeof(hw->mr));
1358 } /* chipreset */
1359
1360 /********************************************/
1361 /* disable/enable hardware in nt or te mode */
1362 /********************************************/
1363 static void
1364 hfc_hardware_enable(hfc4s8s_hw * hw, int enable, int nt_mode)
1365 {
1366 u_long flags;
1367 char if_name[40];
1368 int i;
1369
1370 if (enable) {
1371 /* save system vars */
1372 hw->nt_mode = nt_mode;
1373
1374 /* enable fifo and state irqs, but not global irq enable */
1375 hw->mr.r_irq_ctrl = M_FIFO_IRQ;
1376 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1377 hw->mr.r_irqmsk_statchg = 0;
1378 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1379 Write_hfc8(hw, R_PWM_MD, 0x80);
1380 Write_hfc8(hw, R_PWM1, 26);
1381 if (!nt_mode)
1382 Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC);
1383
1384 /* enable the line interfaces and fifos */
1385 for (i = 0; i < hw->driver_data.max_st_ports; i++) {
1386 hw->mr.r_irqmsk_statchg |= (1 << i);
1387 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1388 Write_hfc8(hw, R_ST_SEL, i);
1389 Write_hfc8(hw, A_ST_CLK_DLY,
1390 ((nt_mode) ? CLKDEL_NT : CLKDEL_TE));
1391 hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE);
1392 Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0);
1393 Write_hfc8(hw, A_ST_CTRL2, 3);
1394 Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */
1395
1396 hw->l1[i].enabled = 1;
1397 hw->l1[i].nt_mode = nt_mode;
1398
1399 if (!nt_mode) {
1400 /* setup E-fifo */
1401 Write_hfc8(hw, R_FIFO, i * 8 + 7); /* E fifo */
1402 wait_busy(hw);
1403 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */
1404 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1405 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */
1406 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */
1407 wait_busy(hw);
1408
1409 /* setup D RX-fifo */
1410 Write_hfc8(hw, R_FIFO, i * 8 + 5); /* RX fifo */
1411 wait_busy(hw);
1412 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */
1413 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1414 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */
1415 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */
1416 wait_busy(hw);
1417
1418 /* setup D TX-fifo */
1419 Write_hfc8(hw, R_FIFO, i * 8 + 4); /* TX fifo */
1420 wait_busy(hw);
1421 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */
1422 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1423 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */
1424 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */
1425 wait_busy(hw);
1426 }
1427
1428 sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i);
1429
1430 if (hisax_register
1431 (&hw->l1[i].d_if, hw->l1[i].b_table, if_name,
1432 ((nt_mode) ? 3 : 2))) {
1433
1434 hw->l1[i].enabled = 0;
1435 hw->mr.r_irqmsk_statchg &= ~(1 << i);
1436 Write_hfc8(hw, R_SCI_MSK,
1437 hw->mr.r_irqmsk_statchg);
1438 printk(KERN_INFO
1439 "HFC-4S/8S: Unable to register S/T device %s, break\n",
1440 if_name);
1441 break;
1442 }
1443 }
1444 spin_lock_irqsave(&hw->lock, flags);
1445 hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN;
1446 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1447 spin_unlock_irqrestore(&hw->lock, flags);
1448 } else {
1449 /* disable hardware */
1450 spin_lock_irqsave(&hw->lock, flags);
1451 hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN;
1452 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1453 spin_unlock_irqrestore(&hw->lock, flags);
1454
1455 for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) {
1456 hw->l1[i].enabled = 0;
1457 hisax_unregister(&hw->l1[i].d_if);
1458 del_timer(&hw->l1[i].l1_timer);
1459 skb_queue_purge(&hw->l1[i].d_tx_queue);
1460 skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue);
1461 skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue);
1462 }
1463 chipreset(hw);
1464 }
1465 } /* hfc_hardware_enable */
1466
1467 /******************************************/
1468 /* disable memory mapped ports / io ports */
1469 /******************************************/
1470 static void
1471 release_pci_ports(hfc4s8s_hw * hw)
1472 {
1473 pci_write_config_word(hw->pdev, PCI_COMMAND, 0);
1474 #ifdef HISAX_HFC4S8S_PCIMEM
1475 if (hw->membase)
1476 iounmap((void *) hw->membase);
1477 #else
1478 if (hw->iobase)
1479 release_region(hw->iobase, 8);
1480 #endif
1481 }
1482
1483 /*****************************************/
1484 /* enable memory mapped ports / io ports */
1485 /*****************************************/
1486 static void
1487 enable_pci_ports(hfc4s8s_hw * hw)
1488 {
1489 #ifdef HISAX_HFC4S8S_PCIMEM
1490 pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
1491 #else
1492 pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO);
1493 #endif
1494 }
1495
1496 /*************************************/
1497 /* initialise the HFC-4s/8s hardware */
1498 /* return 0 on success. */
1499 /*************************************/
1500 static int __devinit
1501 setup_instance(hfc4s8s_hw * hw)
1502 {
1503 int err = -EIO;
1504 int i;
1505
1506 for (i = 0; i < HFC_MAX_ST; i++) {
1507 struct hfc4s8s_l1 *l1p;
1508
1509 l1p = hw->l1 + i;
1510 spin_lock_init(&l1p->lock);
1511 l1p->hw = hw;
1512 l1p->l1_timer.function = (void *) hfc_l1_timer;
1513 l1p->l1_timer.data = (long) (l1p);
1514 init_timer(&l1p->l1_timer);
1515 l1p->st_num = i;
1516 skb_queue_head_init(&l1p->d_tx_queue);
1517 l1p->d_if.ifc.priv = hw->l1 + i;
1518 l1p->d_if.ifc.l2l1 = (void *) dch_l2l1;
1519
1520 spin_lock_init(&l1p->b_ch[0].lock);
1521 l1p->b_ch[0].b_if.ifc.l2l1 = (void *) bch_l2l1;
1522 l1p->b_ch[0].b_if.ifc.priv = (void *) &l1p->b_ch[0];
1523 l1p->b_ch[0].l1p = hw->l1 + i;
1524 l1p->b_ch[0].bchan = 1;
1525 l1p->b_table[0] = &l1p->b_ch[0].b_if;
1526 skb_queue_head_init(&l1p->b_ch[0].tx_queue);
1527
1528 spin_lock_init(&l1p->b_ch[1].lock);
1529 l1p->b_ch[1].b_if.ifc.l2l1 = (void *) bch_l2l1;
1530 l1p->b_ch[1].b_if.ifc.priv = (void *) &l1p->b_ch[1];
1531 l1p->b_ch[1].l1p = hw->l1 + i;
1532 l1p->b_ch[1].bchan = 2;
1533 l1p->b_table[1] = &l1p->b_ch[1].b_if;
1534 skb_queue_head_init(&l1p->b_ch[1].tx_queue);
1535 }
1536
1537 enable_pci_ports(hw);
1538 chipreset(hw);
1539
1540 i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT;
1541 if (i != hw->driver_data.chip_id) {
1542 printk(KERN_INFO
1543 "HFC-4S/8S: invalid chip id 0x%x instead of 0x%x, card ignored\n",
1544 i, hw->driver_data.chip_id);
1545 goto out;
1546 }
1547
1548 i = Read_hfc8(hw, R_CHIP_RV) & 0xf;
1549 if (!i) {
1550 printk(KERN_INFO
1551 "HFC-4S/8S: chip revision 0 not supported, card ignored\n");
1552 goto out;
1553 }
1554
1555 INIT_WORK(&hw->tqueue, hfc4s8s_bh);
1556
1557 if (request_irq
1558 (hw->irq, hfc4s8s_interrupt, IRQF_SHARED, hw->card_name, hw)) {
1559 printk(KERN_INFO
1560 "HFC-4S/8S: unable to alloc irq %d, card ignored\n",
1561 hw->irq);
1562 goto out;
1563 }
1564 #ifdef HISAX_HFC4S8S_PCIMEM
1565 printk(KERN_INFO
1566 "HFC-4S/8S: found PCI card at membase 0x%p, irq %d\n",
1567 hw->hw_membase, hw->irq);
1568 #else
1569 printk(KERN_INFO
1570 "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n",
1571 hw->iobase, hw->irq);
1572 #endif
1573
1574 hfc_hardware_enable(hw, 1, 0);
1575
1576 return (0);
1577
1578 out:
1579 hw->irq = 0;
1580 release_pci_ports(hw);
1581 kfree(hw);
1582 return (err);
1583 }
1584
1585 /*****************************************/
1586 /* PCI hotplug interface: probe new card */
1587 /*****************************************/
1588 static int __devinit
1589 hfc4s8s_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1590 {
1591 int err = -ENOMEM;
1592 hfc4s8s_param *driver_data = (hfc4s8s_param *) ent->driver_data;
1593 hfc4s8s_hw *hw;
1594
1595 if (!(hw = kzalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) {
1596 printk(KERN_ERR "No kmem for HFC-4S/8S card\n");
1597 return (err);
1598 }
1599
1600 hw->pdev = pdev;
1601 err = pci_enable_device(pdev);
1602
1603 if (err)
1604 goto out;
1605
1606 hw->cardnum = card_cnt;
1607 sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum);
1608 printk(KERN_INFO "HFC-4S/8S: found adapter %s (%s) at %s\n",
1609 driver_data->device_name, hw->card_name, pci_name(pdev));
1610
1611 spin_lock_init(&hw->lock);
1612
1613 hw->driver_data = *driver_data;
1614 hw->irq = pdev->irq;
1615 hw->iobase = pci_resource_start(pdev, 0);
1616
1617 #ifdef HISAX_HFC4S8S_PCIMEM
1618 hw->hw_membase = (u_char *) pci_resource_start(pdev, 1);
1619 hw->membase = ioremap((ulong) hw->hw_membase, 256);
1620 #else
1621 if (!request_region(hw->iobase, 8, hw->card_name)) {
1622 printk(KERN_INFO
1623 "HFC-4S/8S: failed to rquest address space at 0x%04x\n",
1624 hw->iobase);
1625 goto out;
1626 }
1627 #endif
1628
1629 pci_set_drvdata(pdev, hw);
1630 err = setup_instance(hw);
1631 if (!err)
1632 card_cnt++;
1633 return (err);
1634
1635 out:
1636 kfree(hw);
1637 return (err);
1638 }
1639
1640 /**************************************/
1641 /* PCI hotplug interface: remove card */
1642 /**************************************/
1643 static void __devexit
1644 hfc4s8s_remove(struct pci_dev *pdev)
1645 {
1646 hfc4s8s_hw *hw = pci_get_drvdata(pdev);
1647
1648 printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum);
1649 hfc_hardware_enable(hw, 0, 0);
1650
1651 if (hw->irq)
1652 free_irq(hw->irq, hw);
1653 hw->irq = 0;
1654 release_pci_ports(hw);
1655
1656 card_cnt--;
1657 pci_disable_device(pdev);
1658 kfree(hw);
1659 return;
1660 }
1661
1662 static struct pci_driver hfc4s8s_driver = {
1663 .name = "hfc4s8s_l1",
1664 .probe = hfc4s8s_probe,
1665 .remove = __devexit_p(hfc4s8s_remove),
1666 .id_table = hfc4s8s_ids,
1667 };
1668
1669 /**********************/
1670 /* driver Module init */
1671 /**********************/
1672 static int __init
1673 hfc4s8s_module_init(void)
1674 {
1675 int err;
1676
1677 printk(KERN_INFO
1678 "HFC-4S/8S: Layer 1 driver module for HFC-4S/8S isdn chips, %s\n",
1679 hfc4s8s_rev);
1680 printk(KERN_INFO
1681 "HFC-4S/8S: (C) 2003 Cornelius Consult, www.cornelius-consult.de\n");
1682
1683 card_cnt = 0;
1684
1685 err = pci_register_driver(&hfc4s8s_driver);
1686 if (err < 0) {
1687 goto out;
1688 }
1689 printk(KERN_INFO "HFC-4S/8S: found %d cards\n", card_cnt);
1690
1691 #if !defined(CONFIG_HOTPLUG)
1692 if (err == 0) {
1693 err = -ENODEV;
1694 pci_unregister_driver(&hfc4s8s_driver);
1695 goto out;
1696 }
1697 #endif
1698
1699 return 0;
1700 out:
1701 return (err);
1702 } /* hfc4s8s_init_hw */
1703
1704 /*************************************/
1705 /* driver module exit : */
1706 /* release the HFC-4s/8s hardware */
1707 /*************************************/
1708 static void __exit
1709 hfc4s8s_module_exit(void)
1710 {
1711 pci_unregister_driver(&hfc4s8s_driver);
1712 printk(KERN_INFO "HFC-4S/8S: module removed\n");
1713 } /* hfc4s8s_release_hw */
1714
1715 module_init(hfc4s8s_module_init);
1716 module_exit(hfc4s8s_module_exit);