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[pohmelfs.git] / drivers / media / video / pxa_camera.c
blob0bd7da26d018142878c35956ae8c1126a44c5bfb
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/device.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-dev.h>
33 #include <media/videobuf-dma-sg.h>
34 #include <media/soc_camera.h>
35 #include <media/soc_mediabus.h>
36
37 #include <linux/videodev2.h>
38
39 #include <mach/dma.h>
40 #include <mach/camera.h>
41
42 #define PXA_CAM_VERSION "0.0.6"
43 #define PXA_CAM_DRV_NAME "pxa27x-camera"
44
45 /* Camera Interface */
46 #define CICR0 0x0000
47 #define CICR1 0x0004
48 #define CICR2 0x0008
49 #define CICR3 0x000C
50 #define CICR4 0x0010
51 #define CISR 0x0014
52 #define CIFR 0x0018
53 #define CITOR 0x001C
54 #define CIBR0 0x0028
55 #define CIBR1 0x0030
56 #define CIBR2 0x0038
57
58 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
59 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
60 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
61 #define CICR0_ENB (1 << 28) /* Camera interface enable */
62 #define CICR0_DIS (1 << 27) /* Camera interface disable */
63 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
64 #define CICR0_TOM (1 << 9) /* Time-out mask */
65 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
66 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
67 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
68 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
69 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
70 #define CICR0_CDM (1 << 3) /* Disable-done mask */
71 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
72 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
73 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
74
75 #define CICR1_TBIT (1 << 31) /* Transparency bit */
76 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
77 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
78 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
79 #define CICR1_RGB_F (1 << 11) /* RGB format */
80 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
81 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
82 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
83 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
84 #define CICR1_DW (0x7 << 0) /* Data width mask */
85
86 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
87 wait count mask */
88 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
89 wait count mask */
90 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
91 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
92 wait count mask */
93 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
94 wait count mask */
95
96 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
97 wait count mask */
98 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
99 wait count mask */
100 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
101 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
102 wait count mask */
103 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
104
105 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
106 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
107 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
108 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
109 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
110 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
111 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
112 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
113
114 #define CISR_FTO (1 << 15) /* FIFO time-out */
115 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
116 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
117 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
118 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
119 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
120 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
121 #define CISR_EOL (1 << 8) /* End of line */
122 #define CISR_PAR_ERR (1 << 7) /* Parity error */
123 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
124 #define CISR_CDD (1 << 5) /* Camera interface disable done */
125 #define CISR_SOF (1 << 4) /* Start of frame */
126 #define CISR_EOF (1 << 3) /* End of frame */
127 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
128 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
129 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
130
131 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
132 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
133 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
134 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
135 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
136 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
137 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
138 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
139
140 #define CICR0_SIM_MP (0 << 24)
141 #define CICR0_SIM_SP (1 << 24)
142 #define CICR0_SIM_MS (2 << 24)
143 #define CICR0_SIM_EP (3 << 24)
144 #define CICR0_SIM_ES (4 << 24)
145
146 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
147 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
148 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
149 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
150 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
151
152 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
153 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
154 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
155 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
156 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
157
158 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
159 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
160 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
161 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
162
163 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
164 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
165 CICR0_EOFM | CICR0_FOM)
166
167 /*
168 * Structures
169 */
170 enum pxa_camera_active_dma {
171 DMA_Y = 0x1,
172 DMA_U = 0x2,
173 DMA_V = 0x4,
174 };
175
176 /* descriptor needed for the PXA DMA engine */
177 struct pxa_cam_dma {
178 dma_addr_t sg_dma;
179 struct pxa_dma_desc *sg_cpu;
180 size_t sg_size;
181 int sglen;
182 };
183
184 /* buffer for one video frame */
185 struct pxa_buffer {
186 /* common v4l buffer stuff -- must be first */
187 struct videobuf_buffer vb;
188 enum v4l2_mbus_pixelcode code;
189 /* our descriptor lists for Y, U and V channels */
190 struct pxa_cam_dma dmas[3];
191 int inwork;
192 enum pxa_camera_active_dma active_dma;
193 };
194
195 struct pxa_camera_dev {
196 struct soc_camera_host soc_host;
197 /*
198 * PXA27x is only supposed to handle one camera on its Quick Capture
199 * interface. If anyone ever builds hardware to enable more than
200 * one camera, they will have to modify this driver too
201 */
202 struct soc_camera_device *icd;
203 struct clk *clk;
204
205 unsigned int irq;
206 void __iomem *base;
207
208 int channels;
209 unsigned int dma_chans[3];
210
211 struct pxacamera_platform_data *pdata;
212 struct resource *res;
213 unsigned long platform_flags;
214 unsigned long ciclk;
215 unsigned long mclk;
216 u32 mclk_divisor;
217 u16 width_flags; /* max 10 bits */
218
219 struct list_head capture;
220
221 spinlock_t lock;
222
223 struct pxa_buffer *active;
224 struct pxa_dma_desc *sg_tail[3];
225
226 u32 save_cicr[5];
227 };
228
229 struct pxa_cam {
230 unsigned long flags;
231 };
232
233 static const char *pxa_cam_driver_description = "PXA_Camera";
234
235 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
236
237 /*
238 * Videobuf operations
239 */
240 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
241 unsigned int *size)
242 {
243 struct soc_camera_device *icd = vq->priv_data;
244 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
245 icd->current_fmt->host_fmt);
246
247 if (bytes_per_line < 0)
248 return bytes_per_line;
249
250 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size);
251
252 *size = bytes_per_line * icd->user_height;
253
254 if (0 == *count)
255 *count = 32;
256 if (*size * *count > vid_limit * 1024 * 1024)
257 *count = (vid_limit * 1024 * 1024) / *size;
258
259 return 0;
260 }
261
262 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
263 {
264 struct soc_camera_device *icd = vq->priv_data;
265 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
266 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
267 int i;
268
269 BUG_ON(in_interrupt());
270
271 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
272 &buf->vb, buf->vb.baddr, buf->vb.bsize);
273
274 /*
275 * This waits until this buffer is out of danger, i.e., until it is no
276 * longer in STATE_QUEUED or STATE_ACTIVE
277 */
278 videobuf_waiton(vq, &buf->vb, 0, 0);
279 videobuf_dma_unmap(vq->dev, dma);
280 videobuf_dma_free(dma);
281
282 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
283 if (buf->dmas[i].sg_cpu)
284 dma_free_coherent(ici->v4l2_dev.dev,
285 buf->dmas[i].sg_size,
286 buf->dmas[i].sg_cpu,
287 buf->dmas[i].sg_dma);
288 buf->dmas[i].sg_cpu = NULL;
289 }
290
291 buf->vb.state = VIDEOBUF_NEEDS_INIT;
292 }
293
294 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
295 int sg_first_ofs, int size)
296 {
297 int i, offset, dma_len, xfer_len;
298 struct scatterlist *sg;
299
300 offset = sg_first_ofs;
301 for_each_sg(sglist, sg, sglen, i) {
302 dma_len = sg_dma_len(sg);
303
304 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
305 xfer_len = roundup(min(dma_len - offset, size), 8);
306
307 size = max(0, size - xfer_len);
308 offset = 0;
309 if (size == 0)
310 break;
311 }
312
313 BUG_ON(size != 0);
314 return i + 1;
315 }
316
317 /**
318 * pxa_init_dma_channel - init dma descriptors
319 * @pcdev: pxa camera device
320 * @buf: pxa buffer to find pxa dma channel
321 * @dma: dma video buffer
322 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
323 * @cibr: camera Receive Buffer Register
324 * @size: bytes to transfer
325 * @sg_first: first element of sg_list
326 * @sg_first_ofs: offset in first element of sg_list
327 *
328 * Prepares the pxa dma descriptors to transfer one camera channel.
329 * Beware sg_first and sg_first_ofs are both input and output parameters.
330 *
331 * Returns 0 or -ENOMEM if no coherent memory is available
332 */
333 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
334 struct pxa_buffer *buf,
335 struct videobuf_dmabuf *dma, int channel,
336 int cibr, int size,
337 struct scatterlist **sg_first, int *sg_first_ofs)
338 {
339 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
340 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
341 struct scatterlist *sg;
342 int i, offset, sglen;
343 int dma_len = 0, xfer_len = 0;
344
345 if (pxa_dma->sg_cpu)
346 dma_free_coherent(dev, pxa_dma->sg_size,
347 pxa_dma->sg_cpu, pxa_dma->sg_dma);
348
349 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
350 *sg_first_ofs, size);
351
352 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
353 pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
354 &pxa_dma->sg_dma, GFP_KERNEL);
355 if (!pxa_dma->sg_cpu)
356 return -ENOMEM;
357
358 pxa_dma->sglen = sglen;
359 offset = *sg_first_ofs;
360
361 dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
362 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
363
364
365 for_each_sg(*sg_first, sg, sglen, i) {
366 dma_len = sg_dma_len(sg);
367
368 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
369 xfer_len = roundup(min(dma_len - offset, size), 8);
370
371 size = max(0, size - xfer_len);
372
373 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
374 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
375 pxa_dma->sg_cpu[i].dcmd =
376 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
377 #ifdef DEBUG
378 if (!i)
379 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
380 #endif
381 pxa_dma->sg_cpu[i].ddadr =
382 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
383
384 dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
385 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
386 sg_dma_address(sg) + offset, xfer_len);
387 offset = 0;
388
389 if (size == 0)
390 break;
391 }
392
393 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
394 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
395
396 /*
397 * Handle 1 special case :
398 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
399 * to dma_len (end on PAGE boundary). In this case, the sg element
400 * for next plane should be the next after the last used to store the
401 * last scatter gather RAM page
402 */
403 if (xfer_len >= dma_len) {
404 *sg_first_ofs = xfer_len - dma_len;
405 *sg_first = sg_next(sg);
406 } else {
407 *sg_first_ofs = xfer_len;
408 *sg_first = sg;
409 }
410
411 return 0;
412 }
413
414 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
415 struct pxa_buffer *buf)
416 {
417 buf->active_dma = DMA_Y;
418 if (pcdev->channels == 3)
419 buf->active_dma |= DMA_U | DMA_V;
420 }
421
422 /*
423 * Please check the DMA prepared buffer structure in :
424 * Documentation/video4linux/pxa_camera.txt
425 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
426 * modification while DMA chain is running will work anyway.
427 */
428 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
429 struct videobuf_buffer *vb, enum v4l2_field field)
430 {
431 struct soc_camera_device *icd = vq->priv_data;
432 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
433 struct pxa_camera_dev *pcdev = ici->priv;
434 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
435 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
436 int ret;
437 int size_y, size_u = 0, size_v = 0;
438 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
439 icd->current_fmt->host_fmt);
440
441 if (bytes_per_line < 0)
442 return bytes_per_line;
443
444 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
445 vb, vb->baddr, vb->bsize);
446
447 /* Added list head initialization on alloc */
448 WARN_ON(!list_empty(&vb->queue));
449
450 #ifdef DEBUG
451 /*
452 * This can be useful if you want to see if we actually fill
453 * the buffer with something
454 */
455 memset((void *)vb->baddr, 0xaa, vb->bsize);
456 #endif
457
458 BUG_ON(NULL == icd->current_fmt);
459
460 /*
461 * I think, in buf_prepare you only have to protect global data,
462 * the actual buffer is yours
463 */
464 buf->inwork = 1;
465
466 if (buf->code != icd->current_fmt->code ||
467 vb->width != icd->user_width ||
468 vb->height != icd->user_height ||
469 vb->field != field) {
470 buf->code = icd->current_fmt->code;
471 vb->width = icd->user_width;
472 vb->height = icd->user_height;
473 vb->field = field;
474 vb->state = VIDEOBUF_NEEDS_INIT;
475 }
476
477 vb->size = bytes_per_line * vb->height;
478 if (0 != vb->baddr && vb->bsize < vb->size) {
479 ret = -EINVAL;
480 goto out;
481 }
482
483 if (vb->state == VIDEOBUF_NEEDS_INIT) {
484 int size = vb->size;
485 int next_ofs = 0;
486 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
487 struct scatterlist *sg;
488
489 ret = videobuf_iolock(vq, vb, NULL);
490 if (ret)
491 goto fail;
492
493 if (pcdev->channels == 3) {
494 size_y = size / 2;
495 size_u = size_v = size / 4;
496 } else {
497 size_y = size;
498 }
499
500 sg = dma->sglist;
501
502 /* init DMA for Y channel */
503 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
504 &sg, &next_ofs);
505 if (ret) {
506 dev_err(dev, "DMA initialization for Y/RGB failed\n");
507 goto fail;
508 }
509
510 /* init DMA for U channel */
511 if (size_u)
512 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
513 size_u, &sg, &next_ofs);
514 if (ret) {
515 dev_err(dev, "DMA initialization for U failed\n");
516 goto fail_u;
517 }
518
519 /* init DMA for V channel */
520 if (size_v)
521 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
522 size_v, &sg, &next_ofs);
523 if (ret) {
524 dev_err(dev, "DMA initialization for V failed\n");
525 goto fail_v;
526 }
527
528 vb->state = VIDEOBUF_PREPARED;
529 }
530
531 buf->inwork = 0;
532 pxa_videobuf_set_actdma(pcdev, buf);
533
534 return 0;
535
536 fail_v:
537 dma_free_coherent(dev, buf->dmas[1].sg_size,
538 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
539 fail_u:
540 dma_free_coherent(dev, buf->dmas[0].sg_size,
541 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
542 fail:
543 free_buffer(vq, buf);
544 out:
545 buf->inwork = 0;
546 return ret;
547 }
548
549 /**
550 * pxa_dma_start_channels - start DMA channel for active buffer
551 * @pcdev: pxa camera device
552 *
553 * Initialize DMA channels to the beginning of the active video buffer, and
554 * start these channels.
555 */
556 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
557 {
558 int i;
559 struct pxa_buffer *active;
560
561 active = pcdev->active;
562
563 for (i = 0; i < pcdev->channels; i++) {
564 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
565 "%s (channel=%d) ddadr=%08x\n", __func__,
566 i, active->dmas[i].sg_dma);
567 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
568 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
569 }
570 }
571
572 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
573 {
574 int i;
575
576 for (i = 0; i < pcdev->channels; i++) {
577 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
578 "%s (channel=%d)\n", __func__, i);
579 DCSR(pcdev->dma_chans[i]) = 0;
580 }
581 }
582
583 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
584 struct pxa_buffer *buf)
585 {
586 int i;
587 struct pxa_dma_desc *buf_last_desc;
588
589 for (i = 0; i < pcdev->channels; i++) {
590 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
591 buf_last_desc->ddadr = DDADR_STOP;
592
593 if (pcdev->sg_tail[i])
594 /* Link the new buffer to the old tail */
595 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
596
597 /* Update the channel tail */
598 pcdev->sg_tail[i] = buf_last_desc;
599 }
600 }
601
602 /**
603 * pxa_camera_start_capture - start video capturing
604 * @pcdev: camera device
605 *
606 * Launch capturing. DMA channels should not be active yet. They should get
607 * activated at the end of frame interrupt, to capture only whole frames, and
608 * never begin the capture of a partial frame.
609 */
610 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
611 {
612 unsigned long cicr0;
613
614 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
615 /* Enable End-Of-Frame Interrupt */
616 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
617 cicr0 &= ~CICR0_EOFM;
618 __raw_writel(cicr0, pcdev->base + CICR0);
619 }
620
621 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
622 {
623 unsigned long cicr0;
624
625 pxa_dma_stop_channels(pcdev);
626
627 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
628 __raw_writel(cicr0, pcdev->base + CICR0);
629
630 pcdev->active = NULL;
631 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
632 }
633
634 /* Called under spinlock_irqsave(&pcdev->lock, ...) */
635 static void pxa_videobuf_queue(struct videobuf_queue *vq,
636 struct videobuf_buffer *vb)
637 {
638 struct soc_camera_device *icd = vq->priv_data;
639 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
640 struct pxa_camera_dev *pcdev = ici->priv;
641 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
642
643 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
644 __func__, vb, vb->baddr, vb->bsize, pcdev->active);
645
646 list_add_tail(&vb->queue, &pcdev->capture);
647
648 vb->state = VIDEOBUF_ACTIVE;
649 pxa_dma_add_tail_buf(pcdev, buf);
650
651 if (!pcdev->active)
652 pxa_camera_start_capture(pcdev);
653 }
654
655 static void pxa_videobuf_release(struct videobuf_queue *vq,
656 struct videobuf_buffer *vb)
657 {
658 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
659 #ifdef DEBUG
660 struct soc_camera_device *icd = vq->priv_data;
661 struct device *dev = icd->parent;
662
663 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
664 vb, vb->baddr, vb->bsize);
665
666 switch (vb->state) {
667 case VIDEOBUF_ACTIVE:
668 dev_dbg(dev, "%s (active)\n", __func__);
669 break;
670 case VIDEOBUF_QUEUED:
671 dev_dbg(dev, "%s (queued)\n", __func__);
672 break;
673 case VIDEOBUF_PREPARED:
674 dev_dbg(dev, "%s (prepared)\n", __func__);
675 break;
676 default:
677 dev_dbg(dev, "%s (unknown)\n", __func__);
678 break;
679 }
680 #endif
681
682 free_buffer(vq, buf);
683 }
684
685 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
686 struct videobuf_buffer *vb,
687 struct pxa_buffer *buf)
688 {
689 int i;
690
691 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
692 list_del_init(&vb->queue);
693 vb->state = VIDEOBUF_DONE;
694 do_gettimeofday(&vb->ts);
695 vb->field_count++;
696 wake_up(&vb->done);
697 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
698 __func__, vb);
699
700 if (list_empty(&pcdev->capture)) {
701 pxa_camera_stop_capture(pcdev);
702 for (i = 0; i < pcdev->channels; i++)
703 pcdev->sg_tail[i] = NULL;
704 return;
705 }
706
707 pcdev->active = list_entry(pcdev->capture.next,
708 struct pxa_buffer, vb.queue);
709 }
710
711 /**
712 * pxa_camera_check_link_miss - check missed DMA linking
713 * @pcdev: camera device
714 *
715 * The DMA chaining is done with DMA running. This means a tiny temporal window
716 * remains, where a buffer is queued on the chain, while the chain is already
717 * stopped. This means the tailed buffer would never be transferred by DMA.
718 * This function restarts the capture for this corner case, where :
719 * - DADR() == DADDR_STOP
720 * - a videobuffer is queued on the pcdev->capture list
721 *
722 * Please check the "DMA hot chaining timeslice issue" in
723 * Documentation/video4linux/pxa_camera.txt
724 *
725 * Context: should only be called within the dma irq handler
726 */
727 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
728 {
729 int i, is_dma_stopped = 1;
730
731 for (i = 0; i < pcdev->channels; i++)
732 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
733 is_dma_stopped = 0;
734 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
735 "%s : top queued buffer=%p, dma_stopped=%d\n",
736 __func__, pcdev->active, is_dma_stopped);
737 if (pcdev->active && is_dma_stopped)
738 pxa_camera_start_capture(pcdev);
739 }
740
741 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
742 enum pxa_camera_active_dma act_dma)
743 {
744 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
745 struct pxa_buffer *buf;
746 unsigned long flags;
747 u32 status, camera_status, overrun;
748 struct videobuf_buffer *vb;
749
750 spin_lock_irqsave(&pcdev->lock, flags);
751
752 status = DCSR(channel);
753 DCSR(channel) = status;
754
755 camera_status = __raw_readl(pcdev->base + CISR);
756 overrun = CISR_IFO_0;
757 if (pcdev->channels == 3)
758 overrun |= CISR_IFO_1 | CISR_IFO_2;
759
760 if (status & DCSR_BUSERR) {
761 dev_err(dev, "DMA Bus Error IRQ!\n");
762 goto out;
763 }
764
765 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
766 dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
767 status);
768 goto out;
769 }
770
771 /*
772 * pcdev->active should not be NULL in DMA irq handler.
773 *
774 * But there is one corner case : if capture was stopped due to an
775 * overrun of channel 1, and at that same channel 2 was completed.
776 *
777 * When handling the overrun in DMA irq for channel 1, we'll stop the
778 * capture and restart it (and thus set pcdev->active to NULL). But the
779 * DMA irq handler will already be pending for channel 2. So on entering
780 * the DMA irq handler for channel 2 there will be no active buffer, yet
781 * that is normal.
782 */
783 if (!pcdev->active)
784 goto out;
785
786 vb = &pcdev->active->vb;
787 buf = container_of(vb, struct pxa_buffer, vb);
788 WARN_ON(buf->inwork || list_empty(&vb->queue));
789
790 dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
791 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
792 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
793
794 if (status & DCSR_ENDINTR) {
795 /*
796 * It's normal if the last frame creates an overrun, as there
797 * are no more DMA descriptors to fetch from QCI fifos
798 */
799 if (camera_status & overrun &&
800 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
801 dev_dbg(dev, "FIFO overrun! CISR: %x\n",
802 camera_status);
803 pxa_camera_stop_capture(pcdev);
804 pxa_camera_start_capture(pcdev);
805 goto out;
806 }
807 buf->active_dma &= ~act_dma;
808 if (!buf->active_dma) {
809 pxa_camera_wakeup(pcdev, vb, buf);
810 pxa_camera_check_link_miss(pcdev);
811 }
812 }
813
814 out:
815 spin_unlock_irqrestore(&pcdev->lock, flags);
816 }
817
818 static void pxa_camera_dma_irq_y(int channel, void *data)
819 {
820 struct pxa_camera_dev *pcdev = data;
821 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
822 }
823
824 static void pxa_camera_dma_irq_u(int channel, void *data)
825 {
826 struct pxa_camera_dev *pcdev = data;
827 pxa_camera_dma_irq(channel, pcdev, DMA_U);
828 }
829
830 static void pxa_camera_dma_irq_v(int channel, void *data)
831 {
832 struct pxa_camera_dev *pcdev = data;
833 pxa_camera_dma_irq(channel, pcdev, DMA_V);
834 }
835
836 static struct videobuf_queue_ops pxa_videobuf_ops = {
837 .buf_setup = pxa_videobuf_setup,
838 .buf_prepare = pxa_videobuf_prepare,
839 .buf_queue = pxa_videobuf_queue,
840 .buf_release = pxa_videobuf_release,
841 };
842
843 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
844 struct soc_camera_device *icd)
845 {
846 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
847 struct pxa_camera_dev *pcdev = ici->priv;
848
849 /*
850 * We must pass NULL as dev pointer, then all pci_* dma operations
851 * transform to normal dma_* ones.
852 */
853 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
854 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
855 sizeof(struct pxa_buffer), icd, &icd->video_lock);
856 }
857
858 static u32 mclk_get_divisor(struct platform_device *pdev,
859 struct pxa_camera_dev *pcdev)
860 {
861 unsigned long mclk = pcdev->mclk;
862 struct device *dev = &pdev->dev;
863 u32 div;
864 unsigned long lcdclk;
865
866 lcdclk = clk_get_rate(pcdev->clk);
867 pcdev->ciclk = lcdclk;
868
869 /* mclk <= ciclk / 4 (27.4.2) */
870 if (mclk > lcdclk / 4) {
871 mclk = lcdclk / 4;
872 dev_warn(dev, "Limiting master clock to %lu\n", mclk);
873 }
874
875 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
876 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
877
878 /* If we're not supplying MCLK, leave it at 0 */
879 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
880 pcdev->mclk = lcdclk / (2 * (div + 1));
881
882 dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
883 lcdclk, mclk, div);
884
885 return div;
886 }
887
888 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
889 unsigned long pclk)
890 {
891 /* We want a timeout > 1 pixel time, not ">=" */
892 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
893
894 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
895 }
896
897 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
898 {
899 u32 cicr4 = 0;
900
901 /* disable all interrupts */
902 __raw_writel(0x3ff, pcdev->base + CICR0);
903
904 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
905 cicr4 |= CICR4_PCLK_EN;
906 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
907 cicr4 |= CICR4_MCLK_EN;
908 if (pcdev->platform_flags & PXA_CAMERA_PCP)
909 cicr4 |= CICR4_PCP;
910 if (pcdev->platform_flags & PXA_CAMERA_HSP)
911 cicr4 |= CICR4_HSP;
912 if (pcdev->platform_flags & PXA_CAMERA_VSP)
913 cicr4 |= CICR4_VSP;
914
915 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
916
917 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
918 /* Initialise the timeout under the assumption pclk = mclk */
919 recalculate_fifo_timeout(pcdev, pcdev->mclk);
920 else
921 /* "Safe default" - 13MHz */
922 recalculate_fifo_timeout(pcdev, 13000000);
923
924 clk_enable(pcdev->clk);
925 }
926
927 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
928 {
929 clk_disable(pcdev->clk);
930 }
931
932 static irqreturn_t pxa_camera_irq(int irq, void *data)
933 {
934 struct pxa_camera_dev *pcdev = data;
935 unsigned long status, cifr, cicr0;
936 struct pxa_buffer *buf;
937 struct videobuf_buffer *vb;
938
939 status = __raw_readl(pcdev->base + CISR);
940 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
941 "Camera interrupt status 0x%lx\n", status);
942
943 if (!status)
944 return IRQ_NONE;
945
946 __raw_writel(status, pcdev->base + CISR);
947
948 if (status & CISR_EOF) {
949 /* Reset the FIFOs */
950 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
951 __raw_writel(cifr, pcdev->base + CIFR);
952
953 pcdev->active = list_first_entry(&pcdev->capture,
954 struct pxa_buffer, vb.queue);
955 vb = &pcdev->active->vb;
956 buf = container_of(vb, struct pxa_buffer, vb);
957 pxa_videobuf_set_actdma(pcdev, buf);
958
959 pxa_dma_start_channels(pcdev);
960
961 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
962 __raw_writel(cicr0, pcdev->base + CICR0);
963 }
964
965 return IRQ_HANDLED;
966 }
967
968 /*
969 * The following two functions absolutely depend on the fact, that
970 * there can be only one camera on PXA quick capture interface
971 * Called with .video_lock held
972 */
973 static int pxa_camera_add_device(struct soc_camera_device *icd)
974 {
975 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
976 struct pxa_camera_dev *pcdev = ici->priv;
977
978 if (pcdev->icd)
979 return -EBUSY;
980
981 pxa_camera_activate(pcdev);
982
983 pcdev->icd = icd;
984
985 dev_info(icd->parent, "PXA Camera driver attached to camera %d\n",
986 icd->devnum);
987
988 return 0;
989 }
990
991 /* Called with .video_lock held */
992 static void pxa_camera_remove_device(struct soc_camera_device *icd)
993 {
994 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
995 struct pxa_camera_dev *pcdev = ici->priv;
996
997 BUG_ON(icd != pcdev->icd);
998
999 dev_info(icd->parent, "PXA Camera driver detached from camera %d\n",
1000 icd->devnum);
1001
1002 /* disable capture, disable interrupts */
1003 __raw_writel(0x3ff, pcdev->base + CICR0);
1004
1005 /* Stop DMA engine */
1006 DCSR(pcdev->dma_chans[0]) = 0;
1007 DCSR(pcdev->dma_chans[1]) = 0;
1008 DCSR(pcdev->dma_chans[2]) = 0;
1009
1010 pxa_camera_deactivate(pcdev);
1011
1012 pcdev->icd = NULL;
1013 }
1014
1015 static int test_platform_param(struct pxa_camera_dev *pcdev,
1016 unsigned char buswidth, unsigned long *flags)
1017 {
1018 /*
1019 * Platform specified synchronization and pixel clock polarities are
1020 * only a recommendation and are only used during probing. The PXA270
1021 * quick capture interface supports both.
1022 */
1023 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1024 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1025 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1026 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1027 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1028 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1029 V4L2_MBUS_DATA_ACTIVE_HIGH |
1030 V4L2_MBUS_PCLK_SAMPLE_RISING |
1031 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1032
1033 /* If requested data width is supported by the platform, use it */
1034 if ((1 << (buswidth - 1)) & pcdev->width_flags)
1035 return 0;
1036
1037 return -EINVAL;
1038 }
1039
1040 static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
1041 unsigned long flags, __u32 pixfmt)
1042 {
1043 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1044 struct pxa_camera_dev *pcdev = ici->priv;
1045 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1046 unsigned long dw, bpp;
1047 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1048 int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top);
1049
1050 if (ret < 0)
1051 y_skip_top = 0;
1052
1053 /*
1054 * Datawidth is now guaranteed to be equal to one of the three values.
1055 * We fix bit-per-pixel equal to data-width...
1056 */
1057 switch (icd->current_fmt->host_fmt->bits_per_sample) {
1058 case 10:
1059 dw = 4;
1060 bpp = 0x40;
1061 break;
1062 case 9:
1063 dw = 3;
1064 bpp = 0x20;
1065 break;
1066 default:
1067 /*
1068 * Actually it can only be 8 now,
1069 * default is just to silence compiler warnings
1070 */
1071 case 8:
1072 dw = 2;
1073 bpp = 0;
1074 }
1075
1076 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1077 cicr4 |= CICR4_PCLK_EN;
1078 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1079 cicr4 |= CICR4_MCLK_EN;
1080 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1081 cicr4 |= CICR4_PCP;
1082 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1083 cicr4 |= CICR4_HSP;
1084 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1085 cicr4 |= CICR4_VSP;
1086
1087 cicr0 = __raw_readl(pcdev->base + CICR0);
1088 if (cicr0 & CICR0_ENB)
1089 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1090
1091 cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
1092
1093 switch (pixfmt) {
1094 case V4L2_PIX_FMT_YUV422P:
1095 pcdev->channels = 3;
1096 cicr1 |= CICR1_YCBCR_F;
1097 /*
1098 * Normally, pxa bus wants as input UYVY format. We allow all
1099 * reorderings of the YUV422 format, as no processing is done,
1100 * and the YUV stream is just passed through without any
1101 * transformation. Note that UYVY is the only format that
1102 * should be used if pxa framebuffer Overlay2 is used.
1103 */
1104 case V4L2_PIX_FMT_UYVY:
1105 case V4L2_PIX_FMT_VYUY:
1106 case V4L2_PIX_FMT_YUYV:
1107 case V4L2_PIX_FMT_YVYU:
1108 cicr1 |= CICR1_COLOR_SP_VAL(2);
1109 break;
1110 case V4L2_PIX_FMT_RGB555:
1111 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1112 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1113 break;
1114 case V4L2_PIX_FMT_RGB565:
1115 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1116 break;
1117 }
1118
1119 cicr2 = 0;
1120 cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
1121 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1122 cicr4 |= pcdev->mclk_divisor;
1123
1124 __raw_writel(cicr1, pcdev->base + CICR1);
1125 __raw_writel(cicr2, pcdev->base + CICR2);
1126 __raw_writel(cicr3, pcdev->base + CICR3);
1127 __raw_writel(cicr4, pcdev->base + CICR4);
1128
1129 /* CIF interrupts are not used, only DMA */
1130 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1131 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1132 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1133 __raw_writel(cicr0, pcdev->base + CICR0);
1134 }
1135
1136 static int pxa_camera_set_bus_param(struct soc_camera_device *icd)
1137 {
1138 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1139 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1140 struct pxa_camera_dev *pcdev = ici->priv;
1141 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1142 u32 pixfmt = icd->current_fmt->host_fmt->fourcc;
1143 unsigned long bus_flags, common_flags;
1144 int ret;
1145 struct pxa_cam *cam = icd->host_priv;
1146
1147 ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample,
1148 &bus_flags);
1149 if (ret < 0)
1150 return ret;
1151
1152 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1153 if (!ret) {
1154 common_flags = soc_mbus_config_compatible(&cfg,
1155 bus_flags);
1156 if (!common_flags) {
1157 dev_warn(icd->parent,
1158 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1159 cfg.flags, bus_flags);
1160 return -EINVAL;
1161 }
1162 } else if (ret != -ENOIOCTLCMD) {
1163 return ret;
1164 } else {
1165 common_flags = bus_flags;
1166 }
1167
1168 pcdev->channels = 1;
1169
1170 /* Make choises, based on platform preferences */
1171 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1172 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1173 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1174 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1175 else
1176 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1177 }
1178
1179 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1180 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1181 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1182 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1183 else
1184 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1185 }
1186
1187 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1188 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1189 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1190 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1191 else
1192 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1193 }
1194
1195 cfg.flags = common_flags;
1196 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1197 if (ret < 0 && ret != -ENOIOCTLCMD) {
1198 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1199 common_flags, ret);
1200 return ret;
1201 }
1202
1203 cam->flags = common_flags;
1204
1205 pxa_camera_setup_cicr(icd, common_flags, pixfmt);
1206
1207 return 0;
1208 }
1209
1210 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1211 unsigned char buswidth)
1212 {
1213 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1214 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1215 struct pxa_camera_dev *pcdev = ici->priv;
1216 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1217 unsigned long bus_flags, common_flags;
1218 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1219
1220 if (ret < 0)
1221 return ret;
1222
1223 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1224 if (!ret) {
1225 common_flags = soc_mbus_config_compatible(&cfg,
1226 bus_flags);
1227 if (!common_flags) {
1228 dev_warn(icd->parent,
1229 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1230 cfg.flags, bus_flags);
1231 return -EINVAL;
1232 }
1233 } else if (ret == -ENOIOCTLCMD) {
1234 ret = 0;
1235 }
1236
1237 return ret;
1238 }
1239
1240 static const struct soc_mbus_pixelfmt pxa_camera_formats[] = {
1241 {
1242 .fourcc = V4L2_PIX_FMT_YUV422P,
1243 .name = "Planar YUV422 16 bit",
1244 .bits_per_sample = 8,
1245 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1246 .order = SOC_MBUS_ORDER_LE,
1247 },
1248 };
1249
1250 /* This will be corrected as we get more formats */
1251 static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
1252 {
1253 return fmt->packing == SOC_MBUS_PACKING_NONE ||
1254 (fmt->bits_per_sample == 8 &&
1255 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
1256 (fmt->bits_per_sample > 8 &&
1257 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
1258 }
1259
1260 static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
1261 struct soc_camera_format_xlate *xlate)
1262 {
1263 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1264 struct device *dev = icd->parent;
1265 int formats = 0, ret;
1266 struct pxa_cam *cam;
1267 enum v4l2_mbus_pixelcode code;
1268 const struct soc_mbus_pixelfmt *fmt;
1269
1270 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1271 if (ret < 0)
1272 /* No more formats */
1273 return 0;
1274
1275 fmt = soc_mbus_get_fmtdesc(code);
1276 if (!fmt) {
1277 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1278 return 0;
1279 }
1280
1281 /* This also checks support for the requested bits-per-sample */
1282 ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample);
1283 if (ret < 0)
1284 return 0;
1285
1286 if (!icd->host_priv) {
1287 cam = kzalloc(sizeof(*cam), GFP_KERNEL);
1288 if (!cam)
1289 return -ENOMEM;
1290
1291 icd->host_priv = cam;
1292 } else {
1293 cam = icd->host_priv;
1294 }
1295
1296 switch (code) {
1297 case V4L2_MBUS_FMT_UYVY8_2X8:
1298 formats++;
1299 if (xlate) {
1300 xlate->host_fmt = &pxa_camera_formats[0];
1301 xlate->code = code;
1302 xlate++;
1303 dev_dbg(dev, "Providing format %s using code %d\n",
1304 pxa_camera_formats[0].name, code);
1305 }
1306 case V4L2_MBUS_FMT_VYUY8_2X8:
1307 case V4L2_MBUS_FMT_YUYV8_2X8:
1308 case V4L2_MBUS_FMT_YVYU8_2X8:
1309 case V4L2_MBUS_FMT_RGB565_2X8_LE:
1310 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
1311 if (xlate)
1312 dev_dbg(dev, "Providing format %s packed\n",
1313 fmt->name);
1314 break;
1315 default:
1316 if (!pxa_camera_packing_supported(fmt))
1317 return 0;
1318 if (xlate)
1319 dev_dbg(dev,
1320 "Providing format %s in pass-through mode\n",
1321 fmt->name);
1322 }
1323
1324 /* Generic pass-through */
1325 formats++;
1326 if (xlate) {
1327 xlate->host_fmt = fmt;
1328 xlate->code = code;
1329 xlate++;
1330 }
1331
1332 return formats;
1333 }
1334
1335 static void pxa_camera_put_formats(struct soc_camera_device *icd)
1336 {
1337 kfree(icd->host_priv);
1338 icd->host_priv = NULL;
1339 }
1340
1341 static int pxa_camera_check_frame(u32 width, u32 height)
1342 {
1343 /* limit to pxa hardware capabilities */
1344 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1345 (width & 0x01);
1346 }
1347
1348 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1349 struct v4l2_crop *a)
1350 {
1351 struct v4l2_rect *rect = &a->c;
1352 struct device *dev = icd->parent;
1353 struct soc_camera_host *ici = to_soc_camera_host(dev);
1354 struct pxa_camera_dev *pcdev = ici->priv;
1355 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1356 struct soc_camera_sense sense = {
1357 .master_clock = pcdev->mclk,
1358 .pixel_clock_max = pcdev->ciclk / 4,
1359 };
1360 struct v4l2_mbus_framefmt mf;
1361 struct pxa_cam *cam = icd->host_priv;
1362 u32 fourcc = icd->current_fmt->host_fmt->fourcc;
1363 int ret;
1364
1365 /* If PCLK is used to latch data from the sensor, check sense */
1366 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1367 icd->sense = &sense;
1368
1369 ret = v4l2_subdev_call(sd, video, s_crop, a);
1370
1371 icd->sense = NULL;
1372
1373 if (ret < 0) {
1374 dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n",
1375 rect->width, rect->height, rect->left, rect->top);
1376 return ret;
1377 }
1378
1379 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1380 if (ret < 0)
1381 return ret;
1382
1383 if (pxa_camera_check_frame(mf.width, mf.height)) {
1384 /*
1385 * Camera cropping produced a frame beyond our capabilities.
1386 * FIXME: just extract a subframe, that we can process.
1387 */
1388 v4l_bound_align_image(&mf.width, 48, 2048, 1,
1389 &mf.height, 32, 2048, 0,
1390 fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1391 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1392 if (ret < 0)
1393 return ret;
1394
1395 if (pxa_camera_check_frame(mf.width, mf.height)) {
1396 dev_warn(icd->parent,
1397 "Inconsistent state. Use S_FMT to repair\n");
1398 return -EINVAL;
1399 }
1400 }
1401
1402 if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1403 if (sense.pixel_clock > sense.pixel_clock_max) {
1404 dev_err(dev,
1405 "pixel clock %lu set by the camera too high!",
1406 sense.pixel_clock);
1407 return -EIO;
1408 }
1409 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1410 }
1411
1412 icd->user_width = mf.width;
1413 icd->user_height = mf.height;
1414
1415 pxa_camera_setup_cicr(icd, cam->flags, fourcc);
1416
1417 return ret;
1418 }
1419
1420 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1421 struct v4l2_format *f)
1422 {
1423 struct device *dev = icd->parent;
1424 struct soc_camera_host *ici = to_soc_camera_host(dev);
1425 struct pxa_camera_dev *pcdev = ici->priv;
1426 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1427 const struct soc_camera_format_xlate *xlate = NULL;
1428 struct soc_camera_sense sense = {
1429 .master_clock = pcdev->mclk,
1430 .pixel_clock_max = pcdev->ciclk / 4,
1431 };
1432 struct v4l2_pix_format *pix = &f->fmt.pix;
1433 struct v4l2_mbus_framefmt mf;
1434 int ret;
1435
1436 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1437 if (!xlate) {
1438 dev_warn(dev, "Format %x not found\n", pix->pixelformat);
1439 return -EINVAL;
1440 }
1441
1442 /* If PCLK is used to latch data from the sensor, check sense */
1443 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1444 /* The caller holds a mutex. */
1445 icd->sense = &sense;
1446
1447 mf.width = pix->width;
1448 mf.height = pix->height;
1449 mf.field = pix->field;
1450 mf.colorspace = pix->colorspace;
1451 mf.code = xlate->code;
1452
1453 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1454
1455 if (mf.code != xlate->code)
1456 return -EINVAL;
1457
1458 icd->sense = NULL;
1459
1460 if (ret < 0) {
1461 dev_warn(dev, "Failed to configure for format %x\n",
1462 pix->pixelformat);
1463 } else if (pxa_camera_check_frame(mf.width, mf.height)) {
1464 dev_warn(dev,
1465 "Camera driver produced an unsupported frame %dx%d\n",
1466 mf.width, mf.height);
1467 ret = -EINVAL;
1468 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1469 if (sense.pixel_clock > sense.pixel_clock_max) {
1470 dev_err(dev,
1471 "pixel clock %lu set by the camera too high!",
1472 sense.pixel_clock);
1473 return -EIO;
1474 }
1475 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1476 }
1477
1478 if (ret < 0)
1479 return ret;
1480
1481 pix->width = mf.width;
1482 pix->height = mf.height;
1483 pix->field = mf.field;
1484 pix->colorspace = mf.colorspace;
1485 icd->current_fmt = xlate;
1486
1487 return ret;
1488 }
1489
1490 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1491 struct v4l2_format *f)
1492 {
1493 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1494 const struct soc_camera_format_xlate *xlate;
1495 struct v4l2_pix_format *pix = &f->fmt.pix;
1496 struct v4l2_mbus_framefmt mf;
1497 __u32 pixfmt = pix->pixelformat;
1498 int ret;
1499
1500 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1501 if (!xlate) {
1502 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1503 return -EINVAL;
1504 }
1505
1506 /*
1507 * Limit to pxa hardware capabilities. YUV422P planar format requires
1508 * images size to be a multiple of 16 bytes. If not, zeros will be
1509 * inserted between Y and U planes, and U and V planes, which violates
1510 * the YUV422P standard.
1511 */
1512 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1513 &pix->height, 32, 2048, 0,
1514 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1515
1516 /* limit to sensor capabilities */
1517 mf.width = pix->width;
1518 mf.height = pix->height;
1519 /* Only progressive video supported so far */
1520 mf.field = V4L2_FIELD_NONE;
1521 mf.colorspace = pix->colorspace;
1522 mf.code = xlate->code;
1523
1524 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1525 if (ret < 0)
1526 return ret;
1527
1528 pix->width = mf.width;
1529 pix->height = mf.height;
1530 pix->colorspace = mf.colorspace;
1531
1532 switch (mf.field) {
1533 case V4L2_FIELD_ANY:
1534 case V4L2_FIELD_NONE:
1535 pix->field = V4L2_FIELD_NONE;
1536 break;
1537 default:
1538 /* TODO: support interlaced at least in pass-through mode */
1539 dev_err(icd->parent, "Field type %d unsupported.\n",
1540 mf.field);
1541 return -EINVAL;
1542 }
1543
1544 return ret;
1545 }
1546
1547 static int pxa_camera_reqbufs(struct soc_camera_device *icd,
1548 struct v4l2_requestbuffers *p)
1549 {
1550 int i;
1551
1552 /*
1553 * This is for locking debugging only. I removed spinlocks and now I
1554 * check whether .prepare is ever called on a linked buffer, or whether
1555 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1556 * it hadn't triggered
1557 */
1558 for (i = 0; i < p->count; i++) {
1559 struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i],
1560 struct pxa_buffer, vb);
1561 buf->inwork = 0;
1562 INIT_LIST_HEAD(&buf->vb.queue);
1563 }
1564
1565 return 0;
1566 }
1567
1568 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1569 {
1570 struct soc_camera_device *icd = file->private_data;
1571 struct pxa_buffer *buf;
1572
1573 buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer,
1574 vb.stream);
1575
1576 poll_wait(file, &buf->vb.done, pt);
1577
1578 if (buf->vb.state == VIDEOBUF_DONE ||
1579 buf->vb.state == VIDEOBUF_ERROR)
1580 return POLLIN|POLLRDNORM;
1581
1582 return 0;
1583 }
1584
1585 static int pxa_camera_querycap(struct soc_camera_host *ici,
1586 struct v4l2_capability *cap)
1587 {
1588 /* cap->name is set by the firendly caller:-> */
1589 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1590 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1591
1592 return 0;
1593 }
1594
1595 static int pxa_camera_suspend(struct device *dev)
1596 {
1597 struct soc_camera_host *ici = to_soc_camera_host(dev);
1598 struct pxa_camera_dev *pcdev = ici->priv;
1599 int i = 0, ret = 0;
1600
1601 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1602 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1603 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1604 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1605 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1606
1607 if (pcdev->icd) {
1608 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->icd);
1609 ret = v4l2_subdev_call(sd, core, s_power, 0);
1610 if (ret == -ENOIOCTLCMD)
1611 ret = 0;
1612 }
1613
1614 return ret;
1615 }
1616
1617 static int pxa_camera_resume(struct device *dev)
1618 {
1619 struct soc_camera_host *ici = to_soc_camera_host(dev);
1620 struct pxa_camera_dev *pcdev = ici->priv;
1621 int i = 0, ret = 0;
1622
1623 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1624 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1625 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1626
1627 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1628 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1629 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1630 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1631 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1632
1633 if (pcdev->icd) {
1634 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->icd);
1635 ret = v4l2_subdev_call(sd, core, s_power, 1);
1636 if (ret == -ENOIOCTLCMD)
1637 ret = 0;
1638 }
1639
1640 /* Restart frame capture if active buffer exists */
1641 if (!ret && pcdev->active)
1642 pxa_camera_start_capture(pcdev);
1643
1644 return ret;
1645 }
1646
1647 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1648 .owner = THIS_MODULE,
1649 .add = pxa_camera_add_device,
1650 .remove = pxa_camera_remove_device,
1651 .set_crop = pxa_camera_set_crop,
1652 .get_formats = pxa_camera_get_formats,
1653 .put_formats = pxa_camera_put_formats,
1654 .set_fmt = pxa_camera_set_fmt,
1655 .try_fmt = pxa_camera_try_fmt,
1656 .init_videobuf = pxa_camera_init_videobuf,
1657 .reqbufs = pxa_camera_reqbufs,
1658 .poll = pxa_camera_poll,
1659 .querycap = pxa_camera_querycap,
1660 .set_bus_param = pxa_camera_set_bus_param,
1661 };
1662
1663 static int __devinit pxa_camera_probe(struct platform_device *pdev)
1664 {
1665 struct pxa_camera_dev *pcdev;
1666 struct resource *res;
1667 void __iomem *base;
1668 int irq;
1669 int err = 0;
1670
1671 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1672 irq = platform_get_irq(pdev, 0);
1673 if (!res || irq < 0) {
1674 err = -ENODEV;
1675 goto exit;
1676 }
1677
1678 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1679 if (!pcdev) {
1680 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1681 err = -ENOMEM;
1682 goto exit;
1683 }
1684
1685 pcdev->clk = clk_get(&pdev->dev, NULL);
1686 if (IS_ERR(pcdev->clk)) {
1687 err = PTR_ERR(pcdev->clk);
1688 goto exit_kfree;
1689 }
1690
1691 pcdev->res = res;
1692
1693 pcdev->pdata = pdev->dev.platform_data;
1694 pcdev->platform_flags = pcdev->pdata->flags;
1695 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1696 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1697 /*
1698 * Platform hasn't set available data widths. This is bad.
1699 * Warn and use a default.
1700 */
1701 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1702 "data widths, using default 10 bit\n");
1703 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1704 }
1705 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
1706 pcdev->width_flags = 1 << 7;
1707 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
1708 pcdev->width_flags |= 1 << 8;
1709 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
1710 pcdev->width_flags |= 1 << 9;
1711 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1712 if (!pcdev->mclk) {
1713 dev_warn(&pdev->dev,
1714 "mclk == 0! Please, fix your platform data. "
1715 "Using default 20MHz\n");
1716 pcdev->mclk = 20000000;
1717 }
1718
1719 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1720
1721 INIT_LIST_HEAD(&pcdev->capture);
1722 spin_lock_init(&pcdev->lock);
1723
1724 /*
1725 * Request the regions.
1726 */
1727 if (!request_mem_region(res->start, resource_size(res),
1728 PXA_CAM_DRV_NAME)) {
1729 err = -EBUSY;
1730 goto exit_clk;
1731 }
1732
1733 base = ioremap(res->start, resource_size(res));
1734 if (!base) {
1735 err = -ENOMEM;
1736 goto exit_release;
1737 }
1738 pcdev->irq = irq;
1739 pcdev->base = base;
1740
1741 /* request dma */
1742 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1743 pxa_camera_dma_irq_y, pcdev);
1744 if (err < 0) {
1745 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1746 goto exit_iounmap;
1747 }
1748 pcdev->dma_chans[0] = err;
1749 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1750
1751 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1752 pxa_camera_dma_irq_u, pcdev);
1753 if (err < 0) {
1754 dev_err(&pdev->dev, "Can't request DMA for U\n");
1755 goto exit_free_dma_y;
1756 }
1757 pcdev->dma_chans[1] = err;
1758 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1759
1760 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1761 pxa_camera_dma_irq_v, pcdev);
1762 if (err < 0) {
1763 dev_err(&pdev->dev, "Can't request DMA for V\n");
1764 goto exit_free_dma_u;
1765 }
1766 pcdev->dma_chans[2] = err;
1767 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1768
1769 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1770 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1771 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1772
1773 /* request irq */
1774 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1775 pcdev);
1776 if (err) {
1777 dev_err(&pdev->dev, "Camera interrupt register failed \n");
1778 goto exit_free_dma;
1779 }
1780
1781 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1782 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1783 pcdev->soc_host.priv = pcdev;
1784 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1785 pcdev->soc_host.nr = pdev->id;
1786
1787 err = soc_camera_host_register(&pcdev->soc_host);
1788 if (err)
1789 goto exit_free_irq;
1790
1791 return 0;
1792
1793 exit_free_irq:
1794 free_irq(pcdev->irq, pcdev);
1795 exit_free_dma:
1796 pxa_free_dma(pcdev->dma_chans[2]);
1797 exit_free_dma_u:
1798 pxa_free_dma(pcdev->dma_chans[1]);
1799 exit_free_dma_y:
1800 pxa_free_dma(pcdev->dma_chans[0]);
1801 exit_iounmap:
1802 iounmap(base);
1803 exit_release:
1804 release_mem_region(res->start, resource_size(res));
1805 exit_clk:
1806 clk_put(pcdev->clk);
1807 exit_kfree:
1808 kfree(pcdev);
1809 exit:
1810 return err;
1811 }
1812
1813 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1814 {
1815 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1816 struct pxa_camera_dev *pcdev = container_of(soc_host,
1817 struct pxa_camera_dev, soc_host);
1818 struct resource *res;
1819
1820 clk_put(pcdev->clk);
1821
1822 pxa_free_dma(pcdev->dma_chans[0]);
1823 pxa_free_dma(pcdev->dma_chans[1]);
1824 pxa_free_dma(pcdev->dma_chans[2]);
1825 free_irq(pcdev->irq, pcdev);
1826
1827 soc_camera_host_unregister(soc_host);
1828
1829 iounmap(pcdev->base);
1830
1831 res = pcdev->res;
1832 release_mem_region(res->start, resource_size(res));
1833
1834 kfree(pcdev);
1835
1836 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1837
1838 return 0;
1839 }
1840
1841 static struct dev_pm_ops pxa_camera_pm = {
1842 .suspend = pxa_camera_suspend,
1843 .resume = pxa_camera_resume,
1844 };
1845
1846 static struct platform_driver pxa_camera_driver = {
1847 .driver = {
1848 .name = PXA_CAM_DRV_NAME,
1849 .pm = &pxa_camera_pm,
1850 },
1851 .probe = pxa_camera_probe,
1852 .remove = __devexit_p(pxa_camera_remove),
1853 };
1854
1855 module_platform_driver(pxa_camera_driver);
1856
1857 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1858 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1859 MODULE_LICENSE("GPL");
1860 MODULE_VERSION(PXA_CAM_VERSION);
1861 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);