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[pohmelfs.git] / drivers / spi / spi-bfin5xx.c
blob3b83ff8b1e2b7ac60fb5494347fbc2a189b6dc14
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
25
26 #include <asm/dma.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
30
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
35
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
39
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
44
45 struct bfin_spi_master_data;
46
47 struct bfin_spi_transfer_ops {
48 void (*write) (struct bfin_spi_master_data *);
49 void (*read) (struct bfin_spi_master_data *);
50 void (*duplex) (struct bfin_spi_master_data *);
51 };
52
53 struct bfin_spi_master_data {
54 /* Driver model hookup */
55 struct platform_device *pdev;
56
57 /* SPI framework hookup */
58 struct spi_master *master;
59
60 /* Regs base of SPI controller */
61 struct bfin_spi_regs __iomem *regs;
62
63 /* Pin request list */
64 u16 *pin_req;
65
66 /* BFIN hookup */
67 struct bfin5xx_spi_master *master_info;
68
69 /* Driver message queue */
70 struct workqueue_struct *workqueue;
71 struct work_struct pump_messages;
72 spinlock_t lock;
73 struct list_head queue;
74 int busy;
75 bool running;
76
77 /* Message Transfer pump */
78 struct tasklet_struct pump_transfers;
79
80 /* Current message transfer state info */
81 struct spi_message *cur_msg;
82 struct spi_transfer *cur_transfer;
83 struct bfin_spi_slave_data *cur_chip;
84 size_t len_in_bytes;
85 size_t len;
86 void *tx;
87 void *tx_end;
88 void *rx;
89 void *rx_end;
90
91 /* DMA stuffs */
92 int dma_channel;
93 int dma_mapped;
94 int dma_requested;
95 dma_addr_t rx_dma;
96 dma_addr_t tx_dma;
97
98 int irq_requested;
99 int spi_irq;
100
101 size_t rx_map_len;
102 size_t tx_map_len;
103 u8 n_bytes;
104 u16 ctrl_reg;
105 u16 flag_reg;
106
107 int cs_change;
108 const struct bfin_spi_transfer_ops *ops;
109 };
110
111 struct bfin_spi_slave_data {
112 u16 ctl_reg;
113 u16 baud;
114 u16 flag;
115
116 u8 chip_select_num;
117 u8 enable_dma;
118 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
119 u32 cs_gpio;
120 u16 idle_tx_val;
121 u8 pio_interrupt; /* use spi data irq */
122 const struct bfin_spi_transfer_ops *ops;
123 };
124
125 static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
126 {
127 bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE);
128 }
129
130 static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
131 {
132 bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE);
133 }
134
135 /* Caculate the SPI_BAUD register value based on input HZ */
136 static u16 hz_to_spi_baud(u32 speed_hz)
137 {
138 u_long sclk = get_sclk();
139 u16 spi_baud = (sclk / (2 * speed_hz));
140
141 if ((sclk % (2 * speed_hz)) > 0)
142 spi_baud++;
143
144 if (spi_baud < MIN_SPI_BAUD_VAL)
145 spi_baud = MIN_SPI_BAUD_VAL;
146
147 return spi_baud;
148 }
149
150 static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
151 {
152 unsigned long limit = loops_per_jiffy << 1;
153
154 /* wait for stop and clear stat */
155 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit)
156 cpu_relax();
157
158 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
159
160 return limit;
161 }
162
163 /* Chip select operation functions for cs_change flag */
164 static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
165 {
166 if (likely(chip->chip_select_num < MAX_CTRL_CS))
167 bfin_write_and(&drv_data->regs->flg, ~chip->flag);
168 else
169 gpio_set_value(chip->cs_gpio, 0);
170 }
171
172 static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
173 struct bfin_spi_slave_data *chip)
174 {
175 if (likely(chip->chip_select_num < MAX_CTRL_CS))
176 bfin_write_or(&drv_data->regs->flg, chip->flag);
177 else
178 gpio_set_value(chip->cs_gpio, 1);
179
180 /* Move delay here for consistency */
181 if (chip->cs_chg_udelay)
182 udelay(chip->cs_chg_udelay);
183 }
184
185 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
186 static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
187 struct bfin_spi_slave_data *chip)
188 {
189 if (chip->chip_select_num < MAX_CTRL_CS)
190 bfin_write_or(&drv_data->regs->flg, chip->flag >> 8);
191 }
192
193 static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
194 struct bfin_spi_slave_data *chip)
195 {
196 if (chip->chip_select_num < MAX_CTRL_CS)
197 bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8));
198 }
199
200 /* stop controller and re-config current chip*/
201 static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
202 {
203 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
204
205 /* Clear status and disable clock */
206 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
207 bfin_spi_disable(drv_data);
208 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
209
210 SSYNC();
211
212 /* Load the registers */
213 bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
214 bfin_write(&drv_data->regs->baud, chip->baud);
215
216 bfin_spi_enable(drv_data);
217 bfin_spi_cs_active(drv_data, chip);
218 }
219
220 /* used to kick off transfer in rx mode and read unwanted RX data */
221 static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
222 {
223 (void) bfin_read(&drv_data->regs->rdbr);
224 }
225
226 static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
227 {
228 /* clear RXS (we check for RXS inside the loop) */
229 bfin_spi_dummy_read(drv_data);
230
231 while (drv_data->tx < drv_data->tx_end) {
232 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
233 /* wait until transfer finished.
234 checking SPIF or TXS may not guarantee transfer completion */
235 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
236 cpu_relax();
237 /* discard RX data and clear RXS */
238 bfin_spi_dummy_read(drv_data);
239 }
240 }
241
242 static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
243 {
244 u16 tx_val = drv_data->cur_chip->idle_tx_val;
245
246 /* discard old RX data and clear RXS */
247 bfin_spi_dummy_read(drv_data);
248
249 while (drv_data->rx < drv_data->rx_end) {
250 bfin_write(&drv_data->regs->tdbr, tx_val);
251 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
252 cpu_relax();
253 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
254 }
255 }
256
257 static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
258 {
259 /* discard old RX data and clear RXS */
260 bfin_spi_dummy_read(drv_data);
261
262 while (drv_data->rx < drv_data->rx_end) {
263 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
264 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
265 cpu_relax();
266 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
267 }
268 }
269
270 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
271 .write = bfin_spi_u8_writer,
272 .read = bfin_spi_u8_reader,
273 .duplex = bfin_spi_u8_duplex,
274 };
275
276 static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
277 {
278 /* clear RXS (we check for RXS inside the loop) */
279 bfin_spi_dummy_read(drv_data);
280
281 while (drv_data->tx < drv_data->tx_end) {
282 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
283 drv_data->tx += 2;
284 /* wait until transfer finished.
285 checking SPIF or TXS may not guarantee transfer completion */
286 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
287 cpu_relax();
288 /* discard RX data and clear RXS */
289 bfin_spi_dummy_read(drv_data);
290 }
291 }
292
293 static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
294 {
295 u16 tx_val = drv_data->cur_chip->idle_tx_val;
296
297 /* discard old RX data and clear RXS */
298 bfin_spi_dummy_read(drv_data);
299
300 while (drv_data->rx < drv_data->rx_end) {
301 bfin_write(&drv_data->regs->tdbr, tx_val);
302 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
303 cpu_relax();
304 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
305 drv_data->rx += 2;
306 }
307 }
308
309 static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
310 {
311 /* discard old RX data and clear RXS */
312 bfin_spi_dummy_read(drv_data);
313
314 while (drv_data->rx < drv_data->rx_end) {
315 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
316 drv_data->tx += 2;
317 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
318 cpu_relax();
319 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
320 drv_data->rx += 2;
321 }
322 }
323
324 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
325 .write = bfin_spi_u16_writer,
326 .read = bfin_spi_u16_reader,
327 .duplex = bfin_spi_u16_duplex,
328 };
329
330 /* test if there is more transfer to be done */
331 static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
332 {
333 struct spi_message *msg = drv_data->cur_msg;
334 struct spi_transfer *trans = drv_data->cur_transfer;
335
336 /* Move to next transfer */
337 if (trans->transfer_list.next != &msg->transfers) {
338 drv_data->cur_transfer =
339 list_entry(trans->transfer_list.next,
340 struct spi_transfer, transfer_list);
341 return RUNNING_STATE;
342 } else
343 return DONE_STATE;
344 }
345
346 /*
347 * caller already set message->status;
348 * dma and pio irqs are blocked give finished message back
349 */
350 static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
351 {
352 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
353 struct spi_transfer *last_transfer;
354 unsigned long flags;
355 struct spi_message *msg;
356
357 spin_lock_irqsave(&drv_data->lock, flags);
358 msg = drv_data->cur_msg;
359 drv_data->cur_msg = NULL;
360 drv_data->cur_transfer = NULL;
361 drv_data->cur_chip = NULL;
362 queue_work(drv_data->workqueue, &drv_data->pump_messages);
363 spin_unlock_irqrestore(&drv_data->lock, flags);
364
365 last_transfer = list_entry(msg->transfers.prev,
366 struct spi_transfer, transfer_list);
367
368 msg->state = NULL;
369
370 if (!drv_data->cs_change)
371 bfin_spi_cs_deactive(drv_data, chip);
372
373 /* Not stop spi in autobuffer mode */
374 if (drv_data->tx_dma != 0xFFFF)
375 bfin_spi_disable(drv_data);
376
377 if (msg->complete)
378 msg->complete(msg->context);
379 }
380
381 /* spi data irq handler */
382 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
383 {
384 struct bfin_spi_master_data *drv_data = dev_id;
385 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
386 struct spi_message *msg = drv_data->cur_msg;
387 int n_bytes = drv_data->n_bytes;
388 int loop = 0;
389
390 /* wait until transfer finished. */
391 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
392 cpu_relax();
393
394 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
395 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
396 /* last read */
397 if (drv_data->rx) {
398 dev_dbg(&drv_data->pdev->dev, "last read\n");
399 if (n_bytes % 2) {
400 u16 *buf = (u16 *)drv_data->rx;
401 for (loop = 0; loop < n_bytes / 2; loop++)
402 *buf++ = bfin_read(&drv_data->regs->rdbr);
403 } else {
404 u8 *buf = (u8 *)drv_data->rx;
405 for (loop = 0; loop < n_bytes; loop++)
406 *buf++ = bfin_read(&drv_data->regs->rdbr);
407 }
408 drv_data->rx += n_bytes;
409 }
410
411 msg->actual_length += drv_data->len_in_bytes;
412 if (drv_data->cs_change)
413 bfin_spi_cs_deactive(drv_data, chip);
414 /* Move to next transfer */
415 msg->state = bfin_spi_next_transfer(drv_data);
416
417 disable_irq_nosync(drv_data->spi_irq);
418
419 /* Schedule transfer tasklet */
420 tasklet_schedule(&drv_data->pump_transfers);
421 return IRQ_HANDLED;
422 }
423
424 if (drv_data->rx && drv_data->tx) {
425 /* duplex */
426 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
427 if (n_bytes % 2) {
428 u16 *buf = (u16 *)drv_data->rx;
429 u16 *buf2 = (u16 *)drv_data->tx;
430 for (loop = 0; loop < n_bytes / 2; loop++) {
431 *buf++ = bfin_read(&drv_data->regs->rdbr);
432 bfin_write(&drv_data->regs->tdbr, *buf2++);
433 }
434 } else {
435 u8 *buf = (u8 *)drv_data->rx;
436 u8 *buf2 = (u8 *)drv_data->tx;
437 for (loop = 0; loop < n_bytes; loop++) {
438 *buf++ = bfin_read(&drv_data->regs->rdbr);
439 bfin_write(&drv_data->regs->tdbr, *buf2++);
440 }
441 }
442 } else if (drv_data->rx) {
443 /* read */
444 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
445 if (n_bytes % 2) {
446 u16 *buf = (u16 *)drv_data->rx;
447 for (loop = 0; loop < n_bytes / 2; loop++) {
448 *buf++ = bfin_read(&drv_data->regs->rdbr);
449 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
450 }
451 } else {
452 u8 *buf = (u8 *)drv_data->rx;
453 for (loop = 0; loop < n_bytes; loop++) {
454 *buf++ = bfin_read(&drv_data->regs->rdbr);
455 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
456 }
457 }
458 } else if (drv_data->tx) {
459 /* write */
460 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
461 if (n_bytes % 2) {
462 u16 *buf = (u16 *)drv_data->tx;
463 for (loop = 0; loop < n_bytes / 2; loop++) {
464 bfin_read(&drv_data->regs->rdbr);
465 bfin_write(&drv_data->regs->tdbr, *buf++);
466 }
467 } else {
468 u8 *buf = (u8 *)drv_data->tx;
469 for (loop = 0; loop < n_bytes; loop++) {
470 bfin_read(&drv_data->regs->rdbr);
471 bfin_write(&drv_data->regs->tdbr, *buf++);
472 }
473 }
474 }
475
476 if (drv_data->tx)
477 drv_data->tx += n_bytes;
478 if (drv_data->rx)
479 drv_data->rx += n_bytes;
480
481 return IRQ_HANDLED;
482 }
483
484 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
485 {
486 struct bfin_spi_master_data *drv_data = dev_id;
487 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
488 struct spi_message *msg = drv_data->cur_msg;
489 unsigned long timeout;
490 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
491 u16 spistat = bfin_read(&drv_data->regs->stat);
492
493 dev_dbg(&drv_data->pdev->dev,
494 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
495 dmastat, spistat);
496
497 if (drv_data->rx != NULL) {
498 u16 cr = bfin_read(&drv_data->regs->ctl);
499 /* discard old RX data and clear RXS */
500 bfin_spi_dummy_read(drv_data);
501 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
502 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */
503 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */
504 }
505
506 clear_dma_irqstat(drv_data->dma_channel);
507
508 /*
509 * wait for the last transaction shifted out. HRM states:
510 * at this point there may still be data in the SPI DMA FIFO waiting
511 * to be transmitted ... software needs to poll TXS in the SPI_STAT
512 * register until it goes low for 2 successive reads
513 */
514 if (drv_data->tx != NULL) {
515 while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) ||
516 (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS))
517 cpu_relax();
518 }
519
520 dev_dbg(&drv_data->pdev->dev,
521 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
522 dmastat, bfin_read(&drv_data->regs->stat));
523
524 timeout = jiffies + HZ;
525 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
526 if (!time_before(jiffies, timeout)) {
527 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
528 break;
529 } else
530 cpu_relax();
531
532 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
533 msg->state = ERROR_STATE;
534 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
535 } else {
536 msg->actual_length += drv_data->len_in_bytes;
537
538 if (drv_data->cs_change)
539 bfin_spi_cs_deactive(drv_data, chip);
540
541 /* Move to next transfer */
542 msg->state = bfin_spi_next_transfer(drv_data);
543 }
544
545 /* Schedule transfer tasklet */
546 tasklet_schedule(&drv_data->pump_transfers);
547
548 /* free the irq handler before next transfer */
549 dev_dbg(&drv_data->pdev->dev,
550 "disable dma channel irq%d\n",
551 drv_data->dma_channel);
552 dma_disable_irq_nosync(drv_data->dma_channel);
553
554 return IRQ_HANDLED;
555 }
556
557 static void bfin_spi_pump_transfers(unsigned long data)
558 {
559 struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
560 struct spi_message *message = NULL;
561 struct spi_transfer *transfer = NULL;
562 struct spi_transfer *previous = NULL;
563 struct bfin_spi_slave_data *chip = NULL;
564 unsigned int bits_per_word;
565 u16 cr, cr_width, dma_width, dma_config;
566 u32 tranf_success = 1;
567 u8 full_duplex = 0;
568
569 /* Get current state information */
570 message = drv_data->cur_msg;
571 transfer = drv_data->cur_transfer;
572 chip = drv_data->cur_chip;
573
574 /*
575 * if msg is error or done, report it back using complete() callback
576 */
577
578 /* Handle for abort */
579 if (message->state == ERROR_STATE) {
580 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
581 message->status = -EIO;
582 bfin_spi_giveback(drv_data);
583 return;
584 }
585
586 /* Handle end of message */
587 if (message->state == DONE_STATE) {
588 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
589 message->status = 0;
590 bfin_spi_giveback(drv_data);
591 return;
592 }
593
594 /* Delay if requested at end of transfer */
595 if (message->state == RUNNING_STATE) {
596 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
597 previous = list_entry(transfer->transfer_list.prev,
598 struct spi_transfer, transfer_list);
599 if (previous->delay_usecs)
600 udelay(previous->delay_usecs);
601 }
602
603 /* Flush any existing transfers that may be sitting in the hardware */
604 if (bfin_spi_flush(drv_data) == 0) {
605 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
606 message->status = -EIO;
607 bfin_spi_giveback(drv_data);
608 return;
609 }
610
611 if (transfer->len == 0) {
612 /* Move to next transfer of this msg */
613 message->state = bfin_spi_next_transfer(drv_data);
614 /* Schedule next transfer tasklet */
615 tasklet_schedule(&drv_data->pump_transfers);
616 return;
617 }
618
619 if (transfer->tx_buf != NULL) {
620 drv_data->tx = (void *)transfer->tx_buf;
621 drv_data->tx_end = drv_data->tx + transfer->len;
622 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
623 transfer->tx_buf, drv_data->tx_end);
624 } else {
625 drv_data->tx = NULL;
626 }
627
628 if (transfer->rx_buf != NULL) {
629 full_duplex = transfer->tx_buf != NULL;
630 drv_data->rx = transfer->rx_buf;
631 drv_data->rx_end = drv_data->rx + transfer->len;
632 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
633 transfer->rx_buf, drv_data->rx_end);
634 } else {
635 drv_data->rx = NULL;
636 }
637
638 drv_data->rx_dma = transfer->rx_dma;
639 drv_data->tx_dma = transfer->tx_dma;
640 drv_data->len_in_bytes = transfer->len;
641 drv_data->cs_change = transfer->cs_change;
642
643 /* Bits per word setup */
644 bits_per_word = transfer->bits_per_word ? :
645 message->spi->bits_per_word ? : 8;
646 if (bits_per_word % 16 == 0) {
647 drv_data->n_bytes = bits_per_word/8;
648 drv_data->len = (transfer->len) >> 1;
649 cr_width = BIT_CTL_WORDSIZE;
650 drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
651 } else if (bits_per_word % 8 == 0) {
652 drv_data->n_bytes = bits_per_word/8;
653 drv_data->len = transfer->len;
654 cr_width = 0;
655 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
656 } else {
657 dev_err(&drv_data->pdev->dev, "transfer: unsupported bits_per_word\n");
658 message->status = -EINVAL;
659 bfin_spi_giveback(drv_data);
660 return;
661 }
662 cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
663 cr |= cr_width;
664 bfin_write(&drv_data->regs->ctl, cr);
665
666 dev_dbg(&drv_data->pdev->dev,
667 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
668 drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
669
670 message->state = RUNNING_STATE;
671 dma_config = 0;
672
673 /* Speed setup (surely valid because already checked) */
674 if (transfer->speed_hz)
675 bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));
676 else
677 bfin_write(&drv_data->regs->baud, chip->baud);
678
679 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
680 bfin_spi_cs_active(drv_data, chip);
681
682 dev_dbg(&drv_data->pdev->dev,
683 "now pumping a transfer: width is %d, len is %d\n",
684 cr_width, transfer->len);
685
686 /*
687 * Try to map dma buffer and do a dma transfer. If successful use,
688 * different way to r/w according to the enable_dma settings and if
689 * we are not doing a full duplex transfer (since the hardware does
690 * not support full duplex DMA transfers).
691 */
692 if (!full_duplex && drv_data->cur_chip->enable_dma
693 && drv_data->len > 6) {
694
695 unsigned long dma_start_addr, flags;
696
697 disable_dma(drv_data->dma_channel);
698 clear_dma_irqstat(drv_data->dma_channel);
699
700 /* config dma channel */
701 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
702 set_dma_x_count(drv_data->dma_channel, drv_data->len);
703 if (cr_width == BIT_CTL_WORDSIZE) {
704 set_dma_x_modify(drv_data->dma_channel, 2);
705 dma_width = WDSIZE_16;
706 } else {
707 set_dma_x_modify(drv_data->dma_channel, 1);
708 dma_width = WDSIZE_8;
709 }
710
711 /* poll for SPI completion before start */
712 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
713 cpu_relax();
714
715 /* dirty hack for autobuffer DMA mode */
716 if (drv_data->tx_dma == 0xFFFF) {
717 dev_dbg(&drv_data->pdev->dev,
718 "doing autobuffer DMA out.\n");
719
720 /* no irq in autobuffer mode */
721 dma_config =
722 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
723 set_dma_config(drv_data->dma_channel, dma_config);
724 set_dma_start_addr(drv_data->dma_channel,
725 (unsigned long)drv_data->tx);
726 enable_dma(drv_data->dma_channel);
727
728 /* start SPI transfer */
729 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);
730
731 /* just return here, there can only be one transfer
732 * in this mode
733 */
734 message->status = 0;
735 bfin_spi_giveback(drv_data);
736 return;
737 }
738
739 /* In dma mode, rx or tx must be NULL in one transfer */
740 dma_config = (RESTART | dma_width | DI_EN);
741 if (drv_data->rx != NULL) {
742 /* set transfer mode, and enable SPI */
743 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
744 drv_data->rx, drv_data->len_in_bytes);
745
746 /* invalidate caches, if needed */
747 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
748 invalidate_dcache_range((unsigned long) drv_data->rx,
749 (unsigned long) (drv_data->rx +
750 drv_data->len_in_bytes));
751
752 dma_config |= WNR;
753 dma_start_addr = (unsigned long)drv_data->rx;
754 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
755
756 } else if (drv_data->tx != NULL) {
757 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
758
759 /* flush caches, if needed */
760 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
761 flush_dcache_range((unsigned long) drv_data->tx,
762 (unsigned long) (drv_data->tx +
763 drv_data->len_in_bytes));
764
765 dma_start_addr = (unsigned long)drv_data->tx;
766 cr |= BIT_CTL_TIMOD_DMA_TX;
767
768 } else
769 BUG();
770
771 /* oh man, here there be monsters ... and i dont mean the
772 * fluffy cute ones from pixar, i mean the kind that'll eat
773 * your data, kick your dog, and love it all. do *not* try
774 * and change these lines unless you (1) heavily test DMA
775 * with SPI flashes on a loaded system (e.g. ping floods),
776 * (2) know just how broken the DMA engine interaction with
777 * the SPI peripheral is, and (3) have someone else to blame
778 * when you screw it all up anyways.
779 */
780 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
781 set_dma_config(drv_data->dma_channel, dma_config);
782 local_irq_save(flags);
783 SSYNC();
784 bfin_write(&drv_data->regs->ctl, cr);
785 enable_dma(drv_data->dma_channel);
786 dma_enable_irq(drv_data->dma_channel);
787 local_irq_restore(flags);
788
789 return;
790 }
791
792 /*
793 * We always use SPI_WRITE mode (transfer starts with TDBR write).
794 * SPI_READ mode (transfer starts with RDBR read) seems to have
795 * problems with setting up the output value in TDBR prior to the
796 * start of the transfer.
797 */
798 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);
799
800 if (chip->pio_interrupt) {
801 /* SPI irq should have been disabled by now */
802
803 /* discard old RX data and clear RXS */
804 bfin_spi_dummy_read(drv_data);
805
806 /* start transfer */
807 if (drv_data->tx == NULL)
808 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
809 else {
810 int loop;
811 if (bits_per_word % 16 == 0) {
812 u16 *buf = (u16 *)drv_data->tx;
813 for (loop = 0; loop < bits_per_word / 16;
814 loop++) {
815 bfin_write(&drv_data->regs->tdbr, *buf++);
816 }
817 } else if (bits_per_word % 8 == 0) {
818 u8 *buf = (u8 *)drv_data->tx;
819 for (loop = 0; loop < bits_per_word / 8; loop++)
820 bfin_write(&drv_data->regs->tdbr, *buf++);
821 }
822
823 drv_data->tx += drv_data->n_bytes;
824 }
825
826 /* once TDBR is empty, interrupt is triggered */
827 enable_irq(drv_data->spi_irq);
828 return;
829 }
830
831 /* IO mode */
832 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
833
834 if (full_duplex) {
835 /* full duplex mode */
836 BUG_ON((drv_data->tx_end - drv_data->tx) !=
837 (drv_data->rx_end - drv_data->rx));
838 dev_dbg(&drv_data->pdev->dev,
839 "IO duplex: cr is 0x%x\n", cr);
840
841 drv_data->ops->duplex(drv_data);
842
843 if (drv_data->tx != drv_data->tx_end)
844 tranf_success = 0;
845 } else if (drv_data->tx != NULL) {
846 /* write only half duplex */
847 dev_dbg(&drv_data->pdev->dev,
848 "IO write: cr is 0x%x\n", cr);
849
850 drv_data->ops->write(drv_data);
851
852 if (drv_data->tx != drv_data->tx_end)
853 tranf_success = 0;
854 } else if (drv_data->rx != NULL) {
855 /* read only half duplex */
856 dev_dbg(&drv_data->pdev->dev,
857 "IO read: cr is 0x%x\n", cr);
858
859 drv_data->ops->read(drv_data);
860 if (drv_data->rx != drv_data->rx_end)
861 tranf_success = 0;
862 }
863
864 if (!tranf_success) {
865 dev_dbg(&drv_data->pdev->dev,
866 "IO write error!\n");
867 message->state = ERROR_STATE;
868 } else {
869 /* Update total byte transferred */
870 message->actual_length += drv_data->len_in_bytes;
871 /* Move to next transfer of this msg */
872 message->state = bfin_spi_next_transfer(drv_data);
873 if (drv_data->cs_change)
874 bfin_spi_cs_deactive(drv_data, chip);
875 }
876
877 /* Schedule next transfer tasklet */
878 tasklet_schedule(&drv_data->pump_transfers);
879 }
880
881 /* pop a msg from queue and kick off real transfer */
882 static void bfin_spi_pump_messages(struct work_struct *work)
883 {
884 struct bfin_spi_master_data *drv_data;
885 unsigned long flags;
886
887 drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
888
889 /* Lock queue and check for queue work */
890 spin_lock_irqsave(&drv_data->lock, flags);
891 if (list_empty(&drv_data->queue) || !drv_data->running) {
892 /* pumper kicked off but no work to do */
893 drv_data->busy = 0;
894 spin_unlock_irqrestore(&drv_data->lock, flags);
895 return;
896 }
897
898 /* Make sure we are not already running a message */
899 if (drv_data->cur_msg) {
900 spin_unlock_irqrestore(&drv_data->lock, flags);
901 return;
902 }
903
904 /* Extract head of queue */
905 drv_data->cur_msg = list_entry(drv_data->queue.next,
906 struct spi_message, queue);
907
908 /* Setup the SSP using the per chip configuration */
909 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
910 bfin_spi_restore_state(drv_data);
911
912 list_del_init(&drv_data->cur_msg->queue);
913
914 /* Initial message state */
915 drv_data->cur_msg->state = START_STATE;
916 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
917 struct spi_transfer, transfer_list);
918
919 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
920 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
921 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
922 drv_data->cur_chip->ctl_reg);
923
924 dev_dbg(&drv_data->pdev->dev,
925 "the first transfer len is %d\n",
926 drv_data->cur_transfer->len);
927
928 /* Mark as busy and launch transfers */
929 tasklet_schedule(&drv_data->pump_transfers);
930
931 drv_data->busy = 1;
932 spin_unlock_irqrestore(&drv_data->lock, flags);
933 }
934
935 /*
936 * got a msg to transfer, queue it in drv_data->queue.
937 * And kick off message pumper
938 */
939 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
940 {
941 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
942 unsigned long flags;
943
944 spin_lock_irqsave(&drv_data->lock, flags);
945
946 if (!drv_data->running) {
947 spin_unlock_irqrestore(&drv_data->lock, flags);
948 return -ESHUTDOWN;
949 }
950
951 msg->actual_length = 0;
952 msg->status = -EINPROGRESS;
953 msg->state = START_STATE;
954
955 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
956 list_add_tail(&msg->queue, &drv_data->queue);
957
958 if (drv_data->running && !drv_data->busy)
959 queue_work(drv_data->workqueue, &drv_data->pump_messages);
960
961 spin_unlock_irqrestore(&drv_data->lock, flags);
962
963 return 0;
964 }
965
966 #define MAX_SPI_SSEL 7
967
968 static const u16 ssel[][MAX_SPI_SSEL] = {
969 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
970 P_SPI0_SSEL4, P_SPI0_SSEL5,
971 P_SPI0_SSEL6, P_SPI0_SSEL7},
972
973 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
974 P_SPI1_SSEL4, P_SPI1_SSEL5,
975 P_SPI1_SSEL6, P_SPI1_SSEL7},
976
977 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
978 P_SPI2_SSEL4, P_SPI2_SSEL5,
979 P_SPI2_SSEL6, P_SPI2_SSEL7},
980 };
981
982 /* setup for devices (may be called multiple times -- not just first setup) */
983 static int bfin_spi_setup(struct spi_device *spi)
984 {
985 struct bfin5xx_spi_chip *chip_info;
986 struct bfin_spi_slave_data *chip = NULL;
987 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
988 u16 bfin_ctl_reg;
989 int ret = -EINVAL;
990
991 /* Only alloc (or use chip_info) on first setup */
992 chip_info = NULL;
993 chip = spi_get_ctldata(spi);
994 if (chip == NULL) {
995 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
996 if (!chip) {
997 dev_err(&spi->dev, "cannot allocate chip data\n");
998 ret = -ENOMEM;
999 goto error;
1000 }
1001
1002 chip->enable_dma = 0;
1003 chip_info = spi->controller_data;
1004 }
1005
1006 /* Let people set non-standard bits directly */
1007 bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
1008 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
1009
1010 /* chip_info isn't always needed */
1011 if (chip_info) {
1012 /* Make sure people stop trying to set fields via ctl_reg
1013 * when they should actually be using common SPI framework.
1014 * Currently we let through: WOM EMISO PSSE GM SZ.
1015 * Not sure if a user actually needs/uses any of these,
1016 * but let's assume (for now) they do.
1017 */
1018 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1019 dev_err(&spi->dev, "do not set bits in ctl_reg "
1020 "that the SPI framework manages\n");
1021 goto error;
1022 }
1023 chip->enable_dma = chip_info->enable_dma != 0
1024 && drv_data->master_info->enable_dma;
1025 chip->ctl_reg = chip_info->ctl_reg;
1026 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1027 chip->idle_tx_val = chip_info->idle_tx_val;
1028 chip->pio_interrupt = chip_info->pio_interrupt;
1029 spi->bits_per_word = chip_info->bits_per_word;
1030 } else {
1031 /* force a default base state */
1032 chip->ctl_reg &= bfin_ctl_reg;
1033 }
1034
1035 if (spi->bits_per_word % 8) {
1036 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1037 spi->bits_per_word);
1038 goto error;
1039 }
1040
1041 /* translate common spi framework into our register */
1042 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1043 dev_err(&spi->dev, "unsupported spi modes detected\n");
1044 goto error;
1045 }
1046 if (spi->mode & SPI_CPOL)
1047 chip->ctl_reg |= BIT_CTL_CPOL;
1048 if (spi->mode & SPI_CPHA)
1049 chip->ctl_reg |= BIT_CTL_CPHA;
1050 if (spi->mode & SPI_LSB_FIRST)
1051 chip->ctl_reg |= BIT_CTL_LSBF;
1052 /* we dont support running in slave mode (yet?) */
1053 chip->ctl_reg |= BIT_CTL_MASTER;
1054
1055 /*
1056 * Notice: for blackfin, the speed_hz is the value of register
1057 * SPI_BAUD, not the real baudrate
1058 */
1059 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1060 chip->chip_select_num = spi->chip_select;
1061 if (chip->chip_select_num < MAX_CTRL_CS) {
1062 if (!(spi->mode & SPI_CPHA))
1063 dev_warn(&spi->dev, "Warning: SPI CPHA not set:"
1064 " Slave Select not under software control!\n"
1065 " See Documentation/blackfin/bfin-spi-notes.txt");
1066
1067 chip->flag = (1 << spi->chip_select) << 8;
1068 } else
1069 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1070
1071 if (chip->enable_dma && chip->pio_interrupt) {
1072 dev_err(&spi->dev, "enable_dma is set, "
1073 "do not set pio_interrupt\n");
1074 goto error;
1075 }
1076 /*
1077 * if any one SPI chip is registered and wants DMA, request the
1078 * DMA channel for it
1079 */
1080 if (chip->enable_dma && !drv_data->dma_requested) {
1081 /* register dma irq handler */
1082 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1083 if (ret) {
1084 dev_err(&spi->dev,
1085 "Unable to request BlackFin SPI DMA channel\n");
1086 goto error;
1087 }
1088 drv_data->dma_requested = 1;
1089
1090 ret = set_dma_callback(drv_data->dma_channel,
1091 bfin_spi_dma_irq_handler, drv_data);
1092 if (ret) {
1093 dev_err(&spi->dev, "Unable to set dma callback\n");
1094 goto error;
1095 }
1096 dma_disable_irq(drv_data->dma_channel);
1097 }
1098
1099 if (chip->pio_interrupt && !drv_data->irq_requested) {
1100 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1101 0, "BFIN_SPI", drv_data);
1102 if (ret) {
1103 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1104 goto error;
1105 }
1106 drv_data->irq_requested = 1;
1107 /* we use write mode, spi irq has to be disabled here */
1108 disable_irq(drv_data->spi_irq);
1109 }
1110
1111 if (chip->chip_select_num >= MAX_CTRL_CS) {
1112 /* Only request on first setup */
1113 if (spi_get_ctldata(spi) == NULL) {
1114 ret = gpio_request(chip->cs_gpio, spi->modalias);
1115 if (ret) {
1116 dev_err(&spi->dev, "gpio_request() error\n");
1117 goto pin_error;
1118 }
1119 gpio_direction_output(chip->cs_gpio, 1);
1120 }
1121 }
1122
1123 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1124 spi->modalias, spi->bits_per_word, chip->enable_dma);
1125 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1126 chip->ctl_reg, chip->flag);
1127
1128 spi_set_ctldata(spi, chip);
1129
1130 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1131 if (chip->chip_select_num < MAX_CTRL_CS) {
1132 ret = peripheral_request(ssel[spi->master->bus_num]
1133 [chip->chip_select_num-1], spi->modalias);
1134 if (ret) {
1135 dev_err(&spi->dev, "peripheral_request() error\n");
1136 goto pin_error;
1137 }
1138 }
1139
1140 bfin_spi_cs_enable(drv_data, chip);
1141 bfin_spi_cs_deactive(drv_data, chip);
1142
1143 return 0;
1144
1145 pin_error:
1146 if (chip->chip_select_num >= MAX_CTRL_CS)
1147 gpio_free(chip->cs_gpio);
1148 else
1149 peripheral_free(ssel[spi->master->bus_num]
1150 [chip->chip_select_num - 1]);
1151 error:
1152 if (chip) {
1153 if (drv_data->dma_requested)
1154 free_dma(drv_data->dma_channel);
1155 drv_data->dma_requested = 0;
1156
1157 kfree(chip);
1158 /* prevent free 'chip' twice */
1159 spi_set_ctldata(spi, NULL);
1160 }
1161
1162 return ret;
1163 }
1164
1165 /*
1166 * callback for spi framework.
1167 * clean driver specific data
1168 */
1169 static void bfin_spi_cleanup(struct spi_device *spi)
1170 {
1171 struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1172 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1173
1174 if (!chip)
1175 return;
1176
1177 if (chip->chip_select_num < MAX_CTRL_CS) {
1178 peripheral_free(ssel[spi->master->bus_num]
1179 [chip->chip_select_num-1]);
1180 bfin_spi_cs_disable(drv_data, chip);
1181 } else
1182 gpio_free(chip->cs_gpio);
1183
1184 kfree(chip);
1185 /* prevent free 'chip' twice */
1186 spi_set_ctldata(spi, NULL);
1187 }
1188
1189 static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
1190 {
1191 INIT_LIST_HEAD(&drv_data->queue);
1192 spin_lock_init(&drv_data->lock);
1193
1194 drv_data->running = false;
1195 drv_data->busy = 0;
1196
1197 /* init transfer tasklet */
1198 tasklet_init(&drv_data->pump_transfers,
1199 bfin_spi_pump_transfers, (unsigned long)drv_data);
1200
1201 /* init messages workqueue */
1202 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1203 drv_data->workqueue = create_singlethread_workqueue(
1204 dev_name(drv_data->master->dev.parent));
1205 if (drv_data->workqueue == NULL)
1206 return -EBUSY;
1207
1208 return 0;
1209 }
1210
1211 static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
1212 {
1213 unsigned long flags;
1214
1215 spin_lock_irqsave(&drv_data->lock, flags);
1216
1217 if (drv_data->running || drv_data->busy) {
1218 spin_unlock_irqrestore(&drv_data->lock, flags);
1219 return -EBUSY;
1220 }
1221
1222 drv_data->running = true;
1223 drv_data->cur_msg = NULL;
1224 drv_data->cur_transfer = NULL;
1225 drv_data->cur_chip = NULL;
1226 spin_unlock_irqrestore(&drv_data->lock, flags);
1227
1228 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1229
1230 return 0;
1231 }
1232
1233 static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
1234 {
1235 unsigned long flags;
1236 unsigned limit = 500;
1237 int status = 0;
1238
1239 spin_lock_irqsave(&drv_data->lock, flags);
1240
1241 /*
1242 * This is a bit lame, but is optimized for the common execution path.
1243 * A wait_queue on the drv_data->busy could be used, but then the common
1244 * execution path (pump_messages) would be required to call wake_up or
1245 * friends on every SPI message. Do this instead
1246 */
1247 drv_data->running = false;
1248 while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1249 spin_unlock_irqrestore(&drv_data->lock, flags);
1250 msleep(10);
1251 spin_lock_irqsave(&drv_data->lock, flags);
1252 }
1253
1254 if (!list_empty(&drv_data->queue) || drv_data->busy)
1255 status = -EBUSY;
1256
1257 spin_unlock_irqrestore(&drv_data->lock, flags);
1258
1259 return status;
1260 }
1261
1262 static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
1263 {
1264 int status;
1265
1266 status = bfin_spi_stop_queue(drv_data);
1267 if (status != 0)
1268 return status;
1269
1270 destroy_workqueue(drv_data->workqueue);
1271
1272 return 0;
1273 }
1274
1275 static int __init bfin_spi_probe(struct platform_device *pdev)
1276 {
1277 struct device *dev = &pdev->dev;
1278 struct bfin5xx_spi_master *platform_info;
1279 struct spi_master *master;
1280 struct bfin_spi_master_data *drv_data;
1281 struct resource *res;
1282 int status = 0;
1283
1284 platform_info = dev->platform_data;
1285
1286 /* Allocate master with space for drv_data */
1287 master = spi_alloc_master(dev, sizeof(*drv_data));
1288 if (!master) {
1289 dev_err(&pdev->dev, "can not alloc spi_master\n");
1290 return -ENOMEM;
1291 }
1292
1293 drv_data = spi_master_get_devdata(master);
1294 drv_data->master = master;
1295 drv_data->master_info = platform_info;
1296 drv_data->pdev = pdev;
1297 drv_data->pin_req = platform_info->pin_req;
1298
1299 /* the spi->mode bits supported by this driver: */
1300 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1301
1302 master->bus_num = pdev->id;
1303 master->num_chipselect = platform_info->num_chipselect;
1304 master->cleanup = bfin_spi_cleanup;
1305 master->setup = bfin_spi_setup;
1306 master->transfer = bfin_spi_transfer;
1307
1308 /* Find and map our resources */
1309 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1310 if (res == NULL) {
1311 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1312 status = -ENOENT;
1313 goto out_error_get_res;
1314 }
1315
1316 drv_data->regs = ioremap(res->start, resource_size(res));
1317 if (drv_data->regs == NULL) {
1318 dev_err(dev, "Cannot map IO\n");
1319 status = -ENXIO;
1320 goto out_error_ioremap;
1321 }
1322
1323 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1324 if (res == NULL) {
1325 dev_err(dev, "No DMA channel specified\n");
1326 status = -ENOENT;
1327 goto out_error_free_io;
1328 }
1329 drv_data->dma_channel = res->start;
1330
1331 drv_data->spi_irq = platform_get_irq(pdev, 0);
1332 if (drv_data->spi_irq < 0) {
1333 dev_err(dev, "No spi pio irq specified\n");
1334 status = -ENOENT;
1335 goto out_error_free_io;
1336 }
1337
1338 /* Initial and start queue */
1339 status = bfin_spi_init_queue(drv_data);
1340 if (status != 0) {
1341 dev_err(dev, "problem initializing queue\n");
1342 goto out_error_queue_alloc;
1343 }
1344
1345 status = bfin_spi_start_queue(drv_data);
1346 if (status != 0) {
1347 dev_err(dev, "problem starting queue\n");
1348 goto out_error_queue_alloc;
1349 }
1350
1351 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1352 if (status != 0) {
1353 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1354 goto out_error_queue_alloc;
1355 }
1356
1357 /* Reset SPI registers. If these registers were used by the boot loader,
1358 * the sky may fall on your head if you enable the dma controller.
1359 */
1360 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1361 bfin_write(&drv_data->regs->flg, 0xFF00);
1362
1363 /* Register with the SPI framework */
1364 platform_set_drvdata(pdev, drv_data);
1365 status = spi_register_master(master);
1366 if (status != 0) {
1367 dev_err(dev, "problem registering spi master\n");
1368 goto out_error_queue_alloc;
1369 }
1370
1371 dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n",
1372 DRV_DESC, DRV_VERSION, drv_data->regs,
1373 drv_data->dma_channel);
1374 return status;
1375
1376 out_error_queue_alloc:
1377 bfin_spi_destroy_queue(drv_data);
1378 out_error_free_io:
1379 iounmap(drv_data->regs);
1380 out_error_ioremap:
1381 out_error_get_res:
1382 spi_master_put(master);
1383
1384 return status;
1385 }
1386
1387 /* stop hardware and remove the driver */
1388 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1389 {
1390 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1391 int status = 0;
1392
1393 if (!drv_data)
1394 return 0;
1395
1396 /* Remove the queue */
1397 status = bfin_spi_destroy_queue(drv_data);
1398 if (status != 0)
1399 return status;
1400
1401 /* Disable the SSP at the peripheral and SOC level */
1402 bfin_spi_disable(drv_data);
1403
1404 /* Release DMA */
1405 if (drv_data->master_info->enable_dma) {
1406 if (dma_channel_active(drv_data->dma_channel))
1407 free_dma(drv_data->dma_channel);
1408 }
1409
1410 if (drv_data->irq_requested) {
1411 free_irq(drv_data->spi_irq, drv_data);
1412 drv_data->irq_requested = 0;
1413 }
1414
1415 /* Disconnect from the SPI framework */
1416 spi_unregister_master(drv_data->master);
1417
1418 peripheral_free_list(drv_data->pin_req);
1419
1420 /* Prevent double remove */
1421 platform_set_drvdata(pdev, NULL);
1422
1423 return 0;
1424 }
1425
1426 #ifdef CONFIG_PM
1427 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1428 {
1429 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1430 int status = 0;
1431
1432 status = bfin_spi_stop_queue(drv_data);
1433 if (status != 0)
1434 return status;
1435
1436 drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl);
1437 drv_data->flag_reg = bfin_read(&drv_data->regs->flg);
1438
1439 /*
1440 * reset SPI_CTL and SPI_FLG registers
1441 */
1442 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1443 bfin_write(&drv_data->regs->flg, 0xFF00);
1444
1445 return 0;
1446 }
1447
1448 static int bfin_spi_resume(struct platform_device *pdev)
1449 {
1450 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1451 int status = 0;
1452
1453 bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);
1454 bfin_write(&drv_data->regs->flg, drv_data->flag_reg);
1455
1456 /* Start the queue running */
1457 status = bfin_spi_start_queue(drv_data);
1458 if (status != 0) {
1459 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1460 return status;
1461 }
1462
1463 return 0;
1464 }
1465 #else
1466 #define bfin_spi_suspend NULL
1467 #define bfin_spi_resume NULL
1468 #endif /* CONFIG_PM */
1469
1470 MODULE_ALIAS("platform:bfin-spi");
1471 static struct platform_driver bfin_spi_driver = {
1472 .driver = {
1473 .name = DRV_NAME,
1474 .owner = THIS_MODULE,
1475 },
1476 .suspend = bfin_spi_suspend,
1477 .resume = bfin_spi_resume,
1478 .remove = __devexit_p(bfin_spi_remove),
1479 };
1480
1481 static int __init bfin_spi_init(void)
1482 {
1483 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1484 }
1485 subsys_initcall(bfin_spi_init);
1486
1487 static void __exit bfin_spi_exit(void)
1488 {
1489 platform_driver_unregister(&bfin_spi_driver);
1490 }
1491 module_exit(bfin_spi_exit);