drivers/usb/dwc3/core.h

   1 /**
   2  * core.h - DesignWare USB3 DRD Core Header
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #ifndef __DRIVERS_USB_DWC3_CORE_H
  40 #define __DRIVERS_USB_DWC3_CORE_H
  41
  42 #include <linux/device.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/ioport.h>
  45 #include <linux/list.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/mm.h>
  48 #include <linux/debugfs.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 /* Global constants */
  54 #define DWC3_ENDPOINTS_NUM      32
  55
  56 #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
  57 #define DWC3_EVENT_TYPE_MASK    0xfe
  58
  59 #define DWC3_EVENT_TYPE_DEV     0
  60 #define DWC3_EVENT_TYPE_CARKIT  3
  61 #define DWC3_EVENT_TYPE_I2C     4
  62
  63 #define DWC3_DEVICE_EVENT_DISCONNECT            0
  64 #define DWC3_DEVICE_EVENT_RESET                 1
  65 #define DWC3_DEVICE_EVENT_CONNECT_DONE          2
  66 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE    3
  67 #define DWC3_DEVICE_EVENT_WAKEUP                4
  68 #define DWC3_DEVICE_EVENT_EOPF                  6
  69 #define DWC3_DEVICE_EVENT_SOF                   7
  70 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR         9
  71 #define DWC3_DEVICE_EVENT_CMD_CMPL              10
  72 #define DWC3_DEVICE_EVENT_OVERFLOW              11
  73
  74 #define DWC3_GEVNTCOUNT_MASK    0xfffc
  75 #define DWC3_GSNPSID_MASK       0xffff0000
  76 #define DWC3_GSNPSREV_MASK      0xffff
  77
  78 /* Global Registers */
  79 #define DWC3_GSBUSCFG0          0xc100
  80 #define DWC3_GSBUSCFG1          0xc104
  81 #define DWC3_GTXTHRCFG          0xc108
  82 #define DWC3_GRXTHRCFG          0xc10c
  83 #define DWC3_GCTL               0xc110
  84 #define DWC3_GEVTEN             0xc114
  85 #define DWC3_GSTS               0xc118
  86 #define DWC3_GSNPSID            0xc120
  87 #define DWC3_GGPIO              0xc124
  88 #define DWC3_GUID               0xc128
  89 #define DWC3_GUCTL              0xc12c
  90 #define DWC3_GBUSERRADDR0       0xc130
  91 #define DWC3_GBUSERRADDR1       0xc134
  92 #define DWC3_GPRTBIMAP0         0xc138
  93 #define DWC3_GPRTBIMAP1         0xc13c
  94 #define DWC3_GHWPARAMS0         0xc140
  95 #define DWC3_GHWPARAMS1         0xc144
  96 #define DWC3_GHWPARAMS2         0xc148
  97 #define DWC3_GHWPARAMS3         0xc14c
  98 #define DWC3_GHWPARAMS4         0xc150
  99 #define DWC3_GHWPARAMS5         0xc154
 100 #define DWC3_GHWPARAMS6         0xc158
 101 #define DWC3_GHWPARAMS7         0xc15c
 102 #define DWC3_GDBGFIFOSPACE      0xc160
 103 #define DWC3_GDBGLTSSM          0xc164
 104 #define DWC3_GPRTBIMAP_HS0      0xc180
 105 #define DWC3_GPRTBIMAP_HS1      0xc184
 106 #define DWC3_GPRTBIMAP_FS0      0xc188
 107 #define DWC3_GPRTBIMAP_FS1      0xc18c
 108
 109 #define DWC3_GUSB2PHYCFG(n)     (0xc200 + (n * 0x04))
 110 #define DWC3_GUSB2I2CCTL(n)     (0xc240 + (n * 0x04))
 111
 112 #define DWC3_GUSB2PHYACC(n)     (0xc280 + (n * 0x04))
 113
 114 #define DWC3_GUSB3PIPECTL(n)    (0xc2c0 + (n * 0x04))
 115
 116 #define DWC3_GTXFIFOSIZ(n)      (0xc300 + (n * 0x04))
 117 #define DWC3_GRXFIFOSIZ(n)      (0xc380 + (n * 0x04))
 118
 119 #define DWC3_GEVNTADRLO(n)      (0xc400 + (n * 0x10))
 120 #define DWC3_GEVNTADRHI(n)      (0xc404 + (n * 0x10))
 121 #define DWC3_GEVNTSIZ(n)        (0xc408 + (n * 0x10))
 122 #define DWC3_GEVNTCOUNT(n)      (0xc40c + (n * 0x10))
 123
 124 #define DWC3_GHWPARAMS8         0xc600
 125
 126 /* Device Registers */
 127 #define DWC3_DCFG               0xc700
 128 #define DWC3_DCTL               0xc704
 129 #define DWC3_DEVTEN             0xc708
 130 #define DWC3_DSTS               0xc70c
 131 #define DWC3_DGCMDPAR           0xc710
 132 #define DWC3_DGCMD              0xc714
 133 #define DWC3_DALEPENA           0xc720
 134 #define DWC3_DEPCMDPAR2(n)      (0xc800 + (n * 0x10))
 135 #define DWC3_DEPCMDPAR1(n)      (0xc804 + (n * 0x10))
 136 #define DWC3_DEPCMDPAR0(n)      (0xc808 + (n * 0x10))
 137 #define DWC3_DEPCMD(n)          (0xc80c + (n * 0x10))
 138
 139 /* OTG Registers */
 140 #define DWC3_OCFG               0xcc00
 141 #define DWC3_OCTL               0xcc04
 142 #define DWC3_OEVTEN             0xcc08
 143 #define DWC3_OSTS               0xcc0C
 144
 145 /* Bit fields */
 146
 147 /* Global Configuration Register */
 148 #define DWC3_GCTL_PWRDNSCALE(n) (n << 19)
 149 #define DWC3_GCTL_U2RSTECN      (1 << 16)
 150 #define DWC3_GCTL_RAMCLKSEL(x)  ((x & DWC3_GCTL_CLK_MASK) << 6)
 151 #define DWC3_GCTL_CLK_BUS       (0)
 152 #define DWC3_GCTL_CLK_PIPE      (1)
 153 #define DWC3_GCTL_CLK_PIPEHALF  (2)
 154 #define DWC3_GCTL_CLK_MASK      (3)
 155
 156 #define DWC3_GCTL_PRTCAP(n)     (((n) & (3 << 12)) >> 12)
 157 #define DWC3_GCTL_PRTCAPDIR(n)  (n << 12)
 158 #define DWC3_GCTL_PRTCAP_HOST   1
 159 #define DWC3_GCTL_PRTCAP_DEVICE 2
 160 #define DWC3_GCTL_PRTCAP_OTG    3
 161
 162 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
 163 #define DWC3_GCTL_SCALEDOWN(n)  (n << 4)
 164 #define DWC3_GCTL_DISSCRAMBLE   (1 << 3)
 165 #define DWC3_GCTL_DSBLCLKGTNG   (1 << 0)
 166
 167 /* Global USB2 PHY Configuration Register */
 168 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
 169 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
 170
 171 /* Global USB3 PIPE Control Register */
 172 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
 173 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
 174
 175 /* Global HWPARAMS1 Register */
 176 #define DWC3_GHWPARAMS1_EN_PWROPT(n)    ((n & (3 << 24)) >> 24)
 177 #define DWC3_GHWPARAMS1_EN_PWROPT_NO    0
 178 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK   1
 179
 180 /* Device Configuration Register */
 181 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
 182 #define DWC3_DCFG_DEVADDR_MASK  DWC3_DCFG_DEVADDR(0x7f)
 183
 184 #define DWC3_DCFG_SPEED_MASK    (7 << 0)
 185 #define DWC3_DCFG_SUPERSPEED    (4 << 0)
 186 #define DWC3_DCFG_HIGHSPEED     (0 << 0)
 187 #define DWC3_DCFG_FULLSPEED2    (1 << 0)
 188 #define DWC3_DCFG_LOWSPEED      (2 << 0)
 189 #define DWC3_DCFG_FULLSPEED1    (3 << 0)
 190
 191 /* Device Control Register */
 192 #define DWC3_DCTL_RUN_STOP      (1 << 31)
 193 #define DWC3_DCTL_CSFTRST       (1 << 30)
 194 #define DWC3_DCTL_LSFTRST       (1 << 29)
 195
 196 #define DWC3_DCTL_HIRD_THRES_MASK       (0x1f << 24)
 197 #define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24)
 198
 199 #define DWC3_DCTL_APPL1RES      (1 << 23)
 200
 201 #define DWC3_DCTL_INITU2ENA     (1 << 12)
 202 #define DWC3_DCTL_ACCEPTU2ENA   (1 << 11)
 203 #define DWC3_DCTL_INITU1ENA     (1 << 10)
 204 #define DWC3_DCTL_ACCEPTU1ENA   (1 << 9)
 205 #define DWC3_DCTL_TSTCTRL_MASK  (0xf << 1)
 206
 207 #define DWC3_DCTL_ULSTCHNGREQ_MASK      (0x0f << 5)
 208 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
 209
 210 #define DWC3_DCTL_ULSTCHNG_NO_ACTION    (DWC3_DCTL_ULSTCHNGREQ(0))
 211 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED  (DWC3_DCTL_ULSTCHNGREQ(4))
 212 #define DWC3_DCTL_ULSTCHNG_RX_DETECT    (DWC3_DCTL_ULSTCHNGREQ(5))
 213 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE  (DWC3_DCTL_ULSTCHNGREQ(6))
 214 #define DWC3_DCTL_ULSTCHNG_RECOVERY     (DWC3_DCTL_ULSTCHNGREQ(8))
 215 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE   (DWC3_DCTL_ULSTCHNGREQ(10))
 216 #define DWC3_DCTL_ULSTCHNG_LOOPBACK     (DWC3_DCTL_ULSTCHNGREQ(11))
 217
 218 /* Device Event Enable Register */
 219 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN   (1 << 12)
 220 #define DWC3_DEVTEN_EVNTOVERFLOWEN      (1 << 11)
 221 #define DWC3_DEVTEN_CMDCMPLTEN          (1 << 10)
 222 #define DWC3_DEVTEN_ERRTICERREN         (1 << 9)
 223 #define DWC3_DEVTEN_SOFEN               (1 << 7)
 224 #define DWC3_DEVTEN_EOPFEN              (1 << 6)
 225 #define DWC3_DEVTEN_WKUPEVTEN           (1 << 4)
 226 #define DWC3_DEVTEN_ULSTCNGEN           (1 << 3)
 227 #define DWC3_DEVTEN_CONNECTDONEEN       (1 << 2)
 228 #define DWC3_DEVTEN_USBRSTEN            (1 << 1)
 229 #define DWC3_DEVTEN_DISCONNEVTEN        (1 << 0)
 230
 231 /* Device Status Register */
 232 #define DWC3_DSTS_PWRUPREQ              (1 << 24)
 233 #define DWC3_DSTS_COREIDLE              (1 << 23)
 234 #define DWC3_DSTS_DEVCTRLHLT            (1 << 22)
 235
 236 #define DWC3_DSTS_USBLNKST_MASK         (0x0f << 18)
 237 #define DWC3_DSTS_USBLNKST(n)           (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
 238
 239 #define DWC3_DSTS_RXFIFOEMPTY           (1 << 17)
 240
 241 #define DWC3_DSTS_SOFFN_MASK            (0x3ff << 3)
 242 #define DWC3_DSTS_SOFFN(n)              (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
 243
 244 #define DWC3_DSTS_CONNECTSPD            (7 << 0)
 245
 246 #define DWC3_DSTS_SUPERSPEED            (4 << 0)
 247 #define DWC3_DSTS_HIGHSPEED             (0 << 0)
 248 #define DWC3_DSTS_FULLSPEED2            (1 << 0)
 249 #define DWC3_DSTS_LOWSPEED              (2 << 0)
 250 #define DWC3_DSTS_FULLSPEED1            (3 << 0)
 251
 252 /* Device Generic Command Register */
 253 #define DWC3_DGCMD_SET_LMP              0x01
 254 #define DWC3_DGCMD_SET_PERIODIC_PAR     0x02
 255 #define DWC3_DGCMD_XMIT_FUNCTION        0x03
 256 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH  0x09
 257 #define DWC3_DGCMD_ALL_FIFO_FLUSH       0x0a
 258 #define DWC3_DGCMD_SET_ENDPOINT_NRDY    0x0c
 259 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
 260
 261 /* Device Endpoint Command Register */
 262 #define DWC3_DEPCMD_PARAM_SHIFT         16
 263 #define DWC3_DEPCMD_PARAM(x)            (x << DWC3_DEPCMD_PARAM_SHIFT)
 264 #define DWC3_DEPCMD_GET_RSC_IDX(x)      ((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
 265 #define DWC3_DEPCMD_STATUS_MASK         (0x0f << 12)
 266 #define DWC3_DEPCMD_STATUS(x)           ((x & DWC3_DEPCMD_STATUS_MASK) >> 12)
 267 #define DWC3_DEPCMD_HIPRI_FORCERM       (1 << 11)
 268 #define DWC3_DEPCMD_CMDACT              (1 << 10)
 269 #define DWC3_DEPCMD_CMDIOC              (1 << 8)
 270
 271 #define DWC3_DEPCMD_DEPSTARTCFG         (0x09 << 0)
 272 #define DWC3_DEPCMD_ENDTRANSFER         (0x08 << 0)
 273 #define DWC3_DEPCMD_UPDATETRANSFER      (0x07 << 0)
 274 #define DWC3_DEPCMD_STARTTRANSFER       (0x06 << 0)
 275 #define DWC3_DEPCMD_CLEARSTALL          (0x05 << 0)
 276 #define DWC3_DEPCMD_SETSTALL            (0x04 << 0)
 277 #define DWC3_DEPCMD_GETSEQNUMBER        (0x03 << 0)
 278 #define DWC3_DEPCMD_SETTRANSFRESOURCE   (0x02 << 0)
 279 #define DWC3_DEPCMD_SETEPCONFIG         (0x01 << 0)
 280
 281 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
 282 #define DWC3_DALEPENA_EP(n)             (1 << n)
 283
 284 #define DWC3_DEPCMD_TYPE_CONTROL        0
 285 #define DWC3_DEPCMD_TYPE_ISOC           1
 286 #define DWC3_DEPCMD_TYPE_BULK           2
 287 #define DWC3_DEPCMD_TYPE_INTR           3
 288
 289 /* Structures */
 290
 291 struct dwc3_trb_hw;
 292
 293 /**
 294  * struct dwc3_event_buffer - Software event buffer representation
 295  * @list: a list of event buffers
 296  * @buf: _THE_ buffer
 297  * @length: size of this buffer
 298  * @dma: dma_addr_t
 299  * @dwc: pointer to DWC controller
 300  */
 301 struct dwc3_event_buffer {
 302         void                    *buf;
 303         unsigned                length;
 304         unsigned int            lpos;
 305
 306         dma_addr_t              dma;
 307
 308         struct dwc3             *dwc;
 309 };
 310
 311 #define DWC3_EP_FLAG_STALLED    (1 << 0)
 312 #define DWC3_EP_FLAG_WEDGED     (1 << 1)
 313
 314 #define DWC3_EP_DIRECTION_TX    true
 315 #define DWC3_EP_DIRECTION_RX    false
 316
 317 #define DWC3_TRB_NUM            32
 318 #define DWC3_TRB_MASK           (DWC3_TRB_NUM - 1)
 319
 320 /**
 321  * struct dwc3_ep - device side endpoint representation
 322  * @endpoint: usb endpoint
 323  * @request_list: list of requests for this endpoint
 324  * @req_queued: list of requests on this ep which have TRBs setup
 325  * @trb_pool: array of transaction buffers
 326  * @trb_pool_dma: dma address of @trb_pool
 327  * @free_slot: next slot which is going to be used
 328  * @busy_slot: first slot which is owned by HW
 329  * @desc: usb_endpoint_descriptor pointer
 330  * @dwc: pointer to DWC controller
 331  * @flags: endpoint flags (wedged, stalled, ...)
 332  * @current_trb: index of current used trb
 333  * @number: endpoint number (1 - 15)
 334  * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
 335  * @res_trans_idx: Resource transfer index
 336  * @interval: the intervall on which the ISOC transfer is started
 337  * @name: a human readable name e.g. ep1out-bulk
 338  * @direction: true for TX, false for RX
 339  * @stream_capable: true when streams are enabled
 340  */
 341 struct dwc3_ep {
 342         struct usb_ep           endpoint;
 343         struct list_head        request_list;
 344         struct list_head        req_queued;
 345
 346         struct dwc3_trb_hw      *trb_pool;
 347         dma_addr_t              trb_pool_dma;
 348         u32                     free_slot;
 349         u32                     busy_slot;
 350         const struct usb_endpoint_descriptor *desc;
 351         const struct usb_ss_ep_comp_descriptor *comp_desc;
 352         struct dwc3             *dwc;
 353
 354         unsigned                flags;
 355 #define DWC3_EP_ENABLED         (1 << 0)
 356 #define DWC3_EP_STALL           (1 << 1)
 357 #define DWC3_EP_WEDGE           (1 << 2)
 358 #define DWC3_EP_BUSY            (1 << 4)
 359 #define DWC3_EP_PENDING_REQUEST (1 << 5)
 360
 361         /* This last one is specific to EP0 */
 362 #define DWC3_EP0_DIR_IN         (1 << 31)
 363
 364         unsigned                current_trb;
 365
 366         u8                      number;
 367         u8                      type;
 368         u8                      res_trans_idx;
 369         u32                     interval;
 370
 371         char                    name[20];
 372
 373         unsigned                direction:1;
 374         unsigned                stream_capable:1;
 375 };
 376
 377 enum dwc3_phy {
 378         DWC3_PHY_UNKNOWN = 0,
 379         DWC3_PHY_USB3,
 380         DWC3_PHY_USB2,
 381 };
 382
 383 enum dwc3_ep0_next {
 384         DWC3_EP0_UNKNOWN = 0,
 385         DWC3_EP0_COMPLETE,
 386         DWC3_EP0_NRDY_SETUP,
 387         DWC3_EP0_NRDY_DATA,
 388         DWC3_EP0_NRDY_STATUS,
 389 };
 390
 391 enum dwc3_ep0_state {
 392         EP0_UNCONNECTED         = 0,
 393         EP0_SETUP_PHASE,
 394         EP0_DATA_PHASE,
 395         EP0_STATUS_PHASE,
 396 };
 397
 398 enum dwc3_link_state {
 399         /* In SuperSpeed */
 400         DWC3_LINK_STATE_U0              = 0x00, /* in HS, means ON */
 401         DWC3_LINK_STATE_U1              = 0x01,
 402         DWC3_LINK_STATE_U2              = 0x02, /* in HS, means SLEEP */
 403         DWC3_LINK_STATE_U3              = 0x03, /* in HS, means SUSPEND */
 404         DWC3_LINK_STATE_SS_DIS          = 0x04,
 405         DWC3_LINK_STATE_RX_DET          = 0x05, /* in HS, means Early Suspend */
 406         DWC3_LINK_STATE_SS_INACT        = 0x06,
 407         DWC3_LINK_STATE_POLL            = 0x07,
 408         DWC3_LINK_STATE_RECOV           = 0x08,
 409         DWC3_LINK_STATE_HRESET          = 0x09,
 410         DWC3_LINK_STATE_CMPLY           = 0x0a,
 411         DWC3_LINK_STATE_LPBK            = 0x0b,
 412         DWC3_LINK_STATE_MASK            = 0x0f,
 413 };
 414
 415 enum dwc3_device_state {
 416         DWC3_DEFAULT_STATE,
 417         DWC3_ADDRESS_STATE,
 418         DWC3_CONFIGURED_STATE,
 419 };
 420
 421 /**
 422  * struct dwc3_trb - transfer request block
 423  * @bpl: lower 32bit of the buffer
 424  * @bph: higher 32bit of the buffer
 425  * @length: buffer size (up to 16mb - 1)
 426  * @pcm1: packet count m1
 427  * @trbsts: trb status
 428  *      0 = ok
 429  *      1 = missed isoc
 430  *      2 = setup pending
 431  * @hwo: hardware owner of descriptor
 432  * @lst: last trb
 433  * @chn: chain buffers
 434  * @csp: continue on short packets (only supported on isoc eps)
 435  * @trbctl: trb control
 436  *      1 = normal
 437  *      2 = control-setup
 438  *      3 = control-status-2
 439  *      4 = control-status-3
 440  *      5 = control-data (first trb of data stage)
 441  *      6 = isochronous-first (first trb of service interval)
 442  *      7 = isochronous
 443  *      8 = link trb
 444  *      others = reserved
 445  * @isp_imi: interrupt on short packet / interrupt on missed isoc
 446  * @ioc: interrupt on complete
 447  * @sid_sofn: Stream ID / SOF Number
 448  */
 449 struct dwc3_trb {
 450         u64             bplh;
 451
 452         union {
 453                 struct {
 454                         u32             length:24;
 455                         u32             pcm1:2;
 456                         u32             reserved27_26:2;
 457                         u32             trbsts:4;
 458 #define DWC3_TRB_STS_OKAY                       0
 459 #define DWC3_TRB_STS_MISSED_ISOC                1
 460 #define DWC3_TRB_STS_SETUP_PENDING              2
 461                 };
 462                 u32 len_pcm;
 463         };
 464
 465         union {
 466                 struct {
 467                         u32             hwo:1;
 468                         u32             lst:1;
 469                         u32             chn:1;
 470                         u32             csp:1;
 471                         u32             trbctl:6;
 472                         u32             isp_imi:1;
 473                         u32             ioc:1;
 474                         u32             reserved13_12:2;
 475                         u32             sid_sofn:16;
 476                         u32             reserved31_30:2;
 477                 };
 478                 u32 control;
 479         };
 480 } __packed;
 481
 482 /**
 483  * struct dwc3_trb_hw - transfer request block (hw format)
 484  * @bpl: DW0-3
 485  * @bph: DW4-7
 486  * @size: DW8-B
 487  * @trl: DWC-F
 488  */
 489 struct dwc3_trb_hw {
 490         __le32          bpl;
 491         __le32          bph;
 492         __le32          size;
 493         __le32          ctrl;
 494 } __packed;
 495
 496 static inline void dwc3_trb_to_hw(struct dwc3_trb *nat, struct dwc3_trb_hw *hw)
 497 {
 498         hw->bpl = cpu_to_le32(lower_32_bits(nat->bplh));
 499         hw->bph = cpu_to_le32(upper_32_bits(nat->bplh));
 500         hw->size = cpu_to_le32p(&nat->len_pcm);
 501         /* HWO is written last */
 502         hw->ctrl = cpu_to_le32p(&nat->control);
 503 }
 504
 505 static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat)
 506 {
 507         u64 bplh;
 508
 509         bplh = le32_to_cpup(&hw->bpl);
 510         bplh |= (u64) le32_to_cpup(&hw->bph) << 32;
 511         nat->bplh = bplh;
 512
 513         nat->len_pcm = le32_to_cpup(&hw->size);
 514         nat->control = le32_to_cpup(&hw->ctrl);
 515 }
 516
 517 /**
 518  * dwc3_hwparams - copy of HWPARAMS registers
 519  * @hwparams0 - GHWPARAMS0
 520  * @hwparams1 - GHWPARAMS1
 521  * @hwparams2 - GHWPARAMS2
 522  * @hwparams3 - GHWPARAMS3
 523  * @hwparams4 - GHWPARAMS4
 524  * @hwparams5 - GHWPARAMS5
 525  * @hwparams6 - GHWPARAMS6
 526  * @hwparams7 - GHWPARAMS7
 527  * @hwparams8 - GHWPARAMS8
 528  */
 529 struct dwc3_hwparams {
 530         u32     hwparams0;
 531         u32     hwparams1;
 532         u32     hwparams2;
 533         u32     hwparams3;
 534         u32     hwparams4;
 535         u32     hwparams5;
 536         u32     hwparams6;
 537         u32     hwparams7;
 538         u32     hwparams8;
 539 };
 540
 541 /* HWPARAMS0 */
 542 #define DWC3_MODE(n)            ((n) & 0x7)
 543
 544 #define DWC3_MODE_DEVICE        0
 545 #define DWC3_MODE_HOST          1
 546 #define DWC3_MODE_DRD           2
 547 #define DWC3_MODE_HUB           3
 548
 549 /* HWPARAMS1 */
 550 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
 551
 552 struct dwc3_request {
 553         struct usb_request      request;
 554         struct list_head        list;
 555         struct dwc3_ep          *dep;
 556
 557         u8                      epnum;
 558         struct dwc3_trb_hw      *trb;
 559         dma_addr_t              trb_dma;
 560
 561         unsigned                direction:1;
 562         unsigned                mapped:1;
 563         unsigned                queued:1;
 564 };
 565
 566 /**
 567  * struct dwc3 - representation of our controller
 568  * @ctrl_req: usb control request which is used for ep0
 569  * @ep0_trb: trb which is used for the ctrl_req
 570  * @ep0_bounce: bounce buffer for ep0
 571  * @setup_buf: used while precessing STD USB requests
 572  * @ctrl_req_addr: dma address of ctrl_req
 573  * @ep0_trb: dma address of ep0_trb
 574  * @ep0_usb_req: dummy req used while handling STD USB requests
 575  * @setup_buf_addr: dma address of setup_buf
 576  * @ep0_bounce_addr: dma address of ep0_bounce
 577  * @lock: for synchronizing
 578  * @dev: pointer to our struct device
 579  * @xhci: pointer to our xHCI child
 580  * @event_buffer_list: a list of event buffers
 581  * @gadget: device side representation of the peripheral controller
 582  * @gadget_driver: pointer to the gadget driver
 583  * @regs: base address for our registers
 584  * @regs_size: address space size
 585  * @irq: IRQ number
 586  * @num_event_buffers: calculated number of event buffers
 587  * @u1u2: only used on revisions <1.83a for workaround
 588  * @maximum_speed: maximum speed requested (mainly for testing purposes)
 589  * @revision: revision register contents
 590  * @mode: mode of operation
 591  * @is_selfpowered: true when we are selfpowered
 592  * @three_stage_setup: set if we perform a three phase setup
 593  * @ep0_bounced: true when we used bounce buffer
 594  * @ep0_expect_in: true when we expect a DATA IN transfer
 595  * @start_config_issued: true when StartConfig command has been issued
 596  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
 597  * @ep0_next_event: hold the next expected event
 598  * @ep0state: state of endpoint zero
 599  * @link_state: link state
 600  * @speed: device speed (super, high, full, low)
 601  * @mem: points to start of memory which is used for this struct.
 602  * @hwparams: copy of hwparams registers
 603  * @root: debugfs root folder pointer
 604  */
 605 struct dwc3 {
 606         struct usb_ctrlrequest  *ctrl_req;
 607         struct dwc3_trb_hw      *ep0_trb;
 608         void                    *ep0_bounce;
 609         u8                      *setup_buf;
 610         dma_addr_t              ctrl_req_addr;
 611         dma_addr_t              ep0_trb_addr;
 612         dma_addr_t              setup_buf_addr;
 613         dma_addr_t              ep0_bounce_addr;
 614         struct dwc3_request     ep0_usb_req;
 615         /* device lock */
 616         spinlock_t              lock;
 617         struct device           *dev;
 618
 619         struct platform_device  *xhci;
 620         struct resource         *res;
 621
 622         struct dwc3_event_buffer **ev_buffs;
 623         struct dwc3_ep          *eps[DWC3_ENDPOINTS_NUM];
 624
 625         struct usb_gadget       gadget;
 626         struct usb_gadget_driver *gadget_driver;
 627
 628         void __iomem            *regs;
 629         size_t                  regs_size;
 630
 631         int                     irq;
 632
 633         u32                     num_event_buffers;
 634         u32                     u1u2;
 635         u32                     maximum_speed;
 636         u32                     revision;
 637         u32                     mode;
 638
 639 #define DWC3_REVISION_173A      0x5533173a
 640 #define DWC3_REVISION_175A      0x5533175a
 641 #define DWC3_REVISION_180A      0x5533180a
 642 #define DWC3_REVISION_183A      0x5533183a
 643 #define DWC3_REVISION_185A      0x5533185a
 644 #define DWC3_REVISION_188A      0x5533188a
 645 #define DWC3_REVISION_190A      0x5533190a
 646
 647         unsigned                is_selfpowered:1;
 648         unsigned                three_stage_setup:1;
 649         unsigned                ep0_bounced:1;
 650         unsigned                ep0_expect_in:1;
 651         unsigned                start_config_issued:1;
 652         unsigned                setup_packet_pending:1;
 653         unsigned                delayed_status:1;
 654
 655         enum dwc3_ep0_next      ep0_next_event;
 656         enum dwc3_ep0_state     ep0state;
 657         enum dwc3_link_state    link_state;
 658         enum dwc3_device_state  dev_state;
 659
 660         u8                      speed;
 661         void                    *mem;
 662
 663         struct dwc3_hwparams    hwparams;
 664         struct dentry           *root;
 665 };
 666
 667 /* -------------------------------------------------------------------------- */
 668
 669 #define DWC3_TRBSTS_OK                  0
 670 #define DWC3_TRBSTS_MISSED_ISOC         1
 671 #define DWC3_TRBSTS_SETUP_PENDING       2
 672
 673 #define DWC3_TRBCTL_NORMAL              1
 674 #define DWC3_TRBCTL_CONTROL_SETUP       2
 675 #define DWC3_TRBCTL_CONTROL_STATUS2     3
 676 #define DWC3_TRBCTL_CONTROL_STATUS3     4
 677 #define DWC3_TRBCTL_CONTROL_DATA        5
 678 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST   6
 679 #define DWC3_TRBCTL_ISOCHRONOUS         7
 680 #define DWC3_TRBCTL_LINK_TRB            8
 681
 682 /* -------------------------------------------------------------------------- */
 683
 684 struct dwc3_event_type {
 685         u32     is_devspec:1;
 686         u32     type:6;
 687         u32     reserved8_31:25;
 688 } __packed;
 689
 690 #define DWC3_DEPEVT_XFERCOMPLETE        0x01
 691 #define DWC3_DEPEVT_XFERINPROGRESS      0x02
 692 #define DWC3_DEPEVT_XFERNOTREADY        0x03
 693 #define DWC3_DEPEVT_RXTXFIFOEVT         0x04
 694 #define DWC3_DEPEVT_STREAMEVT           0x06
 695 #define DWC3_DEPEVT_EPCMDCMPLT          0x07
 696
 697 /**
 698  * struct dwc3_event_depvt - Device Endpoint Events
 699  * @one_bit: indicates this is an endpoint event (not used)
 700  * @endpoint_number: number of the endpoint
 701  * @endpoint_event: The event we have:
 702  *      0x00    - Reserved
 703  *      0x01    - XferComplete
 704  *      0x02    - XferInProgress
 705  *      0x03    - XferNotReady
 706  *      0x04    - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
 707  *      0x05    - Reserved
 708  *      0x06    - StreamEvt
 709  *      0x07    - EPCmdCmplt
 710  * @reserved11_10: Reserved, don't use.
 711  * @status: Indicates the status of the event. Refer to databook for
 712  *      more information.
 713  * @parameters: Parameters of the current event. Refer to databook for
 714  *      more information.
 715  */
 716 struct dwc3_event_depevt {
 717         u32     one_bit:1;
 718         u32     endpoint_number:5;
 719         u32     endpoint_event:4;
 720         u32     reserved11_10:2;
 721         u32     status:4;
 722 #define DEPEVT_STATUS_BUSERR    (1 << 0)
 723 #define DEPEVT_STATUS_SHORT     (1 << 1)
 724 #define DEPEVT_STATUS_IOC       (1 << 2)
 725 #define DEPEVT_STATUS_LST       (1 << 3)
 726
 727 /* Stream event only */
 728 #define DEPEVT_STREAMEVT_FOUND          1
 729 #define DEPEVT_STREAMEVT_NOTFOUND       2
 730
 731 /* Control-only Status */
 732 #define DEPEVT_STATUS_CONTROL_SETUP     0
 733 #define DEPEVT_STATUS_CONTROL_DATA      1
 734 #define DEPEVT_STATUS_CONTROL_STATUS    2
 735
 736         u32     parameters:16;
 737 } __packed;
 738
 739 /**
 740  * struct dwc3_event_devt - Device Events
 741  * @one_bit: indicates this is a non-endpoint event (not used)
 742  * @device_event: indicates it's a device event. Should read as 0x00
 743  * @type: indicates the type of device event.
 744  *      0       - DisconnEvt
 745  *      1       - USBRst
 746  *      2       - ConnectDone
 747  *      3       - ULStChng
 748  *      4       - WkUpEvt
 749  *      5       - Reserved
 750  *      6       - EOPF
 751  *      7       - SOF
 752  *      8       - Reserved
 753  *      9       - ErrticErr
 754  *      10      - CmdCmplt
 755  *      11      - EvntOverflow
 756  *      12      - VndrDevTstRcved
 757  * @reserved15_12: Reserved, not used
 758  * @event_info: Information about this event
 759  * @reserved31_24: Reserved, not used
 760  */
 761 struct dwc3_event_devt {
 762         u32     one_bit:1;
 763         u32     device_event:7;
 764         u32     type:4;
 765         u32     reserved15_12:4;
 766         u32     event_info:8;
 767         u32     reserved31_24:8;
 768 } __packed;
 769
 770 /**
 771  * struct dwc3_event_gevt - Other Core Events
 772  * @one_bit: indicates this is a non-endpoint event (not used)
 773  * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
 774  * @phy_port_number: self-explanatory
 775  * @reserved31_12: Reserved, not used.
 776  */
 777 struct dwc3_event_gevt {
 778         u32     one_bit:1;
 779         u32     device_event:7;
 780         u32     phy_port_number:4;
 781         u32     reserved31_12:20;
 782 } __packed;
 783
 784 /**
 785  * union dwc3_event - representation of Event Buffer contents
 786  * @raw: raw 32-bit event
 787  * @type: the type of the event
 788  * @depevt: Device Endpoint Event
 789  * @devt: Device Event
 790  * @gevt: Global Event
 791  */
 792 union dwc3_event {
 793         u32                             raw;
 794         struct dwc3_event_type          type;
 795         struct dwc3_event_depevt        depevt;
 796         struct dwc3_event_devt          devt;
 797         struct dwc3_event_gevt          gevt;
 798 };
 799
 800 /*
 801  * DWC3 Features to be used as Driver Data
 802  */
 803
 804 #define DWC3_HAS_PERIPHERAL             BIT(0)
 805 #define DWC3_HAS_XHCI                   BIT(1)
 806 #define DWC3_HAS_OTG                    BIT(3)
 807
 808 /* prototypes */
 809 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
 810
 811 int dwc3_host_init(struct dwc3 *dwc);
 812 void dwc3_host_exit(struct dwc3 *dwc);
 813
 814 int dwc3_gadget_init(struct dwc3 *dwc);
 815 void dwc3_gadget_exit(struct dwc3 *dwc);
 816
 817 extern int dwc3_get_device_id(void);
 818 extern void dwc3_put_device_id(int id);
 819
 820 #endif /* __DRIVERS_USB_DWC3_CORE_H */