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[pohmelfs.git] / drivers / usb / otg / msm_otg.c
blobb276f8fcdeba7970f24f2457e406112cc0721743
1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/delay.h>
27 #include <linux/io.h>
28 #include <linux/ioport.h>
29 #include <linux/uaccess.h>
30 #include <linux/debugfs.h>
31 #include <linux/seq_file.h>
32 #include <linux/pm_runtime.h>
33
34 #include <linux/usb.h>
35 #include <linux/usb/otg.h>
36 #include <linux/usb/ulpi.h>
37 #include <linux/usb/gadget.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/usb/msm_hsusb.h>
40 #include <linux/usb/msm_hsusb_hw.h>
41 #include <linux/regulator/consumer.h>
42
43 #include <mach/clk.h>
44
45 #define MSM_USB_BASE (motg->regs)
46 #define DRIVER_NAME "msm_otg"
47
48 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
49
50 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
51 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
52 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
53 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
54
55 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
56 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
57 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
58 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
59
60 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
61 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
62
63 static struct regulator *hsusb_3p3;
64 static struct regulator *hsusb_1p8;
65 static struct regulator *hsusb_vddcx;
66
67 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
68 {
69 int ret = 0;
70
71 if (init) {
72 hsusb_vddcx = regulator_get(motg->otg.dev, "HSUSB_VDDCX");
73 if (IS_ERR(hsusb_vddcx)) {
74 dev_err(motg->otg.dev, "unable to get hsusb vddcx\n");
75 return PTR_ERR(hsusb_vddcx);
76 }
77
78 ret = regulator_set_voltage(hsusb_vddcx,
79 USB_PHY_VDD_DIG_VOL_MIN,
80 USB_PHY_VDD_DIG_VOL_MAX);
81 if (ret) {
82 dev_err(motg->otg.dev, "unable to set the voltage "
83 "for hsusb vddcx\n");
84 regulator_put(hsusb_vddcx);
85 return ret;
86 }
87
88 ret = regulator_enable(hsusb_vddcx);
89 if (ret) {
90 dev_err(motg->otg.dev, "unable to enable hsusb vddcx\n");
91 regulator_put(hsusb_vddcx);
92 }
93 } else {
94 ret = regulator_set_voltage(hsusb_vddcx, 0,
95 USB_PHY_VDD_DIG_VOL_MAX);
96 if (ret)
97 dev_err(motg->otg.dev, "unable to set the voltage "
98 "for hsusb vddcx\n");
99 ret = regulator_disable(hsusb_vddcx);
100 if (ret)
101 dev_err(motg->otg.dev, "unable to disable hsusb vddcx\n");
102
103 regulator_put(hsusb_vddcx);
104 }
105
106 return ret;
107 }
108
109 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
110 {
111 int rc = 0;
112
113 if (init) {
114 hsusb_3p3 = regulator_get(motg->otg.dev, "HSUSB_3p3");
115 if (IS_ERR(hsusb_3p3)) {
116 dev_err(motg->otg.dev, "unable to get hsusb 3p3\n");
117 return PTR_ERR(hsusb_3p3);
118 }
119
120 rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN,
121 USB_PHY_3P3_VOL_MAX);
122 if (rc) {
123 dev_err(motg->otg.dev, "unable to set voltage level "
124 "for hsusb 3p3\n");
125 goto put_3p3;
126 }
127 rc = regulator_enable(hsusb_3p3);
128 if (rc) {
129 dev_err(motg->otg.dev, "unable to enable the hsusb 3p3\n");
130 goto put_3p3;
131 }
132 hsusb_1p8 = regulator_get(motg->otg.dev, "HSUSB_1p8");
133 if (IS_ERR(hsusb_1p8)) {
134 dev_err(motg->otg.dev, "unable to get hsusb 1p8\n");
135 rc = PTR_ERR(hsusb_1p8);
136 goto disable_3p3;
137 }
138 rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN,
139 USB_PHY_1P8_VOL_MAX);
140 if (rc) {
141 dev_err(motg->otg.dev, "unable to set voltage level "
142 "for hsusb 1p8\n");
143 goto put_1p8;
144 }
145 rc = regulator_enable(hsusb_1p8);
146 if (rc) {
147 dev_err(motg->otg.dev, "unable to enable the hsusb 1p8\n");
148 goto put_1p8;
149 }
150
151 return 0;
152 }
153
154 regulator_disable(hsusb_1p8);
155 put_1p8:
156 regulator_put(hsusb_1p8);
157 disable_3p3:
158 regulator_disable(hsusb_3p3);
159 put_3p3:
160 regulator_put(hsusb_3p3);
161 return rc;
162 }
163
164 #ifdef CONFIG_PM_SLEEP
165 #define USB_PHY_SUSP_DIG_VOL 500000
166 static int msm_hsusb_config_vddcx(int high)
167 {
168 int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
169 int min_vol;
170 int ret;
171
172 if (high)
173 min_vol = USB_PHY_VDD_DIG_VOL_MIN;
174 else
175 min_vol = USB_PHY_SUSP_DIG_VOL;
176
177 ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
178 if (ret) {
179 pr_err("%s: unable to set the voltage for regulator "
180 "HSUSB_VDDCX\n", __func__);
181 return ret;
182 }
183
184 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
185
186 return ret;
187 }
188 #endif
189
190 static int msm_hsusb_ldo_set_mode(int on)
191 {
192 int ret = 0;
193
194 if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) {
195 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
196 return -ENODEV;
197 }
198
199 if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) {
200 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
201 return -ENODEV;
202 }
203
204 if (on) {
205 ret = regulator_set_optimum_mode(hsusb_1p8,
206 USB_PHY_1P8_HPM_LOAD);
207 if (ret < 0) {
208 pr_err("%s: Unable to set HPM of the regulator "
209 "HSUSB_1p8\n", __func__);
210 return ret;
211 }
212 ret = regulator_set_optimum_mode(hsusb_3p3,
213 USB_PHY_3P3_HPM_LOAD);
214 if (ret < 0) {
215 pr_err("%s: Unable to set HPM of the regulator "
216 "HSUSB_3p3\n", __func__);
217 regulator_set_optimum_mode(hsusb_1p8,
218 USB_PHY_1P8_LPM_LOAD);
219 return ret;
220 }
221 } else {
222 ret = regulator_set_optimum_mode(hsusb_1p8,
223 USB_PHY_1P8_LPM_LOAD);
224 if (ret < 0)
225 pr_err("%s: Unable to set LPM of the regulator "
226 "HSUSB_1p8\n", __func__);
227 ret = regulator_set_optimum_mode(hsusb_3p3,
228 USB_PHY_3P3_LPM_LOAD);
229 if (ret < 0)
230 pr_err("%s: Unable to set LPM of the regulator "
231 "HSUSB_3p3\n", __func__);
232 }
233
234 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
235 return ret < 0 ? ret : 0;
236 }
237
238 static int ulpi_read(struct otg_transceiver *otg, u32 reg)
239 {
240 struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
241 int cnt = 0;
242
243 /* initiate read operation */
244 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
245 USB_ULPI_VIEWPORT);
246
247 /* wait for completion */
248 while (cnt < ULPI_IO_TIMEOUT_USEC) {
249 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
250 break;
251 udelay(1);
252 cnt++;
253 }
254
255 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
256 dev_err(otg->dev, "ulpi_read: timeout %08x\n",
257 readl(USB_ULPI_VIEWPORT));
258 return -ETIMEDOUT;
259 }
260 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
261 }
262
263 static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
264 {
265 struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
266 int cnt = 0;
267
268 /* initiate write operation */
269 writel(ULPI_RUN | ULPI_WRITE |
270 ULPI_ADDR(reg) | ULPI_DATA(val),
271 USB_ULPI_VIEWPORT);
272
273 /* wait for completion */
274 while (cnt < ULPI_IO_TIMEOUT_USEC) {
275 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
276 break;
277 udelay(1);
278 cnt++;
279 }
280
281 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
282 dev_err(otg->dev, "ulpi_write: timeout\n");
283 return -ETIMEDOUT;
284 }
285 return 0;
286 }
287
288 static struct otg_io_access_ops msm_otg_io_ops = {
289 .read = ulpi_read,
290 .write = ulpi_write,
291 };
292
293 static void ulpi_init(struct msm_otg *motg)
294 {
295 struct msm_otg_platform_data *pdata = motg->pdata;
296 int *seq = pdata->phy_init_seq;
297
298 if (!seq)
299 return;
300
301 while (seq[0] >= 0) {
302 dev_vdbg(motg->otg.dev, "ulpi: write 0x%02x to 0x%02x\n",
303 seq[0], seq[1]);
304 ulpi_write(&motg->otg, seq[0], seq[1]);
305 seq += 2;
306 }
307 }
308
309 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
310 {
311 int ret;
312
313 if (assert) {
314 ret = clk_reset(motg->clk, CLK_RESET_ASSERT);
315 if (ret)
316 dev_err(motg->otg.dev, "usb hs_clk assert failed\n");
317 } else {
318 ret = clk_reset(motg->clk, CLK_RESET_DEASSERT);
319 if (ret)
320 dev_err(motg->otg.dev, "usb hs_clk deassert failed\n");
321 }
322 return ret;
323 }
324
325 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
326 {
327 int ret;
328
329 ret = clk_reset(motg->phy_reset_clk, CLK_RESET_ASSERT);
330 if (ret) {
331 dev_err(motg->otg.dev, "usb phy clk assert failed\n");
332 return ret;
333 }
334 usleep_range(10000, 12000);
335 ret = clk_reset(motg->phy_reset_clk, CLK_RESET_DEASSERT);
336 if (ret)
337 dev_err(motg->otg.dev, "usb phy clk deassert failed\n");
338 return ret;
339 }
340
341 static int msm_otg_phy_reset(struct msm_otg *motg)
342 {
343 u32 val;
344 int ret;
345 int retries;
346
347 ret = msm_otg_link_clk_reset(motg, 1);
348 if (ret)
349 return ret;
350 ret = msm_otg_phy_clk_reset(motg);
351 if (ret)
352 return ret;
353 ret = msm_otg_link_clk_reset(motg, 0);
354 if (ret)
355 return ret;
356
357 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
358 writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
359
360 for (retries = 3; retries > 0; retries--) {
361 ret = ulpi_write(&motg->otg, ULPI_FUNC_CTRL_SUSPENDM,
362 ULPI_CLR(ULPI_FUNC_CTRL));
363 if (!ret)
364 break;
365 ret = msm_otg_phy_clk_reset(motg);
366 if (ret)
367 return ret;
368 }
369 if (!retries)
370 return -ETIMEDOUT;
371
372 /* This reset calibrates the phy, if the above write succeeded */
373 ret = msm_otg_phy_clk_reset(motg);
374 if (ret)
375 return ret;
376
377 for (retries = 3; retries > 0; retries--) {
378 ret = ulpi_read(&motg->otg, ULPI_DEBUG);
379 if (ret != -ETIMEDOUT)
380 break;
381 ret = msm_otg_phy_clk_reset(motg);
382 if (ret)
383 return ret;
384 }
385 if (!retries)
386 return -ETIMEDOUT;
387
388 dev_info(motg->otg.dev, "phy_reset: success\n");
389 return 0;
390 }
391
392 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
393 static int msm_otg_reset(struct otg_transceiver *otg)
394 {
395 struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
396 struct msm_otg_platform_data *pdata = motg->pdata;
397 int cnt = 0;
398 int ret;
399 u32 val = 0;
400 u32 ulpi_val = 0;
401
402 ret = msm_otg_phy_reset(motg);
403 if (ret) {
404 dev_err(otg->dev, "phy_reset failed\n");
405 return ret;
406 }
407
408 ulpi_init(motg);
409
410 writel(USBCMD_RESET, USB_USBCMD);
411 while (cnt < LINK_RESET_TIMEOUT_USEC) {
412 if (!(readl(USB_USBCMD) & USBCMD_RESET))
413 break;
414 udelay(1);
415 cnt++;
416 }
417 if (cnt >= LINK_RESET_TIMEOUT_USEC)
418 return -ETIMEDOUT;
419
420 /* select ULPI phy */
421 writel(0x80000000, USB_PORTSC);
422
423 msleep(100);
424
425 writel(0x0, USB_AHBBURST);
426 writel(0x00, USB_AHBMODE);
427
428 if (pdata->otg_control == OTG_PHY_CONTROL) {
429 val = readl(USB_OTGSC);
430 if (pdata->mode == USB_OTG) {
431 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
432 val |= OTGSC_IDIE | OTGSC_BSVIE;
433 } else if (pdata->mode == USB_PERIPHERAL) {
434 ulpi_val = ULPI_INT_SESS_VALID;
435 val |= OTGSC_BSVIE;
436 }
437 writel(val, USB_OTGSC);
438 ulpi_write(otg, ulpi_val, ULPI_USB_INT_EN_RISE);
439 ulpi_write(otg, ulpi_val, ULPI_USB_INT_EN_FALL);
440 }
441
442 return 0;
443 }
444
445 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
446 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
447
448 #ifdef CONFIG_PM_SLEEP
449 static int msm_otg_suspend(struct msm_otg *motg)
450 {
451 struct otg_transceiver *otg = &motg->otg;
452 struct usb_bus *bus = otg->host;
453 struct msm_otg_platform_data *pdata = motg->pdata;
454 int cnt = 0;
455
456 if (atomic_read(&motg->in_lpm))
457 return 0;
458
459 disable_irq(motg->irq);
460 /*
461 * Chipidea 45-nm PHY suspend sequence:
462 *
463 * Interrupt Latch Register auto-clear feature is not present
464 * in all PHY versions. Latch register is clear on read type.
465 * Clear latch register to avoid spurious wakeup from
466 * low power mode (LPM).
467 *
468 * PHY comparators are disabled when PHY enters into low power
469 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
470 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
471 * PHY comparators. This save significant amount of power.
472 *
473 * PLL is not turned off when PHY enters into low power mode (LPM).
474 * Disable PLL for maximum power savings.
475 */
476
477 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
478 ulpi_read(otg, 0x14);
479 if (pdata->otg_control == OTG_PHY_CONTROL)
480 ulpi_write(otg, 0x01, 0x30);
481 ulpi_write(otg, 0x08, 0x09);
482 }
483
484 /*
485 * PHY may take some time or even fail to enter into low power
486 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
487 * in failure case.
488 */
489 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
490 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
491 if (readl(USB_PORTSC) & PORTSC_PHCD)
492 break;
493 udelay(1);
494 cnt++;
495 }
496
497 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
498 dev_err(otg->dev, "Unable to suspend PHY\n");
499 msm_otg_reset(otg);
500 enable_irq(motg->irq);
501 return -ETIMEDOUT;
502 }
503
504 /*
505 * PHY has capability to generate interrupt asynchronously in low
506 * power mode (LPM). This interrupt is level triggered. So USB IRQ
507 * line must be disabled till async interrupt enable bit is cleared
508 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
509 * block data communication from PHY.
510 */
511 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
512
513 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
514 motg->pdata->otg_control == OTG_PMIC_CONTROL)
515 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
516
517 clk_disable(motg->pclk);
518 clk_disable(motg->clk);
519 if (motg->core_clk)
520 clk_disable(motg->core_clk);
521
522 if (!IS_ERR(motg->pclk_src))
523 clk_disable(motg->pclk_src);
524
525 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
526 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
527 msm_hsusb_ldo_set_mode(0);
528 msm_hsusb_config_vddcx(0);
529 }
530
531 if (device_may_wakeup(otg->dev))
532 enable_irq_wake(motg->irq);
533 if (bus)
534 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
535
536 atomic_set(&motg->in_lpm, 1);
537 enable_irq(motg->irq);
538
539 dev_info(otg->dev, "USB in low power mode\n");
540
541 return 0;
542 }
543
544 static int msm_otg_resume(struct msm_otg *motg)
545 {
546 struct otg_transceiver *otg = &motg->otg;
547 struct usb_bus *bus = otg->host;
548 int cnt = 0;
549 unsigned temp;
550
551 if (!atomic_read(&motg->in_lpm))
552 return 0;
553
554 if (!IS_ERR(motg->pclk_src))
555 clk_enable(motg->pclk_src);
556
557 clk_enable(motg->pclk);
558 clk_enable(motg->clk);
559 if (motg->core_clk)
560 clk_enable(motg->core_clk);
561
562 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
563 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
564 msm_hsusb_ldo_set_mode(1);
565 msm_hsusb_config_vddcx(1);
566 writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
567 }
568
569 temp = readl(USB_USBCMD);
570 temp &= ~ASYNC_INTR_CTRL;
571 temp &= ~ULPI_STP_CTRL;
572 writel(temp, USB_USBCMD);
573
574 /*
575 * PHY comes out of low power mode (LPM) in case of wakeup
576 * from asynchronous interrupt.
577 */
578 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
579 goto skip_phy_resume;
580
581 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
582 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
583 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
584 break;
585 udelay(1);
586 cnt++;
587 }
588
589 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
590 /*
591 * This is a fatal error. Reset the link and
592 * PHY. USB state can not be restored. Re-insertion
593 * of USB cable is the only way to get USB working.
594 */
595 dev_err(otg->dev, "Unable to resume USB."
596 "Re-plugin the cable\n");
597 msm_otg_reset(otg);
598 }
599
600 skip_phy_resume:
601 if (device_may_wakeup(otg->dev))
602 disable_irq_wake(motg->irq);
603 if (bus)
604 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
605
606 atomic_set(&motg->in_lpm, 0);
607
608 if (motg->async_int) {
609 motg->async_int = 0;
610 pm_runtime_put(otg->dev);
611 enable_irq(motg->irq);
612 }
613
614 dev_info(otg->dev, "USB exited from low power mode\n");
615
616 return 0;
617 }
618 #endif
619
620 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
621 {
622 if (motg->cur_power == mA)
623 return;
624
625 /* TODO: Notify PMIC about available current */
626 dev_info(motg->otg.dev, "Avail curr from USB = %u\n", mA);
627 motg->cur_power = mA;
628 }
629
630 static int msm_otg_set_power(struct otg_transceiver *otg, unsigned mA)
631 {
632 struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
633
634 /*
635 * Gadget driver uses set_power method to notify about the
636 * available current based on suspend/configured states.
637 *
638 * IDEV_CHG can be drawn irrespective of suspend/un-configured
639 * states when CDP/ACA is connected.
640 */
641 if (motg->chg_type == USB_SDP_CHARGER)
642 msm_otg_notify_charger(motg, mA);
643
644 return 0;
645 }
646
647 static void msm_otg_start_host(struct otg_transceiver *otg, int on)
648 {
649 struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
650 struct msm_otg_platform_data *pdata = motg->pdata;
651 struct usb_hcd *hcd;
652
653 if (!otg->host)
654 return;
655
656 hcd = bus_to_hcd(otg->host);
657
658 if (on) {
659 dev_dbg(otg->dev, "host on\n");
660
661 if (pdata->vbus_power)
662 pdata->vbus_power(1);
663 /*
664 * Some boards have a switch cotrolled by gpio
665 * to enable/disable internal HUB. Enable internal
666 * HUB before kicking the host.
667 */
668 if (pdata->setup_gpio)
669 pdata->setup_gpio(OTG_STATE_A_HOST);
670 #ifdef CONFIG_USB
671 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
672 #endif
673 } else {
674 dev_dbg(otg->dev, "host off\n");
675
676 #ifdef CONFIG_USB
677 usb_remove_hcd(hcd);
678 #endif
679 if (pdata->setup_gpio)
680 pdata->setup_gpio(OTG_STATE_UNDEFINED);
681 if (pdata->vbus_power)
682 pdata->vbus_power(0);
683 }
684 }
685
686 static int msm_otg_set_host(struct otg_transceiver *otg, struct usb_bus *host)
687 {
688 struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
689 struct usb_hcd *hcd;
690
691 /*
692 * Fail host registration if this board can support
693 * only peripheral configuration.
694 */
695 if (motg->pdata->mode == USB_PERIPHERAL) {
696 dev_info(otg->dev, "Host mode is not supported\n");
697 return -ENODEV;
698 }
699
700 if (!host) {
701 if (otg->state == OTG_STATE_A_HOST) {
702 pm_runtime_get_sync(otg->dev);
703 msm_otg_start_host(otg, 0);
704 otg->host = NULL;
705 otg->state = OTG_STATE_UNDEFINED;
706 schedule_work(&motg->sm_work);
707 } else {
708 otg->host = NULL;
709 }
710
711 return 0;
712 }
713
714 hcd = bus_to_hcd(host);
715 hcd->power_budget = motg->pdata->power_budget;
716
717 otg->host = host;
718 dev_dbg(otg->dev, "host driver registered w/ tranceiver\n");
719
720 /*
721 * Kick the state machine work, if peripheral is not supported
722 * or peripheral is already registered with us.
723 */
724 if (motg->pdata->mode == USB_HOST || otg->gadget) {
725 pm_runtime_get_sync(otg->dev);
726 schedule_work(&motg->sm_work);
727 }
728
729 return 0;
730 }
731
732 static void msm_otg_start_peripheral(struct otg_transceiver *otg, int on)
733 {
734 struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
735 struct msm_otg_platform_data *pdata = motg->pdata;
736
737 if (!otg->gadget)
738 return;
739
740 if (on) {
741 dev_dbg(otg->dev, "gadget on\n");
742 /*
743 * Some boards have a switch cotrolled by gpio
744 * to enable/disable internal HUB. Disable internal
745 * HUB before kicking the gadget.
746 */
747 if (pdata->setup_gpio)
748 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
749 usb_gadget_vbus_connect(otg->gadget);
750 } else {
751 dev_dbg(otg->dev, "gadget off\n");
752 usb_gadget_vbus_disconnect(otg->gadget);
753 if (pdata->setup_gpio)
754 pdata->setup_gpio(OTG_STATE_UNDEFINED);
755 }
756
757 }
758
759 static int msm_otg_set_peripheral(struct otg_transceiver *otg,
760 struct usb_gadget *gadget)
761 {
762 struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
763
764 /*
765 * Fail peripheral registration if this board can support
766 * only host configuration.
767 */
768 if (motg->pdata->mode == USB_HOST) {
769 dev_info(otg->dev, "Peripheral mode is not supported\n");
770 return -ENODEV;
771 }
772
773 if (!gadget) {
774 if (otg->state == OTG_STATE_B_PERIPHERAL) {
775 pm_runtime_get_sync(otg->dev);
776 msm_otg_start_peripheral(otg, 0);
777 otg->gadget = NULL;
778 otg->state = OTG_STATE_UNDEFINED;
779 schedule_work(&motg->sm_work);
780 } else {
781 otg->gadget = NULL;
782 }
783
784 return 0;
785 }
786 otg->gadget = gadget;
787 dev_dbg(otg->dev, "peripheral driver registered w/ tranceiver\n");
788
789 /*
790 * Kick the state machine work, if host is not supported
791 * or host is already registered with us.
792 */
793 if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
794 pm_runtime_get_sync(otg->dev);
795 schedule_work(&motg->sm_work);
796 }
797
798 return 0;
799 }
800
801 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
802 {
803 struct otg_transceiver *otg = &motg->otg;
804 u32 chg_det;
805 bool ret = false;
806
807 switch (motg->pdata->phy_type) {
808 case CI_45NM_INTEGRATED_PHY:
809 chg_det = ulpi_read(otg, 0x34);
810 ret = chg_det & (1 << 4);
811 break;
812 case SNPS_28NM_INTEGRATED_PHY:
813 chg_det = ulpi_read(otg, 0x87);
814 ret = chg_det & 1;
815 break;
816 default:
817 break;
818 }
819 return ret;
820 }
821
822 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
823 {
824 struct otg_transceiver *otg = &motg->otg;
825 u32 chg_det;
826
827 switch (motg->pdata->phy_type) {
828 case CI_45NM_INTEGRATED_PHY:
829 chg_det = ulpi_read(otg, 0x34);
830 /* Turn off charger block */
831 chg_det |= ~(1 << 1);
832 ulpi_write(otg, chg_det, 0x34);
833 udelay(20);
834 /* control chg block via ULPI */
835 chg_det &= ~(1 << 3);
836 ulpi_write(otg, chg_det, 0x34);
837 /* put it in host mode for enabling D- source */
838 chg_det &= ~(1 << 2);
839 ulpi_write(otg, chg_det, 0x34);
840 /* Turn on chg detect block */
841 chg_det &= ~(1 << 1);
842 ulpi_write(otg, chg_det, 0x34);
843 udelay(20);
844 /* enable chg detection */
845 chg_det &= ~(1 << 0);
846 ulpi_write(otg, chg_det, 0x34);
847 break;
848 case SNPS_28NM_INTEGRATED_PHY:
849 /*
850 * Configure DM as current source, DP as current sink
851 * and enable battery charging comparators.
852 */
853 ulpi_write(otg, 0x8, 0x85);
854 ulpi_write(otg, 0x2, 0x85);
855 ulpi_write(otg, 0x1, 0x85);
856 break;
857 default:
858 break;
859 }
860 }
861
862 static bool msm_chg_check_primary_det(struct msm_otg *motg)
863 {
864 struct otg_transceiver *otg = &motg->otg;
865 u32 chg_det;
866 bool ret = false;
867
868 switch (motg->pdata->phy_type) {
869 case CI_45NM_INTEGRATED_PHY:
870 chg_det = ulpi_read(otg, 0x34);
871 ret = chg_det & (1 << 4);
872 break;
873 case SNPS_28NM_INTEGRATED_PHY:
874 chg_det = ulpi_read(otg, 0x87);
875 ret = chg_det & 1;
876 break;
877 default:
878 break;
879 }
880 return ret;
881 }
882
883 static void msm_chg_enable_primary_det(struct msm_otg *motg)
884 {
885 struct otg_transceiver *otg = &motg->otg;
886 u32 chg_det;
887
888 switch (motg->pdata->phy_type) {
889 case CI_45NM_INTEGRATED_PHY:
890 chg_det = ulpi_read(otg, 0x34);
891 /* enable chg detection */
892 chg_det &= ~(1 << 0);
893 ulpi_write(otg, chg_det, 0x34);
894 break;
895 case SNPS_28NM_INTEGRATED_PHY:
896 /*
897 * Configure DP as current source, DM as current sink
898 * and enable battery charging comparators.
899 */
900 ulpi_write(otg, 0x2, 0x85);
901 ulpi_write(otg, 0x1, 0x85);
902 break;
903 default:
904 break;
905 }
906 }
907
908 static bool msm_chg_check_dcd(struct msm_otg *motg)
909 {
910 struct otg_transceiver *otg = &motg->otg;
911 u32 line_state;
912 bool ret = false;
913
914 switch (motg->pdata->phy_type) {
915 case CI_45NM_INTEGRATED_PHY:
916 line_state = ulpi_read(otg, 0x15);
917 ret = !(line_state & 1);
918 break;
919 case SNPS_28NM_INTEGRATED_PHY:
920 line_state = ulpi_read(otg, 0x87);
921 ret = line_state & 2;
922 break;
923 default:
924 break;
925 }
926 return ret;
927 }
928
929 static void msm_chg_disable_dcd(struct msm_otg *motg)
930 {
931 struct otg_transceiver *otg = &motg->otg;
932 u32 chg_det;
933
934 switch (motg->pdata->phy_type) {
935 case CI_45NM_INTEGRATED_PHY:
936 chg_det = ulpi_read(otg, 0x34);
937 chg_det &= ~(1 << 5);
938 ulpi_write(otg, chg_det, 0x34);
939 break;
940 case SNPS_28NM_INTEGRATED_PHY:
941 ulpi_write(otg, 0x10, 0x86);
942 break;
943 default:
944 break;
945 }
946 }
947
948 static void msm_chg_enable_dcd(struct msm_otg *motg)
949 {
950 struct otg_transceiver *otg = &motg->otg;
951 u32 chg_det;
952
953 switch (motg->pdata->phy_type) {
954 case CI_45NM_INTEGRATED_PHY:
955 chg_det = ulpi_read(otg, 0x34);
956 /* Turn on D+ current source */
957 chg_det |= (1 << 5);
958 ulpi_write(otg, chg_det, 0x34);
959 break;
960 case SNPS_28NM_INTEGRATED_PHY:
961 /* Data contact detection enable */
962 ulpi_write(otg, 0x10, 0x85);
963 break;
964 default:
965 break;
966 }
967 }
968
969 static void msm_chg_block_on(struct msm_otg *motg)
970 {
971 struct otg_transceiver *otg = &motg->otg;
972 u32 func_ctrl, chg_det;
973
974 /* put the controller in non-driving mode */
975 func_ctrl = ulpi_read(otg, ULPI_FUNC_CTRL);
976 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
977 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
978 ulpi_write(otg, func_ctrl, ULPI_FUNC_CTRL);
979
980 switch (motg->pdata->phy_type) {
981 case CI_45NM_INTEGRATED_PHY:
982 chg_det = ulpi_read(otg, 0x34);
983 /* control chg block via ULPI */
984 chg_det &= ~(1 << 3);
985 ulpi_write(otg, chg_det, 0x34);
986 /* Turn on chg detect block */
987 chg_det &= ~(1 << 1);
988 ulpi_write(otg, chg_det, 0x34);
989 udelay(20);
990 break;
991 case SNPS_28NM_INTEGRATED_PHY:
992 /* Clear charger detecting control bits */
993 ulpi_write(otg, 0x3F, 0x86);
994 /* Clear alt interrupt latch and enable bits */
995 ulpi_write(otg, 0x1F, 0x92);
996 ulpi_write(otg, 0x1F, 0x95);
997 udelay(100);
998 break;
999 default:
1000 break;
1001 }
1002 }
1003
1004 static void msm_chg_block_off(struct msm_otg *motg)
1005 {
1006 struct otg_transceiver *otg = &motg->otg;
1007 u32 func_ctrl, chg_det;
1008
1009 switch (motg->pdata->phy_type) {
1010 case CI_45NM_INTEGRATED_PHY:
1011 chg_det = ulpi_read(otg, 0x34);
1012 /* Turn off charger block */
1013 chg_det |= ~(1 << 1);
1014 ulpi_write(otg, chg_det, 0x34);
1015 break;
1016 case SNPS_28NM_INTEGRATED_PHY:
1017 /* Clear charger detecting control bits */
1018 ulpi_write(otg, 0x3F, 0x86);
1019 /* Clear alt interrupt latch and enable bits */
1020 ulpi_write(otg, 0x1F, 0x92);
1021 ulpi_write(otg, 0x1F, 0x95);
1022 break;
1023 default:
1024 break;
1025 }
1026
1027 /* put the controller in normal mode */
1028 func_ctrl = ulpi_read(otg, ULPI_FUNC_CTRL);
1029 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1030 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1031 ulpi_write(otg, func_ctrl, ULPI_FUNC_CTRL);
1032 }
1033
1034 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1035 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1036 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1037 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1038 static void msm_chg_detect_work(struct work_struct *w)
1039 {
1040 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1041 struct otg_transceiver *otg = &motg->otg;
1042 bool is_dcd, tmout, vout;
1043 unsigned long delay;
1044
1045 dev_dbg(otg->dev, "chg detection work\n");
1046 switch (motg->chg_state) {
1047 case USB_CHG_STATE_UNDEFINED:
1048 pm_runtime_get_sync(otg->dev);
1049 msm_chg_block_on(motg);
1050 msm_chg_enable_dcd(motg);
1051 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1052 motg->dcd_retries = 0;
1053 delay = MSM_CHG_DCD_POLL_TIME;
1054 break;
1055 case USB_CHG_STATE_WAIT_FOR_DCD:
1056 is_dcd = msm_chg_check_dcd(motg);
1057 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1058 if (is_dcd || tmout) {
1059 msm_chg_disable_dcd(motg);
1060 msm_chg_enable_primary_det(motg);
1061 delay = MSM_CHG_PRIMARY_DET_TIME;
1062 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1063 } else {
1064 delay = MSM_CHG_DCD_POLL_TIME;
1065 }
1066 break;
1067 case USB_CHG_STATE_DCD_DONE:
1068 vout = msm_chg_check_primary_det(motg);
1069 if (vout) {
1070 msm_chg_enable_secondary_det(motg);
1071 delay = MSM_CHG_SECONDARY_DET_TIME;
1072 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1073 } else {
1074 motg->chg_type = USB_SDP_CHARGER;
1075 motg->chg_state = USB_CHG_STATE_DETECTED;
1076 delay = 0;
1077 }
1078 break;
1079 case USB_CHG_STATE_PRIMARY_DONE:
1080 vout = msm_chg_check_secondary_det(motg);
1081 if (vout)
1082 motg->chg_type = USB_DCP_CHARGER;
1083 else
1084 motg->chg_type = USB_CDP_CHARGER;
1085 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1086 /* fall through */
1087 case USB_CHG_STATE_SECONDARY_DONE:
1088 motg->chg_state = USB_CHG_STATE_DETECTED;
1089 case USB_CHG_STATE_DETECTED:
1090 msm_chg_block_off(motg);
1091 dev_dbg(otg->dev, "charger = %d\n", motg->chg_type);
1092 schedule_work(&motg->sm_work);
1093 return;
1094 default:
1095 return;
1096 }
1097
1098 schedule_delayed_work(&motg->chg_work, delay);
1099 }
1100
1101 /*
1102 * We support OTG, Peripheral only and Host only configurations. In case
1103 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1104 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1105 * enabled when switch is controlled by user and default mode is supplied
1106 * by board file, which can be changed by userspace later.
1107 */
1108 static void msm_otg_init_sm(struct msm_otg *motg)
1109 {
1110 struct msm_otg_platform_data *pdata = motg->pdata;
1111 u32 otgsc = readl(USB_OTGSC);
1112
1113 switch (pdata->mode) {
1114 case USB_OTG:
1115 if (pdata->otg_control == OTG_PHY_CONTROL) {
1116 if (otgsc & OTGSC_ID)
1117 set_bit(ID, &motg->inputs);
1118 else
1119 clear_bit(ID, &motg->inputs);
1120
1121 if (otgsc & OTGSC_BSV)
1122 set_bit(B_SESS_VLD, &motg->inputs);
1123 else
1124 clear_bit(B_SESS_VLD, &motg->inputs);
1125 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1126 if (pdata->default_mode == USB_HOST) {
1127 clear_bit(ID, &motg->inputs);
1128 } else if (pdata->default_mode == USB_PERIPHERAL) {
1129 set_bit(ID, &motg->inputs);
1130 set_bit(B_SESS_VLD, &motg->inputs);
1131 } else {
1132 set_bit(ID, &motg->inputs);
1133 clear_bit(B_SESS_VLD, &motg->inputs);
1134 }
1135 }
1136 break;
1137 case USB_HOST:
1138 clear_bit(ID, &motg->inputs);
1139 break;
1140 case USB_PERIPHERAL:
1141 set_bit(ID, &motg->inputs);
1142 if (otgsc & OTGSC_BSV)
1143 set_bit(B_SESS_VLD, &motg->inputs);
1144 else
1145 clear_bit(B_SESS_VLD, &motg->inputs);
1146 break;
1147 default:
1148 break;
1149 }
1150 }
1151
1152 static void msm_otg_sm_work(struct work_struct *w)
1153 {
1154 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1155 struct otg_transceiver *otg = &motg->otg;
1156
1157 switch (otg->state) {
1158 case OTG_STATE_UNDEFINED:
1159 dev_dbg(otg->dev, "OTG_STATE_UNDEFINED state\n");
1160 msm_otg_reset(otg);
1161 msm_otg_init_sm(motg);
1162 otg->state = OTG_STATE_B_IDLE;
1163 /* FALL THROUGH */
1164 case OTG_STATE_B_IDLE:
1165 dev_dbg(otg->dev, "OTG_STATE_B_IDLE state\n");
1166 if (!test_bit(ID, &motg->inputs) && otg->host) {
1167 /* disable BSV bit */
1168 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1169 msm_otg_start_host(otg, 1);
1170 otg->state = OTG_STATE_A_HOST;
1171 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1172 switch (motg->chg_state) {
1173 case USB_CHG_STATE_UNDEFINED:
1174 msm_chg_detect_work(&motg->chg_work.work);
1175 break;
1176 case USB_CHG_STATE_DETECTED:
1177 switch (motg->chg_type) {
1178 case USB_DCP_CHARGER:
1179 msm_otg_notify_charger(motg,
1180 IDEV_CHG_MAX);
1181 break;
1182 case USB_CDP_CHARGER:
1183 msm_otg_notify_charger(motg,
1184 IDEV_CHG_MAX);
1185 msm_otg_start_peripheral(otg, 1);
1186 otg->state = OTG_STATE_B_PERIPHERAL;
1187 break;
1188 case USB_SDP_CHARGER:
1189 msm_otg_notify_charger(motg, IUNIT);
1190 msm_otg_start_peripheral(otg, 1);
1191 otg->state = OTG_STATE_B_PERIPHERAL;
1192 break;
1193 default:
1194 break;
1195 }
1196 break;
1197 default:
1198 break;
1199 }
1200 } else {
1201 /*
1202 * If charger detection work is pending, decrement
1203 * the pm usage counter to balance with the one that
1204 * is incremented in charger detection work.
1205 */
1206 if (cancel_delayed_work_sync(&motg->chg_work)) {
1207 pm_runtime_put_sync(otg->dev);
1208 msm_otg_reset(otg);
1209 }
1210 msm_otg_notify_charger(motg, 0);
1211 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1212 motg->chg_type = USB_INVALID_CHARGER;
1213 }
1214 pm_runtime_put_sync(otg->dev);
1215 break;
1216 case OTG_STATE_B_PERIPHERAL:
1217 dev_dbg(otg->dev, "OTG_STATE_B_PERIPHERAL state\n");
1218 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1219 !test_bit(ID, &motg->inputs)) {
1220 msm_otg_notify_charger(motg, 0);
1221 msm_otg_start_peripheral(otg, 0);
1222 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1223 motg->chg_type = USB_INVALID_CHARGER;
1224 otg->state = OTG_STATE_B_IDLE;
1225 msm_otg_reset(otg);
1226 schedule_work(w);
1227 }
1228 break;
1229 case OTG_STATE_A_HOST:
1230 dev_dbg(otg->dev, "OTG_STATE_A_HOST state\n");
1231 if (test_bit(ID, &motg->inputs)) {
1232 msm_otg_start_host(otg, 0);
1233 otg->state = OTG_STATE_B_IDLE;
1234 msm_otg_reset(otg);
1235 schedule_work(w);
1236 }
1237 break;
1238 default:
1239 break;
1240 }
1241 }
1242
1243 static irqreturn_t msm_otg_irq(int irq, void *data)
1244 {
1245 struct msm_otg *motg = data;
1246 struct otg_transceiver *otg = &motg->otg;
1247 u32 otgsc = 0;
1248
1249 if (atomic_read(&motg->in_lpm)) {
1250 disable_irq_nosync(irq);
1251 motg->async_int = 1;
1252 pm_runtime_get(otg->dev);
1253 return IRQ_HANDLED;
1254 }
1255
1256 otgsc = readl(USB_OTGSC);
1257 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1258 return IRQ_NONE;
1259
1260 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1261 if (otgsc & OTGSC_ID)
1262 set_bit(ID, &motg->inputs);
1263 else
1264 clear_bit(ID, &motg->inputs);
1265 dev_dbg(otg->dev, "ID set/clear\n");
1266 pm_runtime_get_noresume(otg->dev);
1267 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1268 if (otgsc & OTGSC_BSV)
1269 set_bit(B_SESS_VLD, &motg->inputs);
1270 else
1271 clear_bit(B_SESS_VLD, &motg->inputs);
1272 dev_dbg(otg->dev, "BSV set/clear\n");
1273 pm_runtime_get_noresume(otg->dev);
1274 }
1275
1276 writel(otgsc, USB_OTGSC);
1277 schedule_work(&motg->sm_work);
1278 return IRQ_HANDLED;
1279 }
1280
1281 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1282 {
1283 struct msm_otg *motg = s->private;
1284 struct otg_transceiver *otg = &motg->otg;
1285
1286 switch (otg->state) {
1287 case OTG_STATE_A_HOST:
1288 seq_printf(s, "host\n");
1289 break;
1290 case OTG_STATE_B_PERIPHERAL:
1291 seq_printf(s, "peripheral\n");
1292 break;
1293 default:
1294 seq_printf(s, "none\n");
1295 break;
1296 }
1297
1298 return 0;
1299 }
1300
1301 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1302 {
1303 return single_open(file, msm_otg_mode_show, inode->i_private);
1304 }
1305
1306 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1307 size_t count, loff_t *ppos)
1308 {
1309 struct seq_file *s = file->private_data;
1310 struct msm_otg *motg = s->private;
1311 char buf[16];
1312 struct otg_transceiver *otg = &motg->otg;
1313 int status = count;
1314 enum usb_mode_type req_mode;
1315
1316 memset(buf, 0x00, sizeof(buf));
1317
1318 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1319 status = -EFAULT;
1320 goto out;
1321 }
1322
1323 if (!strncmp(buf, "host", 4)) {
1324 req_mode = USB_HOST;
1325 } else if (!strncmp(buf, "peripheral", 10)) {
1326 req_mode = USB_PERIPHERAL;
1327 } else if (!strncmp(buf, "none", 4)) {
1328 req_mode = USB_NONE;
1329 } else {
1330 status = -EINVAL;
1331 goto out;
1332 }
1333
1334 switch (req_mode) {
1335 case USB_NONE:
1336 switch (otg->state) {
1337 case OTG_STATE_A_HOST:
1338 case OTG_STATE_B_PERIPHERAL:
1339 set_bit(ID, &motg->inputs);
1340 clear_bit(B_SESS_VLD, &motg->inputs);
1341 break;
1342 default:
1343 goto out;
1344 }
1345 break;
1346 case USB_PERIPHERAL:
1347 switch (otg->state) {
1348 case OTG_STATE_B_IDLE:
1349 case OTG_STATE_A_HOST:
1350 set_bit(ID, &motg->inputs);
1351 set_bit(B_SESS_VLD, &motg->inputs);
1352 break;
1353 default:
1354 goto out;
1355 }
1356 break;
1357 case USB_HOST:
1358 switch (otg->state) {
1359 case OTG_STATE_B_IDLE:
1360 case OTG_STATE_B_PERIPHERAL:
1361 clear_bit(ID, &motg->inputs);
1362 break;
1363 default:
1364 goto out;
1365 }
1366 break;
1367 default:
1368 goto out;
1369 }
1370
1371 pm_runtime_get_sync(otg->dev);
1372 schedule_work(&motg->sm_work);
1373 out:
1374 return status;
1375 }
1376
1377 const struct file_operations msm_otg_mode_fops = {
1378 .open = msm_otg_mode_open,
1379 .read = seq_read,
1380 .write = msm_otg_mode_write,
1381 .llseek = seq_lseek,
1382 .release = single_release,
1383 };
1384
1385 static struct dentry *msm_otg_dbg_root;
1386 static struct dentry *msm_otg_dbg_mode;
1387
1388 static int msm_otg_debugfs_init(struct msm_otg *motg)
1389 {
1390 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1391
1392 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1393 return -ENODEV;
1394
1395 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1396 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1397 if (!msm_otg_dbg_mode) {
1398 debugfs_remove(msm_otg_dbg_root);
1399 msm_otg_dbg_root = NULL;
1400 return -ENODEV;
1401 }
1402
1403 return 0;
1404 }
1405
1406 static void msm_otg_debugfs_cleanup(void)
1407 {
1408 debugfs_remove(msm_otg_dbg_mode);
1409 debugfs_remove(msm_otg_dbg_root);
1410 }
1411
1412 static int __init msm_otg_probe(struct platform_device *pdev)
1413 {
1414 int ret = 0;
1415 struct resource *res;
1416 struct msm_otg *motg;
1417 struct otg_transceiver *otg;
1418
1419 dev_info(&pdev->dev, "msm_otg probe\n");
1420 if (!pdev->dev.platform_data) {
1421 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
1422 return -ENODEV;
1423 }
1424
1425 motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL);
1426 if (!motg) {
1427 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1428 return -ENOMEM;
1429 }
1430
1431 motg->pdata = pdev->dev.platform_data;
1432 otg = &motg->otg;
1433 otg->dev = &pdev->dev;
1434
1435 motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk");
1436 if (IS_ERR(motg->phy_reset_clk)) {
1437 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1438 ret = PTR_ERR(motg->phy_reset_clk);
1439 goto free_motg;
1440 }
1441
1442 motg->clk = clk_get(&pdev->dev, "usb_hs_clk");
1443 if (IS_ERR(motg->clk)) {
1444 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1445 ret = PTR_ERR(motg->clk);
1446 goto put_phy_reset_clk;
1447 }
1448 clk_set_rate(motg->clk, 60000000);
1449
1450 /*
1451 * If USB Core is running its protocol engine based on CORE CLK,
1452 * CORE CLK must be running at >55Mhz for correct HSUSB
1453 * operation and USB core cannot tolerate frequency changes on
1454 * CORE CLK. For such USB cores, vote for maximum clk frequency
1455 * on pclk source
1456 */
1457 if (motg->pdata->pclk_src_name) {
1458 motg->pclk_src = clk_get(&pdev->dev,
1459 motg->pdata->pclk_src_name);
1460 if (IS_ERR(motg->pclk_src))
1461 goto put_clk;
1462 clk_set_rate(motg->pclk_src, INT_MAX);
1463 clk_enable(motg->pclk_src);
1464 } else
1465 motg->pclk_src = ERR_PTR(-ENOENT);
1466
1467
1468 motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
1469 if (IS_ERR(motg->pclk)) {
1470 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1471 ret = PTR_ERR(motg->pclk);
1472 goto put_pclk_src;
1473 }
1474
1475 /*
1476 * USB core clock is not present on all MSM chips. This
1477 * clock is introduced to remove the dependency on AXI
1478 * bus frequency.
1479 */
1480 motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk");
1481 if (IS_ERR(motg->core_clk))
1482 motg->core_clk = NULL;
1483
1484 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1485 if (!res) {
1486 dev_err(&pdev->dev, "failed to get platform resource mem\n");
1487 ret = -ENODEV;
1488 goto put_core_clk;
1489 }
1490
1491 motg->regs = ioremap(res->start, resource_size(res));
1492 if (!motg->regs) {
1493 dev_err(&pdev->dev, "ioremap failed\n");
1494 ret = -ENOMEM;
1495 goto put_core_clk;
1496 }
1497 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1498
1499 motg->irq = platform_get_irq(pdev, 0);
1500 if (!motg->irq) {
1501 dev_err(&pdev->dev, "platform_get_irq failed\n");
1502 ret = -ENODEV;
1503 goto free_regs;
1504 }
1505
1506 clk_enable(motg->clk);
1507 clk_enable(motg->pclk);
1508
1509 ret = msm_hsusb_init_vddcx(motg, 1);
1510 if (ret) {
1511 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1512 goto free_regs;
1513 }
1514
1515 ret = msm_hsusb_ldo_init(motg, 1);
1516 if (ret) {
1517 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1518 goto vddcx_exit;
1519 }
1520 ret = msm_hsusb_ldo_set_mode(1);
1521 if (ret) {
1522 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1523 goto ldo_exit;
1524 }
1525
1526 if (motg->core_clk)
1527 clk_enable(motg->core_clk);
1528
1529 writel(0, USB_USBINTR);
1530 writel(0, USB_OTGSC);
1531
1532 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1533 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1534 ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED,
1535 "msm_otg", motg);
1536 if (ret) {
1537 dev_err(&pdev->dev, "request irq failed\n");
1538 goto disable_clks;
1539 }
1540
1541 otg->init = msm_otg_reset;
1542 otg->set_host = msm_otg_set_host;
1543 otg->set_peripheral = msm_otg_set_peripheral;
1544 otg->set_power = msm_otg_set_power;
1545
1546 otg->io_ops = &msm_otg_io_ops;
1547
1548 ret = otg_set_transceiver(&motg->otg);
1549 if (ret) {
1550 dev_err(&pdev->dev, "otg_set_transceiver failed\n");
1551 goto free_irq;
1552 }
1553
1554 platform_set_drvdata(pdev, motg);
1555 device_init_wakeup(&pdev->dev, 1);
1556
1557 if (motg->pdata->mode == USB_OTG &&
1558 motg->pdata->otg_control == OTG_USER_CONTROL) {
1559 ret = msm_otg_debugfs_init(motg);
1560 if (ret)
1561 dev_dbg(&pdev->dev, "mode debugfs file is"
1562 "not available\n");
1563 }
1564
1565 pm_runtime_set_active(&pdev->dev);
1566 pm_runtime_enable(&pdev->dev);
1567
1568 return 0;
1569 free_irq:
1570 free_irq(motg->irq, motg);
1571 disable_clks:
1572 clk_disable(motg->pclk);
1573 clk_disable(motg->clk);
1574 ldo_exit:
1575 msm_hsusb_ldo_init(motg, 0);
1576 vddcx_exit:
1577 msm_hsusb_init_vddcx(motg, 0);
1578 free_regs:
1579 iounmap(motg->regs);
1580 put_core_clk:
1581 if (motg->core_clk)
1582 clk_put(motg->core_clk);
1583 clk_put(motg->pclk);
1584 put_pclk_src:
1585 if (!IS_ERR(motg->pclk_src)) {
1586 clk_disable(motg->pclk_src);
1587 clk_put(motg->pclk_src);
1588 }
1589 put_clk:
1590 clk_put(motg->clk);
1591 put_phy_reset_clk:
1592 clk_put(motg->phy_reset_clk);
1593 free_motg:
1594 kfree(motg);
1595 return ret;
1596 }
1597
1598 static int __devexit msm_otg_remove(struct platform_device *pdev)
1599 {
1600 struct msm_otg *motg = platform_get_drvdata(pdev);
1601 struct otg_transceiver *otg = &motg->otg;
1602 int cnt = 0;
1603
1604 if (otg->host || otg->gadget)
1605 return -EBUSY;
1606
1607 msm_otg_debugfs_cleanup();
1608 cancel_delayed_work_sync(&motg->chg_work);
1609 cancel_work_sync(&motg->sm_work);
1610
1611 pm_runtime_resume(&pdev->dev);
1612
1613 device_init_wakeup(&pdev->dev, 0);
1614 pm_runtime_disable(&pdev->dev);
1615
1616 otg_set_transceiver(NULL);
1617 free_irq(motg->irq, motg);
1618
1619 /*
1620 * Put PHY in low power mode.
1621 */
1622 ulpi_read(otg, 0x14);
1623 ulpi_write(otg, 0x08, 0x09);
1624
1625 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1626 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1627 if (readl(USB_PORTSC) & PORTSC_PHCD)
1628 break;
1629 udelay(1);
1630 cnt++;
1631 }
1632 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1633 dev_err(otg->dev, "Unable to suspend PHY\n");
1634
1635 clk_disable(motg->pclk);
1636 clk_disable(motg->clk);
1637 if (motg->core_clk)
1638 clk_disable(motg->core_clk);
1639 if (!IS_ERR(motg->pclk_src)) {
1640 clk_disable(motg->pclk_src);
1641 clk_put(motg->pclk_src);
1642 }
1643 msm_hsusb_ldo_init(motg, 0);
1644
1645 iounmap(motg->regs);
1646 pm_runtime_set_suspended(&pdev->dev);
1647
1648 clk_put(motg->phy_reset_clk);
1649 clk_put(motg->pclk);
1650 clk_put(motg->clk);
1651 if (motg->core_clk)
1652 clk_put(motg->core_clk);
1653
1654 kfree(motg);
1655
1656 return 0;
1657 }
1658
1659 #ifdef CONFIG_PM_RUNTIME
1660 static int msm_otg_runtime_idle(struct device *dev)
1661 {
1662 struct msm_otg *motg = dev_get_drvdata(dev);
1663 struct otg_transceiver *otg = &motg->otg;
1664
1665 dev_dbg(dev, "OTG runtime idle\n");
1666
1667 /*
1668 * It is observed some times that a spurious interrupt
1669 * comes when PHY is put into LPM immediately after PHY reset.
1670 * This 1 sec delay also prevents entering into LPM immediately
1671 * after asynchronous interrupt.
1672 */
1673 if (otg->state != OTG_STATE_UNDEFINED)
1674 pm_schedule_suspend(dev, 1000);
1675
1676 return -EAGAIN;
1677 }
1678
1679 static int msm_otg_runtime_suspend(struct device *dev)
1680 {
1681 struct msm_otg *motg = dev_get_drvdata(dev);
1682
1683 dev_dbg(dev, "OTG runtime suspend\n");
1684 return msm_otg_suspend(motg);
1685 }
1686
1687 static int msm_otg_runtime_resume(struct device *dev)
1688 {
1689 struct msm_otg *motg = dev_get_drvdata(dev);
1690
1691 dev_dbg(dev, "OTG runtime resume\n");
1692 return msm_otg_resume(motg);
1693 }
1694 #endif
1695
1696 #ifdef CONFIG_PM_SLEEP
1697 static int msm_otg_pm_suspend(struct device *dev)
1698 {
1699 struct msm_otg *motg = dev_get_drvdata(dev);
1700
1701 dev_dbg(dev, "OTG PM suspend\n");
1702 return msm_otg_suspend(motg);
1703 }
1704
1705 static int msm_otg_pm_resume(struct device *dev)
1706 {
1707 struct msm_otg *motg = dev_get_drvdata(dev);
1708 int ret;
1709
1710 dev_dbg(dev, "OTG PM resume\n");
1711
1712 ret = msm_otg_resume(motg);
1713 if (ret)
1714 return ret;
1715
1716 /*
1717 * Runtime PM Documentation recommends bringing the
1718 * device to full powered state upon resume.
1719 */
1720 pm_runtime_disable(dev);
1721 pm_runtime_set_active(dev);
1722 pm_runtime_enable(dev);
1723
1724 return 0;
1725 }
1726 #endif
1727
1728 #ifdef CONFIG_PM
1729 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1730 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1731 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1732 msm_otg_runtime_idle)
1733 };
1734 #endif
1735
1736 static struct platform_driver msm_otg_driver = {
1737 .remove = __devexit_p(msm_otg_remove),
1738 .driver = {
1739 .name = DRIVER_NAME,
1740 .owner = THIS_MODULE,
1741 #ifdef CONFIG_PM
1742 .pm = &msm_otg_dev_pm_ops,
1743 #endif
1744 },
1745 };
1746
1747 static int __init msm_otg_init(void)
1748 {
1749 return platform_driver_probe(&msm_otg_driver, msm_otg_probe);
1750 }
1751
1752 static void __exit msm_otg_exit(void)
1753 {
1754 platform_driver_unregister(&msm_otg_driver);
1755 }
1756
1757 module_init(msm_otg_init);
1758 module_exit(msm_otg_exit);
1759
1760 MODULE_LICENSE("GPL v2");
1761 MODULE_DESCRIPTION("MSM USB transceiver driver");