include/asm-ppc/dma.h

   1 /*
   2  * include/asm-ppc/dma.h: Defines for using and allocating dma channels.
   3  * Written by Hennus Bergman, 1992.
   4  * High DMA channel support & info by Hannu Savolainen
   5  * and John Boyd, Nov. 1992.
   6  * Changes for ppc sound by Christoph Nadig
   7  */
   8
   9 #ifdef __KERNEL__
  10
  11 #include <linux/config.h>
  12 #include <asm/io.h>
  13 #include <linux/spinlock.h>
  14 #include <asm/system.h>
  15
  16 /*
  17  * Note: Adapted for PowerPC by Gary Thomas
  18  * Modified by Cort Dougan <cort@cs.nmt.edu>
  19  *
  20  * None of this really applies for Power Macintoshes.  There is
  21  * basically just enough here to get kernel/dma.c to compile.
  22  *
  23  * There may be some comments or restrictions made here which are
  24  * not valid for the PReP platform.  Take what you read
  25  * with a grain of salt.
  26  */
  27
  28 #ifndef _ASM_DMA_H
  29 #define _ASM_DMA_H
  30
  31 #ifndef MAX_DMA_CHANNELS
  32 #define MAX_DMA_CHANNELS        8
  33 #endif
  34
  35 /* The maximum address that we can perform a DMA transfer to on this platform */
  36 /* Doesn't really apply... */
  37 #define MAX_DMA_ADDRESS         0xFFFFFFFF
  38
  39 /* in arch/ppc/kernel/setup.c -- Cort */
  40 extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
  41 extern unsigned long ISA_DMA_THRESHOLD;
  42
  43 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  44 #define dma_outb        outb_p
  45 #else
  46 #define dma_outb        outb
  47 #endif
  48
  49 #define dma_inb         inb
  50
  51 /*
  52  * NOTES about DMA transfers:
  53  *
  54  *  controller 1: channels 0-3, byte operations, ports 00-1F
  55  *  controller 2: channels 4-7, word operations, ports C0-DF
  56  *
  57  *  - ALL registers are 8 bits only, regardless of transfer size
  58  *  - channel 4 is not used - cascades 1 into 2.
  59  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  60  *  - channels 5-7 are word - addresses/counts are for physical words
  61  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  62  *  - transfer count loaded to registers is 1 less than actual count
  63  *  - controller 2 offsets are all even (2x offsets for controller 1)
  64  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  65  *  - page registers for 0-3 use bit 0, represent 64K pages
  66  *
  67  * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
  68  * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
  69  * Note that addresses loaded into registers must be _physical_ addresses,
  70  * not logical addresses (which may differ if paging is active).
  71  *
  72  *  Address mapping for channels 0-3:
  73  *
  74  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  75  *    |  ...  |   |  ... |   |  ... |
  76  *    |  ...  |   |  ... |   |  ... |
  77  *    |  ...  |   |  ... |   |  ... |
  78  *   P7  ...  P0  A7 ... A0  A7 ... A0
  79  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  80  *
  81  *  Address mapping for channels 5-7:
  82  *
  83  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  84  *    |  ...  |   \   \   ... \  \  \  ... \  \
  85  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  86  *    |  ...  |     \   \   ... \  \  \  ... \
  87  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  88  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  89  *
  90  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  91  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  92  * the hardware level, so odd-byte transfers aren't possible).
  93  *
  94  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  95  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  96  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  97  *
  98  */
  99
 100 /* see prep_setup_arch() for detailed informations */
 101 #if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_PPC_PREP)
 102 extern long ppc_cs4232_dma, ppc_cs4232_dma2;
 103 #define SND_DMA1 ppc_cs4232_dma
 104 #define SND_DMA2 ppc_cs4232_dma2
 105 #else
 106 #define SND_DMA1 -1
 107 #define SND_DMA2 -1
 108 #endif
 109
 110 /* 8237 DMA controllers */
 111 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
 112 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
 113
 114 /* DMA controller registers */
 115 #define DMA1_CMD_REG            0x08    /* command register (w) */
 116 #define DMA1_STAT_REG           0x08    /* status register (r) */
 117 #define DMA1_REQ_REG            0x09    /* request register (w) */
 118 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
 119 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
 120 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
 121 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
 122 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
 123 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
 124 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 125
 126 #define DMA2_CMD_REG            0xD0    /* command register (w) */
 127 #define DMA2_STAT_REG           0xD0    /* status register (r) */
 128 #define DMA2_REQ_REG            0xD2    /* request register (w) */
 129 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 130 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
 131 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 132 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 133 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 134 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 135 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 136
 137 #define DMA_ADDR_0              0x00    /* DMA address registers */
 138 #define DMA_ADDR_1              0x02
 139 #define DMA_ADDR_2              0x04
 140 #define DMA_ADDR_3              0x06
 141 #define DMA_ADDR_4              0xC0
 142 #define DMA_ADDR_5              0xC4
 143 #define DMA_ADDR_6              0xC8
 144 #define DMA_ADDR_7              0xCC
 145
 146 #define DMA_CNT_0               0x01    /* DMA count registers */
 147 #define DMA_CNT_1               0x03
 148 #define DMA_CNT_2               0x05
 149 #define DMA_CNT_3               0x07
 150 #define DMA_CNT_4               0xC2
 151 #define DMA_CNT_5               0xC6
 152 #define DMA_CNT_6               0xCA
 153 #define DMA_CNT_7               0xCE
 154
 155 #define DMA_LO_PAGE_0           0x87    /* DMA page registers */
 156 #define DMA_LO_PAGE_1           0x83
 157 #define DMA_LO_PAGE_2           0x81
 158 #define DMA_LO_PAGE_3           0x82
 159 #define DMA_LO_PAGE_5           0x8B
 160 #define DMA_LO_PAGE_6           0x89
 161 #define DMA_LO_PAGE_7           0x8A
 162
 163 #define DMA_HI_PAGE_0           0x487   /* DMA page registers */
 164 #define DMA_HI_PAGE_1           0x483
 165 #define DMA_HI_PAGE_2           0x481
 166 #define DMA_HI_PAGE_3           0x482
 167 #define DMA_HI_PAGE_5           0x48B
 168 #define DMA_HI_PAGE_6           0x489
 169 #define DMA_HI_PAGE_7           0x48A
 170
 171 #define DMA1_EXT_REG            0x40B
 172 #define DMA2_EXT_REG            0x4D6
 173
 174 #define DMA_MODE_CASCADE        0xC0    /* pass thru DREQ->HRQ, DACK<-HLDA only */
 175 #define DMA_AUTOINIT            0x10
 176
 177 extern spinlock_t dma_spin_lock;
 178
 179 static __inline__ unsigned long claim_dma_lock(void)
 180 {
 181         unsigned long flags;
 182         spin_lock_irqsave(&dma_spin_lock, flags);
 183         return flags;
 184 }
 185
 186 static __inline__ void release_dma_lock(unsigned long flags)
 187 {
 188         spin_unlock_irqrestore(&dma_spin_lock, flags);
 189 }
 190
 191 /* enable/disable a specific DMA channel */
 192 static __inline__ void enable_dma(unsigned int dmanr)
 193 {
 194         unsigned char ucDmaCmd = 0x00;
 195
 196         if (dmanr != 4) {
 197                 dma_outb(0, DMA2_MASK_REG);     /* This may not be enabled */
 198                 dma_outb(ucDmaCmd, DMA2_CMD_REG);       /* Enable group */
 199         }
 200         if (dmanr <= 3) {
 201                 dma_outb(dmanr, DMA1_MASK_REG);
 202                 dma_outb(ucDmaCmd, DMA1_CMD_REG);       /* Enable group */
 203         } else
 204                 dma_outb(dmanr & 3, DMA2_MASK_REG);
 205 }
 206
 207 static __inline__ void disable_dma(unsigned int dmanr)
 208 {
 209         if (dmanr <= 3)
 210                 dma_outb(dmanr | 4, DMA1_MASK_REG);
 211         else
 212                 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
 213 }
 214
 215 /* Clear the 'DMA Pointer Flip Flop'.
 216  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 217  * Use this once to initialize the FF to a known state.
 218  * After that, keep track of it. :-)
 219  * --- In order to do that, the DMA routines below should ---
 220  * --- only be used while interrupts are disabled! ---
 221  */
 222 static __inline__ void clear_dma_ff(unsigned int dmanr)
 223 {
 224         if (dmanr <= 3)
 225                 dma_outb(0, DMA1_CLEAR_FF_REG);
 226         else
 227                 dma_outb(0, DMA2_CLEAR_FF_REG);
 228 }
 229
 230 /* set mode (above) for a specific DMA channel */
 231 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 232 {
 233         if (dmanr <= 3)
 234                 dma_outb(mode | dmanr, DMA1_MODE_REG);
 235         else
 236                 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
 237 }
 238
 239 /* Set only the page register bits of the transfer address.
 240  * This is used for successive transfers when we know the contents of
 241  * the lower 16 bits of the DMA current address register, but a 64k boundary
 242  * may have been crossed.
 243  */
 244 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
 245 {
 246         switch (dmanr) {
 247         case 0:
 248                 dma_outb(pagenr, DMA_LO_PAGE_0);
 249                 dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
 250                 break;
 251         case 1:
 252                 dma_outb(pagenr, DMA_LO_PAGE_1);
 253                 dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
 254                 break;
 255         case 2:
 256                 dma_outb(pagenr, DMA_LO_PAGE_2);
 257                 dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
 258                 break;
 259         case 3:
 260                 dma_outb(pagenr, DMA_LO_PAGE_3);
 261                 dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
 262                 break;
 263         case 5:
 264                 if (SND_DMA1 == 5 || SND_DMA2 == 5)
 265                         dma_outb(pagenr, DMA_LO_PAGE_5);
 266                 else
 267                         dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
 268                 dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
 269                 break;
 270         case 6:
 271                 if (SND_DMA1 == 6 || SND_DMA2 == 6)
 272                         dma_outb(pagenr, DMA_LO_PAGE_6);
 273                 else
 274                         dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
 275                 dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
 276                 break;
 277         case 7:
 278                 if (SND_DMA1 == 7 || SND_DMA2 == 7)
 279                         dma_outb(pagenr, DMA_LO_PAGE_7);
 280                 else
 281                         dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
 282                 dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
 283                 break;
 284         }
 285 }
 286
 287 /* Set transfer address & page bits for specific DMA channel.
 288  * Assumes dma flipflop is clear.
 289  */
 290 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
 291 {
 292         if (dmanr <= 3) {
 293                 dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
 294                 dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
 295         } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
 296                 dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
 297                 dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
 298                 dma_outb((dmanr & 3), DMA2_EXT_REG);
 299         } else {
 300                 dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
 301                 dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
 302         }
 303         set_dma_page(dmanr, phys >> 16);
 304 }
 305
 306 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 307  * a specific DMA channel.
 308  * You must ensure the parameters are valid.
 309  * NOTE: from a manual: "the number of transfers is one more
 310  * than the initial word count"! This is taken into account.
 311  * Assumes dma flip-flop is clear.
 312  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 313  */
 314 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 315 {
 316         count--;
 317         if (dmanr <= 3) {
 318                 dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
 319                 dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 +
 320                          IO_DMA1_BASE);
 321         } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
 322                 dma_outb(count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
 323                 dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 +
 324                          IO_DMA2_BASE);
 325         } else {
 326                 dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 +
 327                          IO_DMA2_BASE);
 328                 dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 +
 329                          IO_DMA2_BASE);
 330         }
 331 }
 332
 333 /* Get DMA residue count. After a DMA transfer, this
 334  * should return zero. Reading this while a DMA transfer is
 335  * still in progress will return unpredictable results.
 336  * If called before the channel has been used, it may return 1.
 337  * Otherwise, it returns the number of _bytes_ left to transfer.
 338  *
 339  * Assumes DMA flip-flop is clear.
 340  */
 341 static __inline__ int get_dma_residue(unsigned int dmanr)
 342 {
 343         unsigned int io_port = (dmanr <= 3) ?
 344             ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
 345             : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
 346
 347         /* using short to get 16-bit wrap around */
 348         unsigned short count;
 349
 350         count = 1 + dma_inb(io_port);
 351         count += dma_inb(io_port) << 8;
 352
 353         return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
 354             ? count : (count << 1);
 355
 356 }
 357
 358 /* These are in kernel/dma.c: */
 359
 360 /* reserve a DMA channel */
 361 extern int request_dma(unsigned int dmanr, const char *device_id);
 362 /* release it again */
 363 extern void free_dma(unsigned int dmanr);
 364
 365 #ifdef CONFIG_PCI
 366 extern int isa_dma_bridge_buggy;
 367 #else
 368 #define isa_dma_bridge_buggy    (0)
 369 #endif
 370 #endif                          /* _ASM_DMA_H */
 371 #endif                          /* __KERNEL__ */