include/asm-ppc/mmu.h

   1 /*
   2  * PowerPC memory management structures
   3  */
   4
   5 #ifdef __KERNEL__
   6 #ifndef _PPC_MMU_H_
   7 #define _PPC_MMU_H_
   8
   9 #include <linux/config.h>
  10
  11 #ifndef __ASSEMBLY__
  12
  13 /*
  14  * Define physical address type.  Machines using split size
  15  * virtual/physical addressing like 32-bit virtual / 36-bit
  16  * physical need a larger than native word size type. -Matt
  17  */
  18 #ifndef CONFIG_PHYS_64BIT
  19 typedef unsigned long phys_addr_t;
  20 #define PHYS_FMT        "%.8lx"
  21 #else
  22 typedef unsigned long long phys_addr_t;
  23 extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
  24 #define PHYS_FMT        "%16Lx"
  25 #endif
  26
  27 /* Default "unsigned long" context */
  28 typedef unsigned long mm_context_t;
  29
  30 /* Hardware Page Table Entry */
  31 typedef struct _PTE {
  32 #ifdef CONFIG_PPC64BRIDGE
  33         unsigned long long vsid:52;
  34         unsigned long api:5;
  35         unsigned long :5;
  36         unsigned long h:1;
  37         unsigned long v:1;
  38         unsigned long long rpn:52;
  39 #else /* CONFIG_PPC64BRIDGE */
  40         unsigned long v:1;      /* Entry is valid */
  41         unsigned long vsid:24;  /* Virtual segment identifier */
  42         unsigned long h:1;      /* Hash algorithm indicator */
  43         unsigned long api:6;    /* Abbreviated page index */
  44         unsigned long rpn:20;   /* Real (physical) page number */
  45 #endif /* CONFIG_PPC64BRIDGE */
  46         unsigned long    :3;    /* Unused */
  47         unsigned long r:1;      /* Referenced */
  48         unsigned long c:1;      /* Changed */
  49         unsigned long w:1;      /* Write-thru cache mode */
  50         unsigned long i:1;      /* Cache inhibited */
  51         unsigned long m:1;      /* Memory coherence */
  52         unsigned long g:1;      /* Guarded */
  53         unsigned long  :1;      /* Unused */
  54         unsigned long pp:2;     /* Page protection */
  55 } PTE;
  56
  57 /* Values for PP (assumes Ks=0, Kp=1) */
  58 #define PP_RWXX 0       /* Supervisor read/write, User none */
  59 #define PP_RWRX 1       /* Supervisor read/write, User read */
  60 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  61 #define PP_RXRX 3       /* Supervisor read,       User read */
  62
  63 /* Segment Register */
  64 typedef struct _SEGREG {
  65         unsigned long t:1;      /* Normal or I/O  type */
  66         unsigned long ks:1;     /* Supervisor 'key' (normally 0) */
  67         unsigned long kp:1;     /* User 'key' (normally 1) */
  68         unsigned long n:1;      /* No-execute */
  69         unsigned long :4;       /* Unused */
  70         unsigned long vsid:24;  /* Virtual Segment Identifier */
  71 } SEGREG;
  72
  73 /* Block Address Translation (BAT) Registers */
  74 typedef struct _P601_BATU {     /* Upper part of BAT for 601 processor */
  75         unsigned long bepi:15;  /* Effective page index (virtual address) */
  76         unsigned long :8;       /* unused */
  77         unsigned long w:1;
  78         unsigned long i:1;      /* Cache inhibit */
  79         unsigned long m:1;      /* Memory coherence */
  80         unsigned long ks:1;     /* Supervisor key (normally 0) */
  81         unsigned long kp:1;     /* User key (normally 1) */
  82         unsigned long pp:2;     /* Page access protections */
  83 } P601_BATU;
  84
  85 typedef struct _BATU {          /* Upper part of BAT (all except 601) */
  86 #ifdef CONFIG_PPC64BRIDGE
  87         unsigned long long bepi:47;
  88 #else /* CONFIG_PPC64BRIDGE */
  89         unsigned long bepi:15;  /* Effective page index (virtual address) */
  90 #endif /* CONFIG_PPC64BRIDGE */
  91         unsigned long :4;       /* Unused */
  92         unsigned long bl:11;    /* Block size mask */
  93         unsigned long vs:1;     /* Supervisor valid */
  94         unsigned long vp:1;     /* User valid */
  95 } BATU;
  96
  97 typedef struct _P601_BATL {     /* Lower part of BAT for 601 processor */
  98         unsigned long brpn:15;  /* Real page index (physical address) */
  99         unsigned long :10;      /* Unused */
 100         unsigned long v:1;      /* Valid bit */
 101         unsigned long bl:6;     /* Block size mask */
 102 } P601_BATL;
 103
 104 typedef struct _BATL {          /* Lower part of BAT (all except 601) */
 105 #ifdef CONFIG_PPC64BRIDGE
 106         unsigned long long brpn:47;
 107 #else /* CONFIG_PPC64BRIDGE */
 108         unsigned long brpn:15;  /* Real page index (physical address) */
 109 #endif /* CONFIG_PPC64BRIDGE */
 110         unsigned long :10;      /* Unused */
 111         unsigned long w:1;      /* Write-thru cache */
 112         unsigned long i:1;      /* Cache inhibit */
 113         unsigned long m:1;      /* Memory coherence */
 114         unsigned long g:1;      /* Guarded (MBZ in IBAT) */
 115         unsigned long :1;       /* Unused */
 116         unsigned long pp:2;     /* Page access protections */
 117 } BATL;
 118
 119 typedef struct _BAT {
 120         BATU batu;              /* Upper register */
 121         BATL batl;              /* Lower register */
 122 } BAT;
 123
 124 typedef struct _P601_BAT {
 125         P601_BATU batu;         /* Upper register */
 126         P601_BATL batl;         /* Lower register */
 127 } P601_BAT;
 128
 129 #endif /* __ASSEMBLY__ */
 130
 131 /* Block size masks */
 132 #define BL_128K 0x000
 133 #define BL_256K 0x001
 134 #define BL_512K 0x003
 135 #define BL_1M   0x007
 136 #define BL_2M   0x00F
 137 #define BL_4M   0x01F
 138 #define BL_8M   0x03F
 139 #define BL_16M  0x07F
 140 #define BL_32M  0x0FF
 141 #define BL_64M  0x1FF
 142 #define BL_128M 0x3FF
 143 #define BL_256M 0x7FF
 144
 145 /* BAT Access Protection */
 146 #define BPP_XX  0x00            /* No access */
 147 #define BPP_RX  0x01            /* Read only */
 148 #define BPP_RW  0x02            /* Read/write */
 149
 150 /* Control/status registers for the MPC8xx.
 151  * A write operation to these registers causes serialized access.
 152  * During software tablewalk, the registers used perform mask/shift-add
 153  * operations when written/read.  A TLB entry is created when the Mx_RPN
 154  * is written, and the contents of several registers are used to
 155  * create the entry.
 156  */
 157 #define SPRN_MI_CTR     784     /* Instruction TLB control register */
 158 #define MI_GPM          0x80000000      /* Set domain manager mode */
 159 #define MI_PPM          0x40000000      /* Set subpage protection */
 160 #define MI_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
 161 #define MI_RSV4I        0x08000000      /* Reserve 4 TLB entries */
 162 #define MI_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
 163 #define MI_IDXMASK      0x00001f00      /* TLB index to be loaded */
 164 #define MI_RESETVAL     0x00000000      /* Value of register at reset */
 165
 166 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 167  * Ks = 0, Kp = 1.
 168  */
 169 #define SPRN_MI_AP      786
 170 #define MI_Ks           0x80000000      /* Should not be set */
 171 #define MI_Kp           0x40000000      /* Should always be set */
 172
 173 /* The effective page number register.  When read, contains the information
 174  * about the last instruction TLB miss.  When MI_RPN is written, bits in
 175  * this register are used to create the TLB entry.
 176  */
 177 #define SPRN_MI_EPN     787
 178 #define MI_EPNMASK      0xfffff000      /* Effective page number for entry */
 179 #define MI_EVALID       0x00000200      /* Entry is valid */
 180 #define MI_ASIDMASK     0x0000000f      /* ASID match value */
 181                                         /* Reset value is undefined */
 182
 183 /* A "level 1" or "segment" or whatever you want to call it register.
 184  * For the instruction TLB, it contains bits that get loaded into the
 185  * TLB entry when the MI_RPN is written.
 186  */
 187 #define SPRN_MI_TWC     789
 188 #define MI_APG          0x000001e0      /* Access protection group (0) */
 189 #define MI_GUARDED      0x00000010      /* Guarded storage */
 190 #define MI_PSMASK       0x0000000c      /* Mask of page size bits */
 191 #define MI_PS8MEG       0x0000000c      /* 8M page size */
 192 #define MI_PS512K       0x00000004      /* 512K page size */
 193 #define MI_PS4K_16K     0x00000000      /* 4K or 16K page size */
 194 #define MI_SVALID       0x00000001      /* Segment entry is valid */
 195                                         /* Reset value is undefined */
 196
 197 /* Real page number.  Defined by the pte.  Writing this register
 198  * causes a TLB entry to be created for the instruction TLB, using
 199  * additional information from the MI_EPN, and MI_TWC registers.
 200  */
 201 #define SPRN_MI_RPN     790
 202
 203 /* Define an RPN value for mapping kernel memory to large virtual
 204  * pages for boot initialization.  This has real page number of 0,
 205  * large page size, shared page, cache enabled, and valid.
 206  * Also mark all subpages valid and write access.
 207  */
 208 #define MI_BOOTINIT     0x000001fd
 209
 210 #define SPRN_MD_CTR     792     /* Data TLB control register */
 211 #define MD_GPM          0x80000000      /* Set domain manager mode */
 212 #define MD_PPM          0x40000000      /* Set subpage protection */
 213 #define MD_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
 214 #define MD_WTDEF        0x10000000      /* Set writethrough when MMU dis */
 215 #define MD_RSV4I        0x08000000      /* Reserve 4 TLB entries */
 216 #define MD_TWAM         0x04000000      /* Use 4K page hardware assist */
 217 #define MD_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
 218 #define MD_IDXMASK      0x00001f00      /* TLB index to be loaded */
 219 #define MD_RESETVAL     0x04000000      /* Value of register at reset */
 220
 221 #define SPRN_M_CASID    793     /* Address space ID (context) to match */
 222 #define MC_ASIDMASK     0x0000000f      /* Bits used for ASID value */
 223
 224
 225 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 226  * Ks = 0, Kp = 1.
 227  */
 228 #define SPRN_MD_AP      794
 229 #define MD_Ks           0x80000000      /* Should not be set */
 230 #define MD_Kp           0x40000000      /* Should always be set */
 231
 232 /* The effective page number register.  When read, contains the information
 233  * about the last instruction TLB miss.  When MD_RPN is written, bits in
 234  * this register are used to create the TLB entry.
 235  */
 236 #define SPRN_MD_EPN     795
 237 #define MD_EPNMASK      0xfffff000      /* Effective page number for entry */
 238 #define MD_EVALID       0x00000200      /* Entry is valid */
 239 #define MD_ASIDMASK     0x0000000f      /* ASID match value */
 240                                         /* Reset value is undefined */
 241
 242 /* The pointer to the base address of the first level page table.
 243  * During a software tablewalk, reading this register provides the address
 244  * of the entry associated with MD_EPN.
 245  */
 246 #define SPRN_M_TWB      796
 247 #define M_L1TB          0xfffff000      /* Level 1 table base address */
 248 #define M_L1INDX        0x00000ffc      /* Level 1 index, when read */
 249                                         /* Reset value is undefined */
 250
 251 /* A "level 1" or "segment" or whatever you want to call it register.
 252  * For the data TLB, it contains bits that get loaded into the TLB entry
 253  * when the MD_RPN is written.  It is also provides the hardware assist
 254  * for finding the PTE address during software tablewalk.
 255  */
 256 #define SPRN_MD_TWC     797
 257 #define MD_L2TB         0xfffff000      /* Level 2 table base address */
 258 #define MD_L2INDX       0xfffffe00      /* Level 2 index (*pte), when read */
 259 #define MD_APG          0x000001e0      /* Access protection group (0) */
 260 #define MD_GUARDED      0x00000010      /* Guarded storage */
 261 #define MD_PSMASK       0x0000000c      /* Mask of page size bits */
 262 #define MD_PS8MEG       0x0000000c      /* 8M page size */
 263 #define MD_PS512K       0x00000004      /* 512K page size */
 264 #define MD_PS4K_16K     0x00000000      /* 4K or 16K page size */
 265 #define MD_WT           0x00000002      /* Use writethrough page attribute */
 266 #define MD_SVALID       0x00000001      /* Segment entry is valid */
 267                                         /* Reset value is undefined */
 268
 269
 270 /* Real page number.  Defined by the pte.  Writing this register
 271  * causes a TLB entry to be created for the data TLB, using
 272  * additional information from the MD_EPN, and MD_TWC registers.
 273  */
 274 #define SPRN_MD_RPN     798
 275
 276 /* This is a temporary storage register that could be used to save
 277  * a processor working register during a tablewalk.
 278  */
 279 #define SPRN_M_TW       799
 280
 281 /*
 282  * At present, all PowerPC 400-class processors share a similar TLB
 283  * architecture. The instruction and data sides share a unified,
 284  * 64-entry, fully-associative TLB which is maintained totally under
 285  * software control. In addition, the instruction side has a
 286  * hardware-managed, 4-entry, fully- associative TLB which serves as a
 287  * first level to the shared TLB. These two TLBs are known as the UTLB
 288  * and ITLB, respectively.
 289  */
 290
 291 #define        PPC4XX_TLB_SIZE 64
 292
 293 /*
 294  * TLB entries are defined by a "high" tag portion and a "low" data
 295  * portion.  On all architectures, the data portion is 32-bits.
 296  *
 297  * TLB entries are managed entirely under software control by reading,
 298  * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
 299  * instructions.
 300  */
 301
 302 #define TLB_LO          1
 303 #define TLB_HI          0
 304
 305 #define TLB_DATA        TLB_LO
 306 #define TLB_TAG         TLB_HI
 307
 308 /* Tag portion */
 309
 310 #define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
 311 #define TLB_PAGESZ_MASK 0x00000380
 312 #define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
 313 #define   PAGESZ_1K             0
 314 #define   PAGESZ_4K             1
 315 #define   PAGESZ_16K            2
 316 #define   PAGESZ_64K            3
 317 #define   PAGESZ_256K           4
 318 #define   PAGESZ_1M             5
 319 #define   PAGESZ_4M             6
 320 #define   PAGESZ_16M            7
 321 #define TLB_VALID       0x00000040      /* Entry is valid */
 322
 323 /* Data portion */
 324
 325 #define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
 326 #define TLB_PERM_MASK   0x00000300
 327 #define TLB_EX          0x00000200      /* Instruction execution allowed */
 328 #define TLB_WR          0x00000100      /* Writes permitted */
 329 #define TLB_ZSEL_MASK   0x000000F0
 330 #define TLB_ZSEL(x)     (((x) & 0xF) << 4)
 331 #define TLB_ATTR_MASK   0x0000000F
 332 #define TLB_W           0x00000008      /* Caching is write-through */
 333 #define TLB_I           0x00000004      /* Caching is inhibited */
 334 #define TLB_M           0x00000002      /* Memory is coherent */
 335 #define TLB_G           0x00000001      /* Memory is guarded from prefetch */
 336
 337 /*
 338  * PPC440 support
 339  */
 340 #define PPC44x_MMUCR_TID        0x000000ff
 341 #define PPC44x_MMUCR_STS        0x00010000
 342
 343 #define PPC44x_TLB_PAGEID       0
 344 #define PPC44x_TLB_XLAT         1
 345 #define PPC44x_TLB_ATTRIB       2
 346
 347 /* Page identification fields */
 348 #define PPC44x_TLB_EPN_MASK     0xfffffc00      /* Effective Page Number */
 349 #define PPC44x_TLB_VALID        0x00000200      /* Valid flag */
 350 #define PPC44x_TLB_TS           0x00000100      /* Translation address space */
 351 #define PPC44x_TLB_1K           0x00000000      /* Page sizes */
 352 #define PPC44x_TLB_4K           0x00000010
 353 #define PPC44x_TLB_16K          0x00000020
 354 #define PPC44x_TLB_64K          0x00000030
 355 #define PPC44x_TLB_256K         0x00000040
 356 #define PPC44x_TLB_1M           0x00000050
 357 #define PPC44x_TLB_16M          0x00000070
 358 #define PPC44x_TLB_256M         0x00000090
 359
 360 /* Translation fields */
 361 #define PPC44x_TLB_RPN_MASK     0xfffffc00      /* Real Page Number */
 362 #define PPC44x_TLB_ERPN_MASK    0x0000000f
 363
 364 /* Storage attribute and access control fields */
 365 #define PPC44x_TLB_ATTR_MASK    0x0000ff80
 366 #define PPC44x_TLB_U0           0x00008000      /* User 0 */
 367 #define PPC44x_TLB_U1           0x00004000      /* User 1 */
 368 #define PPC44x_TLB_U2           0x00002000      /* User 2 */
 369 #define PPC44x_TLB_U3           0x00001000      /* User 3 */
 370 #define PPC44x_TLB_W            0x00000800      /* Caching is write-through */
 371 #define PPC44x_TLB_I            0x00000400      /* Caching is inhibited */
 372 #define PPC44x_TLB_M            0x00000200      /* Memory is coherent */
 373 #define PPC44x_TLB_G            0x00000100      /* Memory is guarded */
 374 #define PPC44x_TLB_E            0x00000080      /* Memory is guarded */
 375
 376 #define PPC44x_TLB_PERM_MASK    0x0000003f
 377 #define PPC44x_TLB_UX           0x00000020      /* User execution */
 378 #define PPC44x_TLB_UW           0x00000010      /* User write */
 379 #define PPC44x_TLB_UR           0x00000008      /* User read */
 380 #define PPC44x_TLB_SX           0x00000004      /* Super execution */
 381 #define PPC44x_TLB_SW           0x00000002      /* Super write */
 382 #define PPC44x_TLB_SR           0x00000001      /* Super read */
 383
 384 /* Book-E defined page sizes */
 385 #define BOOKE_PAGESZ_1K         0
 386 #define BOOKE_PAGESZ_4K         1
 387 #define BOOKE_PAGESZ_16K        2
 388 #define BOOKE_PAGESZ_64K        3
 389 #define BOOKE_PAGESZ_256K       4
 390 #define BOOKE_PAGESZ_1M         5
 391 #define BOOKE_PAGESZ_4M         6
 392 #define BOOKE_PAGESZ_16M        7
 393 #define BOOKE_PAGESZ_64M        8
 394 #define BOOKE_PAGESZ_256M       9
 395 #define BOOKE_PAGESZ_1GB        10
 396 #define BOOKE_PAGESZ_4GB        11
 397 #define BOOKE_PAGESZ_16GB       12
 398 #define BOOKE_PAGESZ_64GB       13
 399 #define BOOKE_PAGESZ_256GB      14
 400 #define BOOKE_PAGESZ_1TB        15
 401
 402 /*
 403  * Freescale Book-E MMU support
 404  */
 405
 406 #define MAS0_TLBSEL(x)  ((x << 28) & 0x30000000)
 407 #define MAS0_ESEL(x)    ((x << 16) & 0x0FFF0000)
 408 #define MAS0_NV(x)      ((x) & 0x00000FFF)
 409
 410 #define MAS1_VALID      0x80000000
 411 #define MAS1_IPROT      0x40000000
 412 #define MAS1_TID(x)     ((x << 16) & 0x3FFF0000)
 413 #define MAS1_TS         0x00001000
 414 #define MAS1_TSIZE(x)   ((x << 8) & 0x00000F00)
 415
 416 #define MAS2_EPN        0xFFFFF000
 417 #define MAS2_X0         0x00000040
 418 #define MAS2_X1         0x00000020
 419 #define MAS2_W          0x00000010
 420 #define MAS2_I          0x00000008
 421 #define MAS2_M          0x00000004
 422 #define MAS2_G          0x00000002
 423 #define MAS2_E          0x00000001
 424
 425 #define MAS3_RPN        0xFFFFF000
 426 #define MAS3_U0         0x00000200
 427 #define MAS3_U1         0x00000100
 428 #define MAS3_U2         0x00000080
 429 #define MAS3_U3         0x00000040
 430 #define MAS3_UX         0x00000020
 431 #define MAS3_SX         0x00000010
 432 #define MAS3_UW         0x00000008
 433 #define MAS3_SW         0x00000004
 434 #define MAS3_UR         0x00000002
 435 #define MAS3_SR         0x00000001
 436
 437 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
 438 #define MAS4_TIDDSEL    0x000F0000
 439 #define MAS4_TSIZED(x)  MAS1_TSIZE(x)
 440 #define MAS4_X0D        0x00000040
 441 #define MAS4_X1D        0x00000020
 442 #define MAS4_WD         0x00000010
 443 #define MAS4_ID         0x00000008
 444 #define MAS4_MD         0x00000004
 445 #define MAS4_GD         0x00000002
 446 #define MAS4_ED         0x00000001
 447
 448 #define MAS6_SPID0      0x3FFF0000
 449 #define MAS6_SPID1      0x00007FFE
 450 #define MAS6_SAS        0x00000001
 451 #define MAS6_SPID       MAS6_SPID0
 452
 453 #define MAS7_RPN        0xFFFFFFFF
 454
 455 #endif /* _PPC_MMU_H_ */
 456 #endif /* __KERNEL__ */