include/asm-ppc64/mmu.h

   1 /*
   2  * PowerPC memory management structures
   3  *
   4  * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
   5  *   PPC64 rework.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12
  13 #ifndef _PPC64_MMU_H_
  14 #define _PPC64_MMU_H_
  15
  16 #include <linux/config.h>
  17 #include <asm/page.h>
  18
  19 /*
  20  * Segment table
  21  */
  22
  23 #define STE_ESID_V      0x80
  24 #define STE_ESID_KS     0x20
  25 #define STE_ESID_KP     0x10
  26 #define STE_ESID_N      0x08
  27
  28 #define STE_VSID_SHIFT  12
  29
  30 /* Location of cpu0's segment table */
  31 #define STAB0_PAGE      0x9
  32 #define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
  33 #define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR)
  34
  35 /*
  36  * SLB
  37  */
  38
  39 #define SLB_NUM_BOLTED          3
  40 #define SLB_CACHE_ENTRIES       8
  41
  42 /* Bits in the SLB ESID word */
  43 #define SLB_ESID_V              ASM_CONST(0x0000000008000000) /* valid */
  44
  45 /* Bits in the SLB VSID word */
  46 #define SLB_VSID_SHIFT          12
  47 #define SLB_VSID_KS             ASM_CONST(0x0000000000000800)
  48 #define SLB_VSID_KP             ASM_CONST(0x0000000000000400)
  49 #define SLB_VSID_N              ASM_CONST(0x0000000000000200) /* no-execute */
  50 #define SLB_VSID_L              ASM_CONST(0x0000000000000100) /* largepage */
  51 #define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
  52 #define SLB_VSID_LS             ASM_CONST(0x0000000000000070) /* size of largepage */
  53
  54 #define SLB_VSID_KERNEL         (SLB_VSID_KP|SLB_VSID_C)
  55 #define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS)
  56
  57 /*
  58  * Hash table
  59  */
  60
  61 #define HPTES_PER_GROUP 8
  62
  63 /* Values for PP (assumes Ks=0, Kp=1) */
  64 /* pp0 will always be 0 for linux     */
  65 #define PP_RWXX 0       /* Supervisor read/write, User none */
  66 #define PP_RWRX 1       /* Supervisor read/write, User read */
  67 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  68 #define PP_RXRX 3       /* Supervisor read,       User read */
  69
  70 #ifndef __ASSEMBLY__
  71
  72 /* Hardware Page Table Entry */
  73 typedef struct {
  74         unsigned long avpn:57; /* vsid | api == avpn  */
  75         unsigned long :     2; /* Software use */
  76         unsigned long bolted: 1; /* HPTE is "bolted" */
  77         unsigned long lock: 1; /* lock on pSeries SMP */
  78         unsigned long l:    1; /* Virtual page is large (L=1) or 4 KB (L=0) */
  79         unsigned long h:    1; /* Hash function identifier */
  80         unsigned long v:    1; /* Valid (v=1) or invalid (v=0) */
  81 } Hpte_dword0;
  82
  83 typedef struct {
  84         unsigned long pp0:  1; /* Page protection bit 0 */
  85         unsigned long ts:   1; /* Tag set bit */
  86         unsigned long rpn: 50; /* Real page number */
  87         unsigned long :     2; /* Reserved */
  88         unsigned long ac:   1; /* Address compare */
  89         unsigned long r:    1; /* Referenced */
  90         unsigned long c:    1; /* Changed */
  91         unsigned long w:    1; /* Write-thru cache mode */
  92         unsigned long i:    1; /* Cache inhibited */
  93         unsigned long m:    1; /* Memory coherence required */
  94         unsigned long g:    1; /* Guarded */
  95         unsigned long n:    1; /* No-execute */
  96         unsigned long pp:   2; /* Page protection bits 1:2 */
  97 } Hpte_dword1;
  98
  99 typedef struct {
 100         char padding[6];                /* padding */
 101         unsigned long :       6;        /* padding */
 102         unsigned long flags: 10;        /* HPTE flags */
 103 } Hpte_dword1_flags;
 104
 105 typedef struct {
 106         union {
 107                 unsigned long dword0;
 108                 Hpte_dword0   dw0;
 109         } dw0;
 110
 111         union {
 112                 unsigned long dword1;
 113                 Hpte_dword1 dw1;
 114                 Hpte_dword1_flags flags;
 115         } dw1;
 116 } HPTE;
 117
 118 extern HPTE *           htab_address;
 119 extern unsigned long    htab_hash_mask;
 120
 121 static inline unsigned long hpt_hash(unsigned long vpn, int large)
 122 {
 123         unsigned long vsid;
 124         unsigned long page;
 125
 126         if (large) {
 127                 vsid = vpn >> 4;
 128                 page = vpn & 0xf;
 129         } else {
 130                 vsid = vpn >> 16;
 131                 page = vpn & 0xffff;
 132         }
 133
 134         return (vsid & 0x7fffffffffUL) ^ page;
 135 }
 136
 137 static inline void __tlbie(unsigned long va, int large)
 138 {
 139         /* clear top 16 bits, non SLS segment */
 140         va &= ~(0xffffULL << 48);
 141
 142         if (large) {
 143                 va &= HPAGE_MASK;
 144                 asm volatile("tlbie %0,1" : : "r"(va) : "memory");
 145         } else {
 146                 va &= PAGE_MASK;
 147                 asm volatile("tlbie %0,0" : : "r"(va) : "memory");
 148         }
 149 }
 150
 151 static inline void tlbie(unsigned long va, int large)
 152 {
 153         asm volatile("ptesync": : :"memory");
 154         __tlbie(va, large);
 155         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 156 }
 157
 158 static inline void __tlbiel(unsigned long va)
 159 {
 160         /* clear top 16 bits, non SLS segment */
 161         va &= ~(0xffffULL << 48);
 162         va &= PAGE_MASK;
 163
 164         /*
 165          * Thanks to Alan Modra we are now able to use machine specific
 166          * assembly instructions (like tlbiel) by using the gas -many flag.
 167          * However we have to support older toolchains so for the moment
 168          * we hardwire it.
 169          */
 170 #if 0
 171         asm volatile("tlbiel %0" : : "r"(va) : "memory");
 172 #else
 173         asm volatile(".long 0x7c000224 | (%0 << 11)" : : "r"(va) : "memory");
 174 #endif
 175 }
 176
 177 static inline void tlbiel(unsigned long va)
 178 {
 179         asm volatile("ptesync": : :"memory");
 180         __tlbiel(va);
 181         asm volatile("ptesync": : :"memory");
 182 }
 183
 184 static inline unsigned long slot2va(unsigned long avpn, unsigned long large,
 185                 unsigned long secondary, unsigned long slot)
 186 {
 187         unsigned long va;
 188
 189         va = avpn << 23;
 190
 191         if (!large) {
 192                 unsigned long vpi, pteg;
 193
 194                 pteg = slot / HPTES_PER_GROUP;
 195                 if (secondary)
 196                         pteg = ~pteg;
 197
 198                 vpi = ((va >> 28) ^ pteg) & htab_hash_mask;
 199
 200                 va |= vpi << PAGE_SHIFT;
 201         }
 202
 203         return va;
 204 }
 205
 206 /*
 207  * Handle a fault by adding an HPTE. If the address can't be determined
 208  * to be valid via Linux page tables, return 1. If handled return 0
 209  */
 210 extern int __hash_page(unsigned long ea, unsigned long access,
 211                        unsigned long vsid, pte_t *ptep, unsigned long trap,
 212                        int local);
 213
 214 extern void htab_finish_init(void);
 215
 216 extern void hpte_init_native(void);
 217 extern void hpte_init_lpar(void);
 218 extern void hpte_init_iSeries(void);
 219
 220 extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
 221                                      unsigned long va, unsigned long prpn,
 222                                      int secondary, unsigned long hpteflags,
 223                                      int bolted, int large);
 224 extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
 225                                unsigned long prpn, int secondary,
 226                                unsigned long hpteflags, int bolted, int large);
 227
 228 #endif /* __ASSEMBLY__ */
 229
 230 /*
 231  * VSID allocation
 232  *
 233  * We first generate a 36-bit "proto-VSID".  For kernel addresses this
 234  * is equal to the ESID, for user addresses it is:
 235  *      (context << 15) | (esid & 0x7fff)
 236  *
 237  * The two forms are distinguishable because the top bit is 0 for user
 238  * addresses, whereas the top two bits are 1 for kernel addresses.
 239  * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
 240  * now.
 241  *
 242  * The proto-VSIDs are then scrambled into real VSIDs with the
 243  * multiplicative hash:
 244  *
 245  *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
 246  *      where   VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
 247  *              VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
 248  *
 249  * This scramble is only well defined for proto-VSIDs below
 250  * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
 251  * reserved.  VSID_MULTIPLIER is prime, so in particular it is
 252  * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
 253  * Because the modulus is 2^n-1 we can compute it efficiently without
 254  * a divide or extra multiply (see below).
 255  *
 256  * This scheme has several advantages over older methods:
 257  *
 258  *      - We have VSIDs allocated for every kernel address
 259  * (i.e. everything above 0xC000000000000000), except the very top
 260  * segment, which simplifies several things.
 261  *
 262  *      - We allow for 15 significant bits of ESID and 20 bits of
 263  * context for user addresses.  i.e. 8T (43 bits) of address space for
 264  * up to 1M contexts (although the page table structure and context
 265  * allocation will need changes to take advantage of this).
 266  *
 267  *      - The scramble function gives robust scattering in the hash
 268  * table (at least based on some initial results).  The previous
 269  * method was more susceptible to pathological cases giving excessive
 270  * hash collisions.
 271  */
 272 /*
 273  * WARNING - If you change these you must make sure the asm
 274  * implementations in slb_allocate (slb_low.S), do_stab_bolted
 275  * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
 276  *
 277  * You'll also need to change the precomputed VSID values in head.S
 278  * which are used by the iSeries firmware.
 279  */
 280
 281 #define VSID_MULTIPLIER ASM_CONST(200730139)    /* 28-bit prime */
 282 #define VSID_BITS       36
 283 #define VSID_MODULUS    ((1UL<<VSID_BITS)-1)
 284
 285 #define CONTEXT_BITS    20
 286 #define USER_ESID_BITS  15
 287
 288 /*
 289  * This macro generates asm code to compute the VSID scramble
 290  * function.  Used in slb_allocate() and do_stab_bolted.  The function
 291  * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
 292  *
 293  *      rt = register continaing the proto-VSID and into which the
 294  *              VSID will be stored
 295  *      rx = scratch register (clobbered)
 296  *
 297  *      - rt and rx must be different registers
 298  *      - The answer will end up in the low 36 bits of rt.  The higher
 299  *        bits may contain other garbage, so you may need to mask the
 300  *        result.
 301  */
 302 #define ASM_VSID_SCRAMBLE(rt, rx)       \
 303         lis     rx,VSID_MULTIPLIER@h;                                   \
 304         ori     rx,rx,VSID_MULTIPLIER@l;                                \
 305         mulld   rt,rt,rx;               /* rt = rt * MULTIPLIER */      \
 306                                                                         \
 307         srdi    rx,rt,VSID_BITS;                                        \
 308         clrldi  rt,rt,(64-VSID_BITS);                                   \
 309         add     rt,rt,rx;               /* add high and low bits */     \
 310         /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and         \
 311          * 2^36-1+2^28-1.  That in particular means that if r3 >=       \
 312          * 2^36-1, then r3+1 has the 2^36 bit set.  So, if r3+1 has     \
 313          * the bit clear, r3 already has the answer we want, if it      \
 314          * doesn't, the answer is the low 36 bits of r3+1.  So in all   \
 315          * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
 316         addi    rx,rt,1;                                                \
 317         srdi    rx,rx,VSID_BITS;        /* extract 2^36 bit */          \
 318         add     rt,rt,rx
 319
 320
 321 #ifndef __ASSEMBLY__
 322
 323 typedef unsigned long mm_context_id_t;
 324
 325 typedef struct {
 326         mm_context_id_t id;
 327 #ifdef CONFIG_HUGETLB_PAGE
 328         pgd_t *huge_pgdir;
 329         u16 htlb_segs; /* bitmask */
 330 #endif
 331 } mm_context_t;
 332
 333
 334 static inline unsigned long vsid_scramble(unsigned long protovsid)
 335 {
 336 #if 0
 337         /* The code below is equivalent to this function for arguments
 338          * < 2^VSID_BITS, which is all this should ever be called
 339          * with.  However gcc is not clever enough to compute the
 340          * modulus (2^n-1) without a second multiply. */
 341         return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
 342 #else /* 1 */
 343         unsigned long x;
 344
 345         x = protovsid * VSID_MULTIPLIER;
 346         x = (x >> VSID_BITS) + (x & VSID_MODULUS);
 347         return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
 348 #endif /* 1 */
 349 }
 350
 351 /* This is only valid for addresses >= KERNELBASE */
 352 static inline unsigned long get_kernel_vsid(unsigned long ea)
 353 {
 354         return vsid_scramble(ea >> SID_SHIFT);
 355 }
 356
 357 /* This is only valid for user addresses (which are below 2^41) */
 358 static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
 359 {
 360         return vsid_scramble((context << USER_ESID_BITS)
 361                              | (ea >> SID_SHIFT));
 362 }
 363
 364 #endif /* __ASSEMBLY */
 365
 366 #endif /* _PPC64_MMU_H_ */