include/asm-arm/arch-ixp2000/ixp2000-regs.h

   1 /*
   2  * include/asm-arm/arch-ixp2000/ixp2000-regs.h
   3  *
   4  * Chipset register definitions for IXP2400/2800 based systems.
   5  *
   6  * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
   7  *
   8  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   9  *
  10  * Copyright (C) 2002 Intel Corp.
  11  * Copyright (C) 2003-2004 MontaVista Software, Inc.
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  */
  18 #ifndef _IXP2000_REGS_H_
  19 #define _IXP2000_REGS_H_
  20
  21 /*
  22  * IXP2000 linux memory map:
  23  *
  24  * virt         phys            size
  25  * fb000000     db000000        16M             PCI CFG1
  26  * fc000000     da000000        16M             PCI CFG0
  27  * fd000000     d8000000        16M             PCI I/O
  28  * fe[0-7]00000                 8M              per-platform mappings
  29  * feb00000     c8000000        1M              MSF
  30  * fec00000     df000000        1M              PCI CSRs
  31  * fed00000     de000000        1M              PCI CREG
  32  * fee00000     d6000000        1M              INTCTL
  33  * fef00000     c0000000        1M              CAP
  34  */
  35
  36 /*
  37  * Static I/O regions.
  38  *
  39  * Most of the registers are clumped in 4K regions spread throughout
  40  * the 0xc0000000 -> 0xc0100000 address range, but we just map in
  41  * the whole range using a single 1 MB section instead of small
  42  * 4K pages.  This has two advantages for us:
  43  *
  44  * 1) We use only one TLB entry for large number of on-chip I/O devices.
  45  *
  46  * 2) We can easily set the Section attributes to XCB=101 on the IXP2400
  47  *    as required per erratum #66.  We accomplish this by using a
  48  *    new MT_IXP2000_DEVICE memory type with the bits set as required.
  49  *
  50  * CAP stands for CSR Access Proxy.
  51  *
  52  * If you change the virtual address of this mapping, please propagate
  53  * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
  54  * address of the UART located in this region.
  55  */
  56
  57 #define IXP2000_CAP_PHYS_BASE           0xc0000000
  58 #define IXP2000_CAP_VIRT_BASE           0xfef00000
  59 #define IXP2000_CAP_SIZE                0x00100000
  60
  61 /*
  62  * Addresses for specific on-chip peripherals.
  63  */
  64 #define IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfef80000
  65 #define IXP2000_GLOBAL_REG_VIRT_BASE    0xfef04000
  66 #define IXP2000_UART_PHYS_BASE          0xc0030000
  67 #define IXP2000_UART_VIRT_BASE          0xfef30000
  68 #define IXP2000_TIMER_VIRT_BASE         0xfef20000
  69 #define IXP2000_UENGINE_CSR_VIRT_BASE   0xfef18000
  70 #define IXP2000_GPIO_VIRT_BASE          0xfef10000
  71
  72 /*
  73  * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
  74  * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
  75  * entry-macro.S, so if you ever change these please propagate
  76  * the change.
  77  */
  78 #define IXP2000_INTCTL_PHYS_BASE        0xd6000000
  79 #define IXP2000_INTCTL_VIRT_BASE        0xfee00000
  80 #define IXP2000_INTCTL_SIZE             0x00100000
  81
  82 #define IXP2000_PCI_CREG_PHYS_BASE      0xde000000
  83 #define IXP2000_PCI_CREG_VIRT_BASE      0xfed00000
  84 #define IXP2000_PCI_CREG_SIZE           0x00100000
  85
  86 #define IXP2000_PCI_CSR_PHYS_BASE       0xdf000000
  87 #define IXP2000_PCI_CSR_VIRT_BASE       0xfec00000
  88 #define IXP2000_PCI_CSR_SIZE            0x00100000
  89
  90 #define IXP2000_MSF_PHYS_BASE           0xc8000000
  91 #define IXP2000_MSF_VIRT_BASE           0xfeb00000
  92 #define IXP2000_MSF_SIZE                0x00100000
  93
  94 #define IXP2000_PCI_IO_PHYS_BASE        0xd8000000
  95 #define IXP2000_PCI_IO_VIRT_BASE        0xfd000000
  96 #define IXP2000_PCI_IO_SIZE             0x01000000
  97
  98 #define IXP2000_PCI_CFG0_PHYS_BASE      0xda000000
  99 #define IXP2000_PCI_CFG0_VIRT_BASE      0xfc000000
 100 #define IXP2000_PCI_CFG0_SIZE           0x01000000
 101
 102 #define IXP2000_PCI_CFG1_PHYS_BASE      0xdb000000
 103 #define IXP2000_PCI_CFG1_VIRT_BASE      0xfb000000
 104 #define IXP2000_PCI_CFG1_SIZE           0x01000000
 105
 106 /*
 107  * Timers
 108  */
 109 #define IXP2000_TIMER_REG(x)            ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
 110 /* Timer control */
 111 #define IXP2000_T1_CTL                  IXP2000_TIMER_REG(0x00)
 112 #define IXP2000_T2_CTL                  IXP2000_TIMER_REG(0x04)
 113 #define IXP2000_T3_CTL                  IXP2000_TIMER_REG(0x08)
 114 #define IXP2000_T4_CTL                  IXP2000_TIMER_REG(0x0c)
 115 /* Store initial value */
 116 #define IXP2000_T1_CLD                  IXP2000_TIMER_REG(0x10)
 117 #define IXP2000_T2_CLD                  IXP2000_TIMER_REG(0x14)
 118 #define IXP2000_T3_CLD                  IXP2000_TIMER_REG(0x18)
 119 #define IXP2000_T4_CLD                  IXP2000_TIMER_REG(0x1c)
 120 /* Read current value */
 121 #define IXP2000_T1_CSR                  IXP2000_TIMER_REG(0x20)
 122 #define IXP2000_T2_CSR                  IXP2000_TIMER_REG(0x24)
 123 #define IXP2000_T3_CSR                  IXP2000_TIMER_REG(0x28)
 124 #define IXP2000_T4_CSR                  IXP2000_TIMER_REG(0x2c)
 125 /* Clear associated timer interrupt */
 126 #define IXP2000_T1_CLR                  IXP2000_TIMER_REG(0x30)
 127 #define IXP2000_T2_CLR                  IXP2000_TIMER_REG(0x34)
 128 #define IXP2000_T3_CLR                  IXP2000_TIMER_REG(0x38)
 129 #define IXP2000_T4_CLR                  IXP2000_TIMER_REG(0x3c)
 130 /* Timer watchdog enable for T4 */
 131 #define IXP2000_TWDE                    IXP2000_TIMER_REG(0x40)
 132
 133 #define WDT_ENABLE                      0x00000001
 134 #define TIMER_DIVIDER_256               0x00000008
 135 #define TIMER_ENABLE                    0x00000080
 136 #define IRQ_MASK_TIMER1                 (1 << 4)
 137
 138 /*
 139  * Interrupt controller registers
 140  */
 141 #define IXP2000_INTCTL_REG(x)           (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
 142 #define IXP2000_IRQ_STATUS              IXP2000_INTCTL_REG(0x08)
 143 #define IXP2000_IRQ_ENABLE              IXP2000_INTCTL_REG(0x10)
 144 #define IXP2000_IRQ_ENABLE_SET          IXP2000_INTCTL_REG(0x10)
 145 #define IXP2000_IRQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x18)
 146 #define IXP2000_FIQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x14)
 147 #define IXP2000_IRQ_ERR_STATUS          IXP2000_INTCTL_REG(0x24)
 148 #define IXP2000_IRQ_ERR_ENABLE_SET      IXP2000_INTCTL_REG(0x2c)
 149 #define IXP2000_FIQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x30)
 150 #define IXP2000_IRQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x34)
 151 #define IXP2000_IRQ_THD_RAW_STATUS_A_0  IXP2000_INTCTL_REG(0x60)
 152 #define IXP2000_IRQ_THD_RAW_STATUS_A_1  IXP2000_INTCTL_REG(0x64)
 153 #define IXP2000_IRQ_THD_RAW_STATUS_A_2  IXP2000_INTCTL_REG(0x68)
 154 #define IXP2000_IRQ_THD_RAW_STATUS_A_3  IXP2000_INTCTL_REG(0x6c)
 155 #define IXP2000_IRQ_THD_RAW_STATUS_B_0  IXP2000_INTCTL_REG(0x80)
 156 #define IXP2000_IRQ_THD_RAW_STATUS_B_1  IXP2000_INTCTL_REG(0x84)
 157 #define IXP2000_IRQ_THD_RAW_STATUS_B_2  IXP2000_INTCTL_REG(0x88)
 158 #define IXP2000_IRQ_THD_RAW_STATUS_B_3  IXP2000_INTCTL_REG(0x8c)
 159 #define IXP2000_IRQ_THD_ENABLE_SET_A_0  IXP2000_INTCTL_REG(0x160)
 160 #define IXP2000_IRQ_THD_ENABLE_SET_A_1  IXP2000_INTCTL_REG(0x164)
 161 #define IXP2000_IRQ_THD_ENABLE_SET_A_2  IXP2000_INTCTL_REG(0x168)
 162 #define IXP2000_IRQ_THD_ENABLE_SET_A_3  IXP2000_INTCTL_REG(0x16c)
 163 #define IXP2000_IRQ_THD_ENABLE_SET_B_0  IXP2000_INTCTL_REG(0x180)
 164 #define IXP2000_IRQ_THD_ENABLE_SET_B_1  IXP2000_INTCTL_REG(0x184)
 165 #define IXP2000_IRQ_THD_ENABLE_SET_B_2  IXP2000_INTCTL_REG(0x188)
 166 #define IXP2000_IRQ_THD_ENABLE_SET_B_3  IXP2000_INTCTL_REG(0x18c)
 167 #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0        IXP2000_INTCTL_REG(0x1e0)
 168 #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1        IXP2000_INTCTL_REG(0x1e4)
 169 #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2        IXP2000_INTCTL_REG(0x1e8)
 170 #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3        IXP2000_INTCTL_REG(0x1ec)
 171 #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0        IXP2000_INTCTL_REG(0x200)
 172 #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1        IXP2000_INTCTL_REG(0x204)
 173 #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2        IXP2000_INTCTL_REG(0x208)
 174 #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3        IXP2000_INTCTL_REG(0x20c)
 175
 176 /*
 177  * Mask of valid IRQs in the 32-bit IRQ register. We use
 178  * this to mark certain IRQs as being invalid.
 179  */
 180 #define IXP2000_VALID_IRQ_MASK  0x0f0fffff
 181
 182 /*
 183  * PCI config register access from core
 184  */
 185 #define IXP2000_PCI_CREG(x)             (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
 186 #define IXP2000_PCI_CMDSTAT             IXP2000_PCI_CREG(0x04)
 187 #define IXP2000_PCI_CSR_BAR             IXP2000_PCI_CREG(0x10)
 188 #define IXP2000_PCI_SRAM_BAR            IXP2000_PCI_CREG(0x14)
 189 #define IXP2000_PCI_SDRAM_BAR           IXP2000_PCI_CREG(0x18)
 190
 191 /*
 192  * PCI CSRs
 193  */
 194 #define IXP2000_PCI_CSR(x)              (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
 195
 196 /*
 197  * PCI outbound interrupts
 198  */
 199 #define IXP2000_PCI_OUT_INT_STATUS      IXP2000_PCI_CSR(0x30)
 200 #define IXP2000_PCI_OUT_INT_MASK        IXP2000_PCI_CSR(0x34)
 201 /*
 202  * PCI communications
 203  */
 204 #define IXP2000_PCI_MAILBOX0            IXP2000_PCI_CSR(0x50)
 205 #define IXP2000_PCI_MAILBOX1            IXP2000_PCI_CSR(0x54)
 206 #define IXP2000_PCI_MAILBOX2            IXP2000_PCI_CSR(0x58)
 207 #define IXP2000_PCI_MAILBOX3            IXP2000_PCI_CSR(0x5C)
 208 #define IXP2000_XSCALE_DOORBELL         IXP2000_PCI_CSR(0x60)
 209 #define IXP2000_XSCALE_DOORBELL_SETUP   IXP2000_PCI_CSR(0x64)
 210 #define IXP2000_PCI_DOORBELL            IXP2000_PCI_CSR(0x70)
 211 #define IXP2000_PCI_DOORBELL_SETUP      IXP2000_PCI_CSR(0x74)
 212
 213 /*
 214  * DMA engines
 215  */
 216 #define IXP2000_PCI_CH1_BYTE_CNT        IXP2000_PCI_CSR(0x80)
 217 #define IXP2000_PCI_CH1_ADDR            IXP2000_PCI_CSR(0x84)
 218 #define IXP2000_PCI_CH1_DRAM_ADDR       IXP2000_PCI_CSR(0x88)
 219 #define IXP2000_PCI_CH1_DESC_PTR        IXP2000_PCI_CSR(0x8C)
 220 #define IXP2000_PCI_CH1_CNTRL           IXP2000_PCI_CSR(0x90)
 221 #define IXP2000_PCI_CH1_ME_PARAM        IXP2000_PCI_CSR(0x94)
 222 #define IXP2000_PCI_CH2_BYTE_CNT        IXP2000_PCI_CSR(0xA0)
 223 #define IXP2000_PCI_CH2_ADDR            IXP2000_PCI_CSR(0xA4)
 224 #define IXP2000_PCI_CH2_DRAM_ADDR       IXP2000_PCI_CSR(0xA8)
 225 #define IXP2000_PCI_CH2_DESC_PTR        IXP2000_PCI_CSR(0xAC)
 226 #define IXP2000_PCI_CH2_CNTRL           IXP2000_PCI_CSR(0xB0)
 227 #define IXP2000_PCI_CH2_ME_PARAM        IXP2000_PCI_CSR(0xB4)
 228 #define IXP2000_PCI_CH3_BYTE_CNT        IXP2000_PCI_CSR(0xC0)
 229 #define IXP2000_PCI_CH3_ADDR            IXP2000_PCI_CSR(0xC4)
 230 #define IXP2000_PCI_CH3_DRAM_ADDR       IXP2000_PCI_CSR(0xC8)
 231 #define IXP2000_PCI_CH3_DESC_PTR        IXP2000_PCI_CSR(0xCC)
 232 #define IXP2000_PCI_CH3_CNTRL           IXP2000_PCI_CSR(0xD0)
 233 #define IXP2000_PCI_CH3_ME_PARAM        IXP2000_PCI_CSR(0xD4)
 234 #define IXP2000_DMA_INF_MODE            IXP2000_PCI_CSR(0xE0)
 235 /*
 236  * Size masks for BARs
 237  */
 238 #define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
 239 #define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
 240 /*
 241  * Control and uEngine related
 242  */
 243 #define IXP2000_PCI_CONTROL             IXP2000_PCI_CSR(0x13C)
 244 #define IXP2000_PCI_ADDR_EXT            IXP2000_PCI_CSR(0x140)
 245 #define IXP2000_PCI_ME_PUSH_STATUS      IXP2000_PCI_CSR(0x148)
 246 #define IXP2000_PCI_ME_PUSH_EN          IXP2000_PCI_CSR(0x14C)
 247 #define IXP2000_PCI_ERR_STATUS          IXP2000_PCI_CSR(0x150)
 248 #define IXP2000_PCI_ERR_ENABLE          IXP2000_PCI_CSR(0x154)
 249 /*
 250  * Inbound PCI interrupt control
 251  */
 252 #define IXP2000_PCI_XSCALE_INT_STATUS   IXP2000_PCI_CSR(0x158)
 253 #define IXP2000_PCI_XSCALE_INT_ENABLE   IXP2000_PCI_CSR(0x15C)
 254
 255 #define IXP2000_PCICNTL_PNR             (1<<17) /* PCI not Reset bit of PCI_CONTROL */
 256 #define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Central function bit */
 257 #define IXP2000_XSCALE_INT              (1<<1)  /* Interrupt from XScale to PCI */
 258
 259 /* These are from the IRQ register in the PCI ISR register */
 260 #define PCI_CONTROL_BE_DEO              (1 << 22)       /* Big Endian Data Enable Out */
 261 #define PCI_CONTROL_BE_DEI              (1 << 21)       /* Big Endian Data Enable In  */
 262 #define PCI_CONTROL_BE_BEO              (1 << 20)       /* Big Endian Byte Enable Out */
 263 #define PCI_CONTROL_BE_BEI              (1 << 19)       /* Big Endian Byte Enable In  */
 264 #define PCI_CONTROL_IEE                 (1 << 17)       /* I/O cycle Endian swap Enable */
 265
 266 #define IXP2000_PCI_RST_REL             (1 << 2)
 267 #define CFG_RST_DIR                     (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
 268 #define CFG_PCI_BOOT_HOST               (1 << 2)
 269 #define CFG_BOOT_PROM                   (1 << 1)
 270
 271 /*
 272  * SlowPort CSRs
 273  *
 274  * The slowport is used to access things like flash, SONET framer control
 275  * ports, slave microprocessors, CPLDs, and others of chip memory mapped
 276  * peripherals.
 277  */
 278 #define SLOWPORT_CSR(x)         (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
 279
 280 #define IXP2000_SLOWPORT_CCR            SLOWPORT_CSR(0x00)
 281 #define IXP2000_SLOWPORT_WTC1           SLOWPORT_CSR(0x04)
 282 #define IXP2000_SLOWPORT_WTC2           SLOWPORT_CSR(0x08)
 283 #define IXP2000_SLOWPORT_RTC1           SLOWPORT_CSR(0x0c)
 284 #define IXP2000_SLOWPORT_RTC2           SLOWPORT_CSR(0x10)
 285 #define IXP2000_SLOWPORT_FSR            SLOWPORT_CSR(0x14)
 286 #define IXP2000_SLOWPORT_PCR            SLOWPORT_CSR(0x18)
 287 #define IXP2000_SLOWPORT_ADC            SLOWPORT_CSR(0x1C)
 288 #define IXP2000_SLOWPORT_FAC            SLOWPORT_CSR(0x20)
 289 #define IXP2000_SLOWPORT_FRM            SLOWPORT_CSR(0x24)
 290 #define IXP2000_SLOWPORT_FIN            SLOWPORT_CSR(0x28)
 291
 292 /*
 293  * CCR values.
 294  * The CCR configures the clock division for the slowport interface.
 295  */
 296 #define SLOWPORT_CCR_DIV_1              0x00
 297 #define SLOWPORT_CCR_DIV_2              0x01
 298 #define SLOWPORT_CCR_DIV_4              0x02
 299 #define SLOWPORT_CCR_DIV_6              0x03
 300 #define SLOWPORT_CCR_DIV_8              0x04
 301 #define SLOWPORT_CCR_DIV_10             0x05
 302 #define SLOWPORT_CCR_DIV_12             0x06
 303 #define SLOWPORT_CCR_DIV_14             0x07
 304 #define SLOWPORT_CCR_DIV_16             0x08
 305 #define SLOWPORT_CCR_DIV_18             0x09
 306 #define SLOWPORT_CCR_DIV_20             0x0a
 307 #define SLOWPORT_CCR_DIV_22             0x0b
 308 #define SLOWPORT_CCR_DIV_24             0x0c
 309 #define SLOWPORT_CCR_DIV_26             0x0d
 310 #define SLOWPORT_CCR_DIV_28             0x0e
 311 #define SLOWPORT_CCR_DIV_30             0x0f
 312
 313 /*
 314  * PCR values.  PCR configure the mode of the interface.
 315  */
 316 #define SLOWPORT_MODE_FLASH             0x00
 317 #define SLOWPORT_MODE_LUCENT            0x01
 318 #define SLOWPORT_MODE_PMC_SIERRA        0x02
 319 #define SLOWPORT_MODE_INTEL_UP          0x03
 320 #define SLOWPORT_MODE_MOTOROLA_UP       0x04
 321
 322 /*
 323  * ADC values.  Defines data and address bus widths.
 324  */
 325 #define SLOWPORT_ADDR_WIDTH_8           0x00
 326 #define SLOWPORT_ADDR_WIDTH_16          0x01
 327 #define SLOWPORT_ADDR_WIDTH_24          0x02
 328 #define SLOWPORT_ADDR_WIDTH_32          0x03
 329 #define SLOWPORT_DATA_WIDTH_8           0x00
 330 #define SLOWPORT_DATA_WIDTH_16          0x10
 331 #define SLOWPORT_DATA_WIDTH_24          0x20
 332 #define SLOWPORT_DATA_WIDTH_32          0x30
 333
 334 /*
 335  * Masks and shifts for various fields in the WTC and RTC registers.
 336  */
 337 #define SLOWPORT_WRTC_MASK_HD           0x0003
 338 #define SLOWPORT_WRTC_MASK_SU           0x003c
 339 #define SLOWPORT_WRTC_MASK_PW           0x03c0
 340
 341 #define SLOWPORT_WRTC_SHIFT_HD          0x00
 342 #define SLOWPORT_WRTC_SHIFT_SU          0x02
 343 #define SLOWPORT_WRTC_SHFIT_PW          0x06
 344
 345
 346 /*
 347  * GPIO registers & GPIO interface.
 348  */
 349 #define IXP2000_GPIO_REG(x)             ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
 350 #define IXP2000_GPIO_PLR                IXP2000_GPIO_REG(0x00)
 351 #define IXP2000_GPIO_PDPR               IXP2000_GPIO_REG(0x04)
 352 #define IXP2000_GPIO_PDSR               IXP2000_GPIO_REG(0x08)
 353 #define IXP2000_GPIO_PDCR               IXP2000_GPIO_REG(0x0c)
 354 #define IXP2000_GPIO_POPR               IXP2000_GPIO_REG(0x10)
 355 #define IXP2000_GPIO_POSR               IXP2000_GPIO_REG(0x14)
 356 #define IXP2000_GPIO_POCR               IXP2000_GPIO_REG(0x18)
 357 #define IXP2000_GPIO_REDR               IXP2000_GPIO_REG(0x1c)
 358 #define IXP2000_GPIO_FEDR               IXP2000_GPIO_REG(0x20)
 359 #define IXP2000_GPIO_EDSR               IXP2000_GPIO_REG(0x24)
 360 #define IXP2000_GPIO_LSHR               IXP2000_GPIO_REG(0x28)
 361 #define IXP2000_GPIO_LSLR               IXP2000_GPIO_REG(0x2c)
 362 #define IXP2000_GPIO_LDSR               IXP2000_GPIO_REG(0x30)
 363 #define IXP2000_GPIO_INER               IXP2000_GPIO_REG(0x34)
 364 #define IXP2000_GPIO_INSR               IXP2000_GPIO_REG(0x38)
 365 #define IXP2000_GPIO_INCR               IXP2000_GPIO_REG(0x3c)
 366 #define IXP2000_GPIO_INST               IXP2000_GPIO_REG(0x40)
 367
 368 /*
 369  * "Global" registers...whatever that's supposed to mean.
 370  */
 371 #define GLOBAL_REG_BASE                 (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
 372 #define GLOBAL_REG(x)                   (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
 373
 374 #define IXP2000_MAJ_PROD_TYPE_MASK      0x001F0000
 375 #define IXP2000_MAJ_PROD_TYPE_IXP2000   0x00000000
 376 #define IXP2000_MIN_PROD_TYPE_MASK      0x0000FF00
 377 #define IXP2000_MIN_PROD_TYPE_IXP2400   0x00000200
 378 #define IXP2000_MIN_PROD_TYPE_IXP2850   0x00000100
 379 #define IXP2000_MIN_PROD_TYPE_IXP2800   0x00000000
 380 #define IXP2000_MAJ_REV_MASK            0x000000F0
 381 #define IXP2000_MIN_REV_MASK            0x0000000F
 382 #define IXP2000_PROD_ID_MASK            0xFFFFFFFF
 383
 384 #define IXP2000_PRODUCT_ID              GLOBAL_REG(0x00)
 385 #define IXP2000_MISC_CONTROL            GLOBAL_REG(0x04)
 386 #define IXP2000_MSF_CLK_CNTRL           GLOBAL_REG(0x08)
 387 #define IXP2000_RESET0                  GLOBAL_REG(0x0c)
 388 #define IXP2000_RESET1                  GLOBAL_REG(0x10)
 389 #define IXP2000_CCR                     GLOBAL_REG(0x14)
 390 #define IXP2000_STRAP_OPTIONS           GLOBAL_REG(0x18)
 391
 392 #define RSTALL                          (1 << 16)
 393 #define WDT_RESET_ENABLE                0x01000000
 394
 395
 396 /*
 397  * MSF registers.  The IXP2400 and IXP2800 have somewhat different MSF
 398  * units, but the registers that differ between the two don't overlap,
 399  * so we can have one register list for both.
 400  */
 401 #define IXP2000_MSF_REG(x)                      ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
 402 #define IXP2000_MSF_RX_CONTROL                  IXP2000_MSF_REG(0x0000)
 403 #define IXP2000_MSF_TX_CONTROL                  IXP2000_MSF_REG(0x0004)
 404 #define IXP2000_MSF_INTERRUPT_STATUS            IXP2000_MSF_REG(0x0008)
 405 #define IXP2000_MSF_INTERRUPT_ENABLE            IXP2000_MSF_REG(0x000c)
 406 #define IXP2000_MSF_CSIX_TYPE_MAP               IXP2000_MSF_REG(0x0010)
 407 #define IXP2000_MSF_FC_EGRESS_STATUS            IXP2000_MSF_REG(0x0014)
 408 #define IXP2000_MSF_FC_INGRESS_STATUS           IXP2000_MSF_REG(0x0018)
 409 #define IXP2000_MSF_HWM_CONTROL                 IXP2000_MSF_REG(0x0024)
 410 #define IXP2000_MSF_FC_STATUS_OVERRIDE          IXP2000_MSF_REG(0x0028)
 411 #define IXP2000_MSF_CLOCK_CONTROL               IXP2000_MSF_REG(0x002c)
 412 #define IXP2000_MSF_RX_PORT_MAP                 IXP2000_MSF_REG(0x0040)
 413 #define IXP2000_MSF_RBUF_ELEMENT_DONE           IXP2000_MSF_REG(0x0044)
 414 #define IXP2000_MSF_RX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0048)
 415 #define IXP2000_MSF_RX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0048)
 416 #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0        IXP2000_MSF_REG(0x0050)
 417 #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1        IXP2000_MSF_REG(0x0054)
 418 #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2        IXP2000_MSF_REG(0x0058)
 419 #define IXP2000_MSF_TX_SEQUENCE_0               IXP2000_MSF_REG(0x0060)
 420 #define IXP2000_MSF_TX_SEQUENCE_1               IXP2000_MSF_REG(0x0064)
 421 #define IXP2000_MSF_TX_SEQUENCE_2               IXP2000_MSF_REG(0x0068)
 422 #define IXP2000_MSF_TX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0070)
 423 #define IXP2000_MSF_TX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0070)
 424 #define IXP2000_MSF_RX_UP_CONTROL_0             IXP2000_MSF_REG(0x0080)
 425 #define IXP2000_MSF_RX_UP_CONTROL_1             IXP2000_MSF_REG(0x0084)
 426 #define IXP2000_MSF_RX_UP_CONTROL_2             IXP2000_MSF_REG(0x0088)
 427 #define IXP2000_MSF_RX_UP_CONTROL_3             IXP2000_MSF_REG(0x008c)
 428 #define IXP2000_MSF_TX_UP_CONTROL_0             IXP2000_MSF_REG(0x0090)
 429 #define IXP2000_MSF_TX_UP_CONTROL_1             IXP2000_MSF_REG(0x0094)
 430 #define IXP2000_MSF_TX_UP_CONTROL_2             IXP2000_MSF_REG(0x0098)
 431 #define IXP2000_MSF_TX_UP_CONTROL_3             IXP2000_MSF_REG(0x009c)
 432 #define IXP2000_MSF_TRAIN_DATA                  IXP2000_MSF_REG(0x00a0)
 433 #define IXP2000_MSF_TRAIN_CALENDAR              IXP2000_MSF_REG(0x00a4)
 434 #define IXP2000_MSF_TRAIN_FLOW_CONTROL          IXP2000_MSF_REG(0x00a8)
 435 #define IXP2000_MSF_TX_CALENDAR_0               IXP2000_MSF_REG(0x1000)
 436 #define IXP2000_MSF_RX_PORT_CALENDAR_STATUS     IXP2000_MSF_REG(0x1400)
 437
 438
 439 #endif                          /* _IXP2000_H_ */