include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h

   1 #ifndef __iop_sw_spu_defs_h
   2 #define __iop_sw_spu_defs_h
   3
   4 /*
   5  * This file is autogenerated from
   6  *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
   7  *     id:           <not found>
   8  *     last modfied: Mon Apr 11 16:10:19 2005
   9  *
  10  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
  11  *      id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
  12  * Any changes here will be lost.
  13  *
  14  * -*- buffer-read-only: t -*-
  15  */
  16 /* Main access macros */
  17 #ifndef REG_RD
  18 #define REG_RD( scope, inst, reg ) \
  19   REG_READ( reg_##scope##_##reg, \
  20             (inst) + REG_RD_ADDR_##scope##_##reg )
  21 #endif
  22
  23 #ifndef REG_WR
  24 #define REG_WR( scope, inst, reg, val ) \
  25   REG_WRITE( reg_##scope##_##reg, \
  26              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  27 #endif
  28
  29 #ifndef REG_RD_VECT
  30 #define REG_RD_VECT( scope, inst, reg, index ) \
  31   REG_READ( reg_##scope##_##reg, \
  32             (inst) + REG_RD_ADDR_##scope##_##reg + \
  33             (index) * STRIDE_##scope##_##reg )
  34 #endif
  35
  36 #ifndef REG_WR_VECT
  37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  38   REG_WRITE( reg_##scope##_##reg, \
  39              (inst) + REG_WR_ADDR_##scope##_##reg + \
  40              (index) * STRIDE_##scope##_##reg, (val) )
  41 #endif
  42
  43 #ifndef REG_RD_INT
  44 #define REG_RD_INT( scope, inst, reg ) \
  45   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  46 #endif
  47
  48 #ifndef REG_WR_INT
  49 #define REG_WR_INT( scope, inst, reg, val ) \
  50   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  51 #endif
  52
  53 #ifndef REG_RD_INT_VECT
  54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  55   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  56             (index) * STRIDE_##scope##_##reg )
  57 #endif
  58
  59 #ifndef REG_WR_INT_VECT
  60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  61   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  62              (index) * STRIDE_##scope##_##reg, (val) )
  63 #endif
  64
  65 #ifndef REG_TYPE_CONV
  66 #define REG_TYPE_CONV( type, orgtype, val ) \
  67   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  68 #endif
  69
  70 #ifndef reg_page_size
  71 #define reg_page_size 8192
  72 #endif
  73
  74 #ifndef REG_ADDR
  75 #define REG_ADDR( scope, inst, reg ) \
  76   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  77 #endif
  78
  79 #ifndef REG_ADDR_VECT
  80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  81   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  82     (index) * STRIDE_##scope##_##reg )
  83 #endif
  84
  85 /* C-code for register scope iop_sw_spu */
  86
  87 /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
  88 typedef struct {
  89   unsigned int keep_owner  : 1;
  90   unsigned int cmd         : 2;
  91   unsigned int size        : 3;
  92   unsigned int wr_spu0_mem : 1;
  93   unsigned int wr_spu1_mem : 1;
  94   unsigned int dummy1      : 24;
  95 } reg_iop_sw_spu_rw_mc_ctrl;
  96 #define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0
  97 #define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0
  98
  99 /* Register rw_mc_data, scope iop_sw_spu, type rw */
 100 typedef struct {
 101   unsigned int val : 32;
 102 } reg_iop_sw_spu_rw_mc_data;
 103 #define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4
 104 #define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4
 105
 106 /* Register rw_mc_addr, scope iop_sw_spu, type rw */
 107 typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
 108 #define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8
 109 #define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8
 110
 111 /* Register rs_mc_data, scope iop_sw_spu, type rs */
 112 typedef unsigned int reg_iop_sw_spu_rs_mc_data;
 113 #define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12
 114
 115 /* Register r_mc_data, scope iop_sw_spu, type r */
 116 typedef unsigned int reg_iop_sw_spu_r_mc_data;
 117 #define REG_RD_ADDR_iop_sw_spu_r_mc_data 16
 118
 119 /* Register r_mc_stat, scope iop_sw_spu, type r */
 120 typedef struct {
 121   unsigned int busy_cpu      : 1;
 122   unsigned int busy_mpu      : 1;
 123   unsigned int busy_spu0     : 1;
 124   unsigned int busy_spu1     : 1;
 125   unsigned int owned_by_cpu  : 1;
 126   unsigned int owned_by_mpu  : 1;
 127   unsigned int owned_by_spu0 : 1;
 128   unsigned int owned_by_spu1 : 1;
 129   unsigned int dummy1        : 24;
 130 } reg_iop_sw_spu_r_mc_stat;
 131 #define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20
 132
 133 /* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
 134 typedef struct {
 135   unsigned int byte0 : 8;
 136   unsigned int byte1 : 8;
 137   unsigned int byte2 : 8;
 138   unsigned int byte3 : 8;
 139 } reg_iop_sw_spu_rw_bus0_clr_mask;
 140 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
 141 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
 142
 143 /* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
 144 typedef struct {
 145   unsigned int byte0 : 8;
 146   unsigned int byte1 : 8;
 147   unsigned int byte2 : 8;
 148   unsigned int byte3 : 8;
 149 } reg_iop_sw_spu_rw_bus0_set_mask;
 150 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28
 151 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28
 152
 153 /* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
 154 typedef struct {
 155   unsigned int byte0 : 1;
 156   unsigned int byte1 : 1;
 157   unsigned int byte2 : 1;
 158   unsigned int byte3 : 1;
 159   unsigned int dummy1 : 28;
 160 } reg_iop_sw_spu_rw_bus0_oe_clr_mask;
 161 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
 162 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
 163
 164 /* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
 165 typedef struct {
 166   unsigned int byte0 : 1;
 167   unsigned int byte1 : 1;
 168   unsigned int byte2 : 1;
 169   unsigned int byte3 : 1;
 170   unsigned int dummy1 : 28;
 171 } reg_iop_sw_spu_rw_bus0_oe_set_mask;
 172 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
 173 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
 174
 175 /* Register r_bus0_in, scope iop_sw_spu, type r */
 176 typedef unsigned int reg_iop_sw_spu_r_bus0_in;
 177 #define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40
 178
 179 /* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
 180 typedef struct {
 181   unsigned int byte0 : 8;
 182   unsigned int byte1 : 8;
 183   unsigned int byte2 : 8;
 184   unsigned int byte3 : 8;
 185 } reg_iop_sw_spu_rw_bus1_clr_mask;
 186 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
 187 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
 188
 189 /* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
 190 typedef struct {
 191   unsigned int byte0 : 8;
 192   unsigned int byte1 : 8;
 193   unsigned int byte2 : 8;
 194   unsigned int byte3 : 8;
 195 } reg_iop_sw_spu_rw_bus1_set_mask;
 196 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48
 197 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48
 198
 199 /* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
 200 typedef struct {
 201   unsigned int byte0 : 1;
 202   unsigned int byte1 : 1;
 203   unsigned int byte2 : 1;
 204   unsigned int byte3 : 1;
 205   unsigned int dummy1 : 28;
 206 } reg_iop_sw_spu_rw_bus1_oe_clr_mask;
 207 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
 208 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
 209
 210 /* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
 211 typedef struct {
 212   unsigned int byte0 : 1;
 213   unsigned int byte1 : 1;
 214   unsigned int byte2 : 1;
 215   unsigned int byte3 : 1;
 216   unsigned int dummy1 : 28;
 217 } reg_iop_sw_spu_rw_bus1_oe_set_mask;
 218 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
 219 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
 220
 221 /* Register r_bus1_in, scope iop_sw_spu, type r */
 222 typedef unsigned int reg_iop_sw_spu_r_bus1_in;
 223 #define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60
 224
 225 /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
 226 typedef struct {
 227   unsigned int val : 32;
 228 } reg_iop_sw_spu_rw_gio_clr_mask;
 229 #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64
 230 #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64
 231
 232 /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
 233 typedef struct {
 234   unsigned int val : 32;
 235 } reg_iop_sw_spu_rw_gio_set_mask;
 236 #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68
 237 #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68
 238
 239 /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
 240 typedef struct {
 241   unsigned int val : 32;
 242 } reg_iop_sw_spu_rw_gio_oe_clr_mask;
 243 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
 244 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
 245
 246 /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
 247 typedef struct {
 248   unsigned int val : 32;
 249 } reg_iop_sw_spu_rw_gio_oe_set_mask;
 250 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
 251 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
 252
 253 /* Register r_gio_in, scope iop_sw_spu, type r */
 254 typedef unsigned int reg_iop_sw_spu_r_gio_in;
 255 #define REG_RD_ADDR_iop_sw_spu_r_gio_in 80
 256
 257 /* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
 258 typedef struct {
 259   unsigned int byte0 : 8;
 260   unsigned int byte1 : 8;
 261   unsigned int dummy1 : 16;
 262 } reg_iop_sw_spu_rw_bus0_clr_mask_lo;
 263 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
 264 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
 265
 266 /* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
 267 typedef struct {
 268   unsigned int byte2 : 8;
 269   unsigned int byte3 : 8;
 270   unsigned int dummy1 : 16;
 271 } reg_iop_sw_spu_rw_bus0_clr_mask_hi;
 272 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
 273 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
 274
 275 /* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
 276 typedef struct {
 277   unsigned int byte0 : 8;
 278   unsigned int byte1 : 8;
 279   unsigned int dummy1 : 16;
 280 } reg_iop_sw_spu_rw_bus0_set_mask_lo;
 281 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
 282 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
 283
 284 /* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
 285 typedef struct {
 286   unsigned int byte2 : 8;
 287   unsigned int byte3 : 8;
 288   unsigned int dummy1 : 16;
 289 } reg_iop_sw_spu_rw_bus0_set_mask_hi;
 290 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
 291 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
 292
 293 /* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
 294 typedef struct {
 295   unsigned int byte0 : 8;
 296   unsigned int byte1 : 8;
 297   unsigned int dummy1 : 16;
 298 } reg_iop_sw_spu_rw_bus1_clr_mask_lo;
 299 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
 300 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
 301
 302 /* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
 303 typedef struct {
 304   unsigned int byte2 : 8;
 305   unsigned int byte3 : 8;
 306   unsigned int dummy1 : 16;
 307 } reg_iop_sw_spu_rw_bus1_clr_mask_hi;
 308 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
 309 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
 310
 311 /* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
 312 typedef struct {
 313   unsigned int byte0 : 8;
 314   unsigned int byte1 : 8;
 315   unsigned int dummy1 : 16;
 316 } reg_iop_sw_spu_rw_bus1_set_mask_lo;
 317 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
 318 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
 319
 320 /* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
 321 typedef struct {
 322   unsigned int byte2 : 8;
 323   unsigned int byte3 : 8;
 324   unsigned int dummy1 : 16;
 325 } reg_iop_sw_spu_rw_bus1_set_mask_hi;
 326 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
 327 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
 328
 329 /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
 330 typedef struct {
 331   unsigned int val : 16;
 332   unsigned int dummy1 : 16;
 333 } reg_iop_sw_spu_rw_gio_clr_mask_lo;
 334 #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
 335 #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
 336
 337 /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
 338 typedef struct {
 339   unsigned int val : 16;
 340   unsigned int dummy1 : 16;
 341 } reg_iop_sw_spu_rw_gio_clr_mask_hi;
 342 #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
 343 #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
 344
 345 /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
 346 typedef struct {
 347   unsigned int val : 16;
 348   unsigned int dummy1 : 16;
 349 } reg_iop_sw_spu_rw_gio_set_mask_lo;
 350 #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
 351 #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
 352
 353 /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
 354 typedef struct {
 355   unsigned int val : 16;
 356   unsigned int dummy1 : 16;
 357 } reg_iop_sw_spu_rw_gio_set_mask_hi;
 358 #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
 359 #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
 360
 361 /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
 362 typedef struct {
 363   unsigned int val : 16;
 364   unsigned int dummy1 : 16;
 365 } reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
 366 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
 367 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
 368
 369 /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
 370 typedef struct {
 371   unsigned int val : 16;
 372   unsigned int dummy1 : 16;
 373 } reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
 374 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
 375 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
 376
 377 /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
 378 typedef struct {
 379   unsigned int val : 16;
 380   unsigned int dummy1 : 16;
 381 } reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
 382 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
 383 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
 384
 385 /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
 386 typedef struct {
 387   unsigned int val : 16;
 388   unsigned int dummy1 : 16;
 389 } reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
 390 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
 391 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
 392
 393 /* Register rw_cpu_intr, scope iop_sw_spu, type rw */
 394 typedef struct {
 395   unsigned int intr0  : 1;
 396   unsigned int intr1  : 1;
 397   unsigned int intr2  : 1;
 398   unsigned int intr3  : 1;
 399   unsigned int intr4  : 1;
 400   unsigned int intr5  : 1;
 401   unsigned int intr6  : 1;
 402   unsigned int intr7  : 1;
 403   unsigned int intr8  : 1;
 404   unsigned int intr9  : 1;
 405   unsigned int intr10 : 1;
 406   unsigned int intr11 : 1;
 407   unsigned int intr12 : 1;
 408   unsigned int intr13 : 1;
 409   unsigned int intr14 : 1;
 410   unsigned int intr15 : 1;
 411   unsigned int dummy1 : 16;
 412 } reg_iop_sw_spu_rw_cpu_intr;
 413 #define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148
 414 #define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148
 415
 416 /* Register r_cpu_intr, scope iop_sw_spu, type r */
 417 typedef struct {
 418   unsigned int intr0  : 1;
 419   unsigned int intr1  : 1;
 420   unsigned int intr2  : 1;
 421   unsigned int intr3  : 1;
 422   unsigned int intr4  : 1;
 423   unsigned int intr5  : 1;
 424   unsigned int intr6  : 1;
 425   unsigned int intr7  : 1;
 426   unsigned int intr8  : 1;
 427   unsigned int intr9  : 1;
 428   unsigned int intr10 : 1;
 429   unsigned int intr11 : 1;
 430   unsigned int intr12 : 1;
 431   unsigned int intr13 : 1;
 432   unsigned int intr14 : 1;
 433   unsigned int intr15 : 1;
 434   unsigned int dummy1 : 16;
 435 } reg_iop_sw_spu_r_cpu_intr;
 436 #define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152
 437
 438 /* Register r_hw_intr, scope iop_sw_spu, type r */
 439 typedef struct {
 440   unsigned int trigger_grp0    : 1;
 441   unsigned int trigger_grp1    : 1;
 442   unsigned int trigger_grp2    : 1;
 443   unsigned int trigger_grp3    : 1;
 444   unsigned int trigger_grp4    : 1;
 445   unsigned int trigger_grp5    : 1;
 446   unsigned int trigger_grp6    : 1;
 447   unsigned int trigger_grp7    : 1;
 448   unsigned int timer_grp0      : 1;
 449   unsigned int timer_grp1      : 1;
 450   unsigned int timer_grp2      : 1;
 451   unsigned int timer_grp3      : 1;
 452   unsigned int fifo_out0       : 1;
 453   unsigned int fifo_out0_extra : 1;
 454   unsigned int fifo_in0        : 1;
 455   unsigned int fifo_in0_extra  : 1;
 456   unsigned int fifo_out1       : 1;
 457   unsigned int fifo_out1_extra : 1;
 458   unsigned int fifo_in1        : 1;
 459   unsigned int fifo_in1_extra  : 1;
 460   unsigned int dmc_out0        : 1;
 461   unsigned int dmc_in0         : 1;
 462   unsigned int dmc_out1        : 1;
 463   unsigned int dmc_in1         : 1;
 464   unsigned int dummy1          : 8;
 465 } reg_iop_sw_spu_r_hw_intr;
 466 #define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156
 467
 468 /* Register rw_mpu_intr, scope iop_sw_spu, type rw */
 469 typedef struct {
 470   unsigned int intr0  : 1;
 471   unsigned int intr1  : 1;
 472   unsigned int intr2  : 1;
 473   unsigned int intr3  : 1;
 474   unsigned int intr4  : 1;
 475   unsigned int intr5  : 1;
 476   unsigned int intr6  : 1;
 477   unsigned int intr7  : 1;
 478   unsigned int intr8  : 1;
 479   unsigned int intr9  : 1;
 480   unsigned int intr10 : 1;
 481   unsigned int intr11 : 1;
 482   unsigned int intr12 : 1;
 483   unsigned int intr13 : 1;
 484   unsigned int intr14 : 1;
 485   unsigned int intr15 : 1;
 486   unsigned int dummy1 : 16;
 487 } reg_iop_sw_spu_rw_mpu_intr;
 488 #define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160
 489 #define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160
 490
 491 /* Register r_mpu_intr, scope iop_sw_spu, type r */
 492 typedef struct {
 493   unsigned int intr0            : 1;
 494   unsigned int intr1            : 1;
 495   unsigned int intr2            : 1;
 496   unsigned int intr3            : 1;
 497   unsigned int intr4            : 1;
 498   unsigned int intr5            : 1;
 499   unsigned int intr6            : 1;
 500   unsigned int intr7            : 1;
 501   unsigned int intr8            : 1;
 502   unsigned int intr9            : 1;
 503   unsigned int intr10           : 1;
 504   unsigned int intr11           : 1;
 505   unsigned int intr12           : 1;
 506   unsigned int intr13           : 1;
 507   unsigned int intr14           : 1;
 508   unsigned int intr15           : 1;
 509   unsigned int other_spu_intr0  : 1;
 510   unsigned int other_spu_intr1  : 1;
 511   unsigned int other_spu_intr2  : 1;
 512   unsigned int other_spu_intr3  : 1;
 513   unsigned int other_spu_intr4  : 1;
 514   unsigned int other_spu_intr5  : 1;
 515   unsigned int other_spu_intr6  : 1;
 516   unsigned int other_spu_intr7  : 1;
 517   unsigned int other_spu_intr8  : 1;
 518   unsigned int other_spu_intr9  : 1;
 519   unsigned int other_spu_intr10 : 1;
 520   unsigned int other_spu_intr11 : 1;
 521   unsigned int other_spu_intr12 : 1;
 522   unsigned int other_spu_intr13 : 1;
 523   unsigned int other_spu_intr14 : 1;
 524   unsigned int other_spu_intr15 : 1;
 525 } reg_iop_sw_spu_r_mpu_intr;
 526 #define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164
 527
 528
 529 /* Constants */
 530 enum {
 531   regk_iop_sw_spu_copy                     = 0x00000000,
 532   regk_iop_sw_spu_no                       = 0x00000000,
 533   regk_iop_sw_spu_nop                      = 0x00000000,
 534   regk_iop_sw_spu_rd                       = 0x00000002,
 535   regk_iop_sw_spu_reg_copy                 = 0x00000001,
 536   regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000,
 537   regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000,
 538   regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000,
 539   regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000,
 540   regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000,
 541   regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000,
 542   regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000,
 543   regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000,
 544   regk_iop_sw_spu_rw_gio_clr_mask_default  = 0x00000000,
 545   regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
 546   regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
 547   regk_iop_sw_spu_rw_gio_set_mask_default  = 0x00000000,
 548   regk_iop_sw_spu_set                      = 0x00000001,
 549   regk_iop_sw_spu_wr                       = 0x00000003,
 550   regk_iop_sw_spu_yes                      = 0x00000001
 551 };
 552 #endif /* __iop_sw_spu_defs_h */