include/asm-frv/spr-regs.h

   1 /* spr-regs.h: special-purpose registers on the FRV
   2  *
   3  * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef _ASM_SPR_REGS_H
  13 #define _ASM_SPR_REGS_H
  14
  15 /*
  16  * PSR - Processor Status Register
  17  */
  18 #define PSR_ET                  0x00000001      /* enable interrupts/exceptions flag */
  19 #define PSR_PS                  0x00000002      /* previous supervisor mode flag */
  20 #define PSR_S                   0x00000004      /* supervisor mode flag */
  21 #define PSR_PIL                 0x00000078      /* processor external interrupt level */
  22 #define PSR_PIL_0               0x00000000      /* - no interrupt in progress */
  23 #define PSR_PIL_13              0x00000068      /* - debugging only */
  24 #define PSR_PIL_14              0x00000070      /* - debugging in progress */
  25 #define PSR_PIL_15              0x00000078      /* - NMI in progress */
  26 #define PSR_EM                  0x00000080      /* enable media operation */
  27 #define PSR_EF                  0x00000100      /* enable FPU operation */
  28 #define PSR_BE                  0x00001000      /* endianness mode */
  29 #define PSR_BE_LE               0x00000000      /* - little endian mode */
  30 #define PSR_BE_BE               0x00001000      /* - big endian mode */
  31 #define PSR_CM                  0x00002000      /* conditional mode */
  32 #define PSR_NEM                 0x00004000      /* non-excepting mode */
  33 #define PSR_ICE                 0x00010000      /* in-circuit emulation mode */
  34 #define PSR_VERSION_SHIFT       24              /* CPU silicon ID */
  35 #define PSR_IMPLE_SHIFT         28              /* CPU core ID */
  36
  37 #define PSR_VERSION(psr)        (((psr) >> PSR_VERSION_SHIFT) & 0xf)
  38 #define PSR_IMPLE(psr)          (((psr) >> PSR_IMPLE_SHIFT) & 0xf)
  39
  40 #define PSR_IMPLE_FR401         0x2
  41 #define PSR_VERSION_FR401_MB93401       0x0
  42 #define PSR_VERSION_FR401_MB93401A      0x1
  43 #define PSR_VERSION_FR401_MB93403       0x2
  44
  45 #define PSR_IMPLE_FR405         0x4
  46 #define PSR_VERSION_FR405_MB93405       0x0
  47
  48 #define PSR_IMPLE_FR451         0x5
  49 #define PSR_VERSION_FR451_MB93451       0x0
  50
  51 #define PSR_IMPLE_FR501         0x1
  52 #define PSR_VERSION_FR501_MB93501       0x1
  53 #define PSR_VERSION_FR501_MB93501A      0x2
  54
  55 #define PSR_IMPLE_FR551         0x3
  56 #define PSR_VERSION_FR551_MB93555       0x1
  57
  58 #define __get_PSR()     ({ unsigned long x; asm volatile("movsg psr,%0" : "=r"(x)); x; })
  59 #define __set_PSR(V)    do { asm volatile("movgs %0,psr" : : "r"(V)); } while(0)
  60
  61 /*
  62  * TBR - Trap Base Register
  63  */
  64 #define TBR_TT                  0x00000ff0
  65 #define TBR_TT_INSTR_MMU_MISS   (0x01 << 4)
  66 #define TBR_TT_INSTR_ACC_ERROR  (0x02 << 4)
  67 #define TBR_TT_INSTR_ACC_EXCEP  (0x03 << 4)
  68 #define TBR_TT_PRIV_INSTR       (0x06 << 4)
  69 #define TBR_TT_ILLEGAL_INSTR    (0x07 << 4)
  70 #define TBR_TT_FP_EXCEPTION     (0x0d << 4)
  71 #define TBR_TT_MP_EXCEPTION     (0x0e << 4)
  72 #define TBR_TT_DATA_ACC_ERROR   (0x11 << 4)
  73 #define TBR_TT_DATA_MMU_MISS    (0x12 << 4)
  74 #define TBR_TT_DATA_ACC_EXCEP   (0x13 << 4)
  75 #define TBR_TT_DATA_STR_ERROR   (0x14 << 4)
  76 #define TBR_TT_DIVISION_EXCEP   (0x17 << 4)
  77 #define TBR_TT_COMMIT_EXCEP     (0x19 << 4)
  78 #define TBR_TT_INSTR_TLB_MISS   (0x1a << 4)
  79 #define TBR_TT_DATA_TLB_MISS    (0x1b << 4)
  80 #define TBR_TT_DATA_DAT_EXCEP   (0x1d << 4)
  81 #define TBR_TT_DECREMENT_TIMER  (0x1f << 4)
  82 #define TBR_TT_COMPOUND_EXCEP   (0x20 << 4)
  83 #define TBR_TT_INTERRUPT_1      (0x21 << 4)
  84 #define TBR_TT_INTERRUPT_2      (0x22 << 4)
  85 #define TBR_TT_INTERRUPT_3      (0x23 << 4)
  86 #define TBR_TT_INTERRUPT_4      (0x24 << 4)
  87 #define TBR_TT_INTERRUPT_5      (0x25 << 4)
  88 #define TBR_TT_INTERRUPT_6      (0x26 << 4)
  89 #define TBR_TT_INTERRUPT_7      (0x27 << 4)
  90 #define TBR_TT_INTERRUPT_8      (0x28 << 4)
  91 #define TBR_TT_INTERRUPT_9      (0x29 << 4)
  92 #define TBR_TT_INTERRUPT_10     (0x2a << 4)
  93 #define TBR_TT_INTERRUPT_11     (0x2b << 4)
  94 #define TBR_TT_INTERRUPT_12     (0x2c << 4)
  95 #define TBR_TT_INTERRUPT_13     (0x2d << 4)
  96 #define TBR_TT_INTERRUPT_14     (0x2e << 4)
  97 #define TBR_TT_INTERRUPT_15     (0x2f << 4)
  98 #define TBR_TT_TRAP0            (0x80 << 4)
  99 #define TBR_TT_TRAP1            (0x81 << 4)
 100 #define TBR_TT_TRAP2            (0x82 << 4)
 101 #define TBR_TT_TRAP126          (0xfe << 4)
 102 #define TBR_TT_BREAK            (0xff << 4)
 103
 104 #define __get_TBR()     ({ unsigned long x; asm volatile("movsg tbr,%0" : "=r"(x)); x; })
 105
 106 /*
 107  * HSR0 - Hardware Status Register 0
 108  */
 109 #define HSR0_PDM                0x00000007      /* power down mode */
 110 #define HSR0_PDM_NORMAL         0x00000000      /* - normal mode */
 111 #define HSR0_PDM_CORE_SLEEP     0x00000001      /* - CPU core sleep mode */
 112 #define HSR0_PDM_BUS_SLEEP      0x00000003      /* - bus sleep mode */
 113 #define HSR0_PDM_PLL_RUN        0x00000005      /* - PLL run */
 114 #define HSR0_PDM_PLL_STOP       0x00000007      /* - PLL stop */
 115 #define HSR0_GRLE               0x00000040      /* GR lower register set enable */
 116 #define HSR0_GRHE               0x00000080      /* GR higher register set enable */
 117 #define HSR0_FRLE               0x00000100      /* FR lower register set enable */
 118 #define HSR0_FRHE               0x00000200      /* FR higher register set enable */
 119 #define HSR0_GRN                0x00000400      /* GR quantity */
 120 #define HSR0_GRN_64             0x00000000      /* - 64 GR registers */
 121 #define HSR0_GRN_32             0x00000400      /* - 32 GR registers */
 122 #define HSR0_FRN                0x00000800      /* FR quantity */
 123 #define HSR0_FRN_64             0x00000000      /* - 64 FR registers */
 124 #define HSR0_FRN_32             0x00000800      /* - 32 FR registers */
 125 #define HSR0_SA                 0x00001000      /* start address (RAMBOOT#) */
 126 #define HSR0_ETMI               0x00008000      /* enable TIMERI (64-bit up timer) */
 127 #define HSR0_ETMD               0x00004000      /* enable TIMERD (32-bit down timer) */
 128 #define HSR0_PEDAT              0x00010000      /* previous DAT mode */
 129 #define HSR0_XEDAT              0x00020000      /* exception DAT mode */
 130 #define HSR0_EDAT               0x00080000      /* enable DAT mode */
 131 #define HSR0_RME                0x00400000      /* enable RAM mode */
 132 #define HSR0_EMEM               0x00800000      /* enable MMU_Miss mask */
 133 #define HSR0_EXMMU              0x01000000      /* enable extended MMU mode */
 134 #define HSR0_EDMMU              0x02000000      /* enable data MMU */
 135 #define HSR0_EIMMU              0x04000000      /* enable instruction MMU */
 136 #define HSR0_CBM                0x08000000      /* copy back mode */
 137 #define HSR0_CBM_WRITE_THRU     0x00000000      /* - write through */
 138 #define HSR0_CBM_COPY_BACK      0x08000000      /* - copy back */
 139 #define HSR0_NWA                0x10000000      /* no write allocate */
 140 #define HSR0_DCE                0x40000000      /* data cache enable */
 141 #define HSR0_ICE                0x80000000      /* instruction cache enable */
 142
 143 #define __get_HSR(R)    ({ unsigned long x; asm volatile("movsg hsr"#R",%0" : "=r"(x)); x; })
 144 #define __set_HSR(R,V)  do { asm volatile("movgs %0,hsr"#R : : "r"(V)); } while(0)
 145
 146 /*
 147  * CCR - Condition Codes Register
 148  */
 149 #define CCR_FCC0                0x0000000f      /* FP/Media condition 0 (fcc0 reg) */
 150 #define CCR_FCC1                0x000000f0      /* FP/Media condition 1 (fcc1 reg) */
 151 #define CCR_FCC2                0x00000f00      /* FP/Media condition 2 (fcc2 reg) */
 152 #define CCR_FCC3                0x0000f000      /* FP/Media condition 3 (fcc3 reg) */
 153 #define CCR_ICC0                0x000f0000      /* Integer condition 0 (icc0 reg) */
 154 #define CCR_ICC0_C              0x00010000      /* - Carry flag */
 155 #define CCR_ICC0_V              0x00020000      /* - Overflow flag */
 156 #define CCR_ICC0_Z              0x00040000      /* - Zero flag */
 157 #define CCR_ICC0_N              0x00080000      /* - Negative flag */
 158 #define CCR_ICC1                0x00f00000      /* Integer condition 1 (icc1 reg) */
 159 #define CCR_ICC2                0x0f000000      /* Integer condition 2 (icc2 reg) */
 160 #define CCR_ICC3                0xf0000000      /* Integer condition 3 (icc3 reg) */
 161
 162 /*
 163  * CCCR - Condition Codes for Conditional Instructions Register
 164  */
 165 #define CCCR_CC0                0x00000003      /* condition 0 (cc0 reg) */
 166 #define CCCR_CC0_FALSE          0x00000002      /* - condition is false */
 167 #define CCCR_CC0_TRUE           0x00000003      /* - condition is true */
 168 #define CCCR_CC1                0x0000000c      /* condition 1 (cc1 reg) */
 169 #define CCCR_CC2                0x00000030      /* condition 2 (cc2 reg) */
 170 #define CCCR_CC3                0x000000c0      /* condition 3 (cc3 reg) */
 171 #define CCCR_CC4                0x00000300      /* condition 4 (cc4 reg) */
 172 #define CCCR_CC5                0x00000c00      /* condition 5 (cc5 reg) */
 173 #define CCCR_CC6                0x00003000      /* condition 6 (cc6 reg) */
 174 #define CCCR_CC7                0x0000c000      /* condition 7 (cc7 reg) */
 175
 176 /*
 177  * ISR - Integer Status Register
 178  */
 179 #define ISR_EMAM                0x00000001      /* memory misaligned access handling */
 180 #define ISR_EMAM_EXCEPTION      0x00000000      /* - generate exception */
 181 #define ISR_EMAM_FUDGE          0x00000001      /* - mask out invalid address bits */
 182 #define ISR_AEXC                0x00000004      /* accrued [overflow] exception */
 183 #define ISR_DTT                 0x00000018      /* division type trap */
 184 #define ISR_DTT_IGNORE          0x00000000      /* - ignore division error */
 185 #define ISR_DTT_DIVBYZERO       0x00000008      /* - generate exception */
 186 #define ISR_DTT_OVERFLOW        0x00000010      /* - record overflow */
 187 #define ISR_EDE                 0x00000020      /* enable division exception */
 188 #define ISR_PLI                 0x20000000      /* pre-load instruction information */
 189 #define ISR_QI                  0x80000000      /* quad data implementation information */
 190
 191 /*
 192  * EPCR0 - Exception PC Register
 193  */
 194 #define EPCR0_V                 0x00000001      /* register content validity indicator */
 195 #define EPCR0_PC                0xfffffffc      /* faulting instruction address */
 196
 197 /*
 198  * ESR0/14/15 - Exception Status Register
 199  */
 200 #define ESRx_VALID              0x00000001      /* register content validity indicator */
 201 #define ESRx_EC                 0x0000003e      /* exception type */
 202 #define ESRx_EC_DATA_STORE      0x00000000      /* - data_store_error */
 203 #define ESRx_EC_INSN_ACCESS     0x00000006      /* - instruction_access_error */
 204 #define ESRx_EC_PRIV_INSN       0x00000008      /* - privileged_instruction */
 205 #define ESRx_EC_ILL_INSN        0x0000000a      /* - illegal_instruction */
 206 #define ESRx_EC_MP_EXCEP        0x0000001c      /* - mp_exception */
 207 #define ESRx_EC_DATA_ACCESS     0x00000020      /* - data_access_error */
 208 #define ESRx_EC_DIVISION        0x00000026      /* - division_exception */
 209 #define ESRx_EC_ITLB_MISS       0x00000034      /* - instruction_access_TLB_miss */
 210 #define ESRx_EC_DTLB_MISS       0x00000036      /* - data_access_TLB_miss */
 211 #define ESRx_EC_DATA_ACCESS_DAT 0x0000003a      /* - data_access_DAT_exception */
 212
 213 #define ESR0_IAEC               0x00000100      /* info for instruction-access-exception */
 214 #define ESR0_IAEC_RESV          0x00000000      /* - reserved */
 215 #define ESR0_IAEC_PROT_VIOL     0x00000100      /* - protection violation */
 216
 217 #define ESR0_ATXC               0x00f00000      /* address translation exception code */
 218 #define ESR0_ATXC_MMU_MISS      0x00000000      /* - MMU miss exception and more (?) */
 219 #define ESR0_ATXC_MULTI_DAT     0x00800000      /* - multiple DAT entry hit */
 220 #define ESR0_ATXC_MULTI_SAT     0x00900000      /* - multiple SAT entry hit */
 221 #define ESR0_ATXC_AMRTLB_MISS   0x00a00000      /* - MMU/TLB miss exception */
 222 #define ESR0_ATXC_PRIV_EXCEP    0x00c00000      /* - privilege protection fault */
 223 #define ESR0_ATXC_WP_EXCEP      0x00d00000      /* - write protection fault */
 224
 225 #define ESR0_EAV                0x00000800      /* true if EAR0 register valid */
 226 #define ESR15_EAV               0x00000800      /* true if EAR15 register valid */
 227
 228 /*
 229  * ESFR1 - Exception Status Valid Flag Register
 230  */
 231 #define ESFR1_ESR0              0x00000001      /* true if ESR0 is valid */
 232 #define ESFR1_ESR14             0x00004000      /* true if ESR14 is valid */
 233 #define ESFR1_ESR15             0x00008000      /* true if ESR15 is valid */
 234
 235 /*
 236  * MSR - Media Status Register
 237  */
 238 #define MSR0_AOVF               0x00000001      /* overflow exception accrued */
 239 #define MSRx_OVF                0x00000002      /* overflow exception detected */
 240 #define MSRx_SIE                0x0000003c      /* last SIMD instruction exception detected */
 241 #define MSRx_SIE_NONE           0x00000000      /* - none detected */
 242 #define MSRx_SIE_FRkHI_ACCk     0x00000020      /* - exception at FRkHI or ACCk */
 243 #define MSRx_SIE_FRkLO_ACCk1    0x00000010      /* - exception at FRkLO or ACCk+1 */
 244 #define MSRx_SIE_FRk1HI_ACCk2   0x00000008      /* - exception at FRk+1HI or ACCk+2 */
 245 #define MSRx_SIE_FRk1LO_ACCk3   0x00000004      /* - exception at FRk+1LO or ACCk+3 */
 246 #define MSR0_MTT                0x00007000      /* type of last media trap detected */
 247 #define MSR0_MTT_NONE           0x00000000      /* - none detected */
 248 #define MSR0_MTT_OVERFLOW       0x00001000      /* - overflow detected */
 249 #define MSR0_HI                 0x00c00000      /* hardware implementation */
 250 #define MSR0_HI_ROUNDING        0x00000000      /* - rounding mode */
 251 #define MSR0_HI_NONROUNDING     0x00c00000      /* - non-rounding mode */
 252 #define MSR0_EMCI               0x01000000      /* enable media custom instructions */
 253 #define MSR0_SRDAV              0x10000000      /* select rounding mode of MAVEH */
 254 #define MSR0_SRDAV_RDAV         0x00000000      /* - controlled by MSR.RDAV */
 255 #define MSR0_SRDAV_RD           0x10000000      /* - controlled by MSR.RD */
 256 #define MSR0_RDAV               0x20000000      /* rounding mode of MAVEH */
 257 #define MSR0_RDAV_NEAREST_MI    0x00000000      /* - round to nearest minus */
 258 #define MSR0_RDAV_NEAREST_PL    0x20000000      /* - round to nearest plus */
 259 #define MSR0_RD                 0xc0000000      /* rounding mode */
 260 #define MSR0_RD_NEAREST         0x00000000      /* - nearest */
 261 #define MSR0_RD_ZERO            0x40000000      /* - zero */
 262 #define MSR0_RD_POS_INF         0x80000000      /* - postive infinity */
 263 #define MSR0_RD_NEG_INF         0xc0000000      /* - negative infinity */
 264
 265 /*
 266  * IAMPR0-7 - Instruction Address Mapping Register
 267  * DAMPR0-7 - Data Address Mapping Register
 268  */
 269 #define xAMPRx_V                0x00000001      /* register content validity indicator */
 270 #define DAMPRx_WP               0x00000002      /* write protect */
 271 #define DAMPRx_WP_RW            0x00000000      /* - read/write */
 272 #define DAMPRx_WP_RO            0x00000002      /* - read-only */
 273 #define xAMPRx_C                0x00000004      /* cached/uncached */
 274 #define xAMPRx_C_CACHED         0x00000000      /* - cached */
 275 #define xAMPRx_C_UNCACHED       0x00000004      /* - uncached */
 276 #define xAMPRx_S                0x00000008      /* supervisor only */
 277 #define xAMPRx_S_USER           0x00000000      /* - userspace can access */
 278 #define xAMPRx_S_KERNEL         0x00000008      /* - kernel only */
 279 #define xAMPRx_SS               0x000000f0      /* segment size */
 280 #define xAMPRx_SS_16Kb          0x00000000      /* - 16 kilobytes */
 281 #define xAMPRx_SS_64Kb          0x00000010      /* - 64 kilobytes */
 282 #define xAMPRx_SS_256Kb         0x00000020      /* - 256 kilobytes */
 283 #define xAMPRx_SS_1Mb           0x00000030      /* - 1 megabyte */
 284 #define xAMPRx_SS_2Mb           0x00000040      /* - 2 megabytes */
 285 #define xAMPRx_SS_4Mb           0x00000050      /* - 4 megabytes */
 286 #define xAMPRx_SS_8Mb           0x00000060      /* - 8 megabytes */
 287 #define xAMPRx_SS_16Mb          0x00000070      /* - 16 megabytes */
 288 #define xAMPRx_SS_32Mb          0x00000080      /* - 32 megabytes */
 289 #define xAMPRx_SS_64Mb          0x00000090      /* - 64 megabytes */
 290 #define xAMPRx_SS_128Mb         0x000000a0      /* - 128 megabytes */
 291 #define xAMPRx_SS_256Mb         0x000000b0      /* - 256 megabytes */
 292 #define xAMPRx_SS_512Mb         0x000000c0      /* - 512 megabytes */
 293 #define xAMPRx_RESERVED8        0x00000100      /* reserved bit */
 294 #define xAMPRx_NG               0x00000200      /* non-global */
 295 #define xAMPRx_L                0x00000400      /* locked */
 296 #define xAMPRx_M                0x00000800      /* modified */
 297 #define xAMPRx_D                0x00001000      /* DAT entry */
 298 #define xAMPRx_RESERVED13       0x00002000      /* reserved bit */
 299 #define xAMPRx_PPFN             0xfff00000      /* physical page frame number */
 300
 301 #define xAMPRx_V_BIT            0
 302 #define DAMPRx_WP_BIT           1
 303 #define xAMPRx_C_BIT            2
 304 #define xAMPRx_S_BIT            3
 305 #define xAMPRx_RESERVED8_BIT    8
 306 #define xAMPRx_NG_BIT           9
 307 #define xAMPRx_L_BIT            10
 308 #define xAMPRx_M_BIT            11
 309 #define xAMPRx_D_BIT            12
 310 #define xAMPRx_RESERVED13_BIT   13
 311
 312 #define __get_IAMPR(R) ({ unsigned long x; asm volatile("movsg iampr"#R",%0" : "=r"(x)); x; })
 313 #define __get_DAMPR(R) ({ unsigned long x; asm volatile("movsg dampr"#R",%0" : "=r"(x)); x; })
 314
 315 #define __get_IAMLR(R) ({ unsigned long x; asm volatile("movsg iamlr"#R",%0" : "=r"(x)); x; })
 316 #define __get_DAMLR(R) ({ unsigned long x; asm volatile("movsg damlr"#R",%0" : "=r"(x)); x; })
 317
 318 #define __set_IAMPR(R,V)        do { asm volatile("movgs %0,iampr"#R : : "r"(V)); } while(0)
 319 #define __set_DAMPR(R,V)        do { asm volatile("movgs %0,dampr"#R : : "r"(V)); } while(0)
 320
 321 #define __set_IAMLR(R,V)        do { asm volatile("movgs %0,iamlr"#R : : "r"(V)); } while(0)
 322 #define __set_DAMLR(R,V)        do { asm volatile("movgs %0,damlr"#R : : "r"(V)); } while(0)
 323
 324 #define save_dampr(R, _dampr)                                   \
 325 do {                                                            \
 326         asm volatile("movsg dampr"R",%0" : "=r"(_dampr));       \
 327 } while(0)
 328
 329 #define restore_dampr(R, _dampr)                        \
 330 do {                                                    \
 331         asm volatile("movgs %0,dampr"R :: "r"(_dampr)); \
 332 } while(0)
 333
 334 /*
 335  * AMCR - Address Mapping Control Register
 336  */
 337 #define AMCR_IAMRN              0x000000ff      /* quantity of IAMPR registers */
 338 #define AMCR_DAMRN              0x0000ff00      /* quantity of DAMPR registers */
 339
 340 /*
 341  * TTBR - Address Translation Table Base Register
 342  */
 343 #define __get_TTBR()            ({ unsigned long x; asm volatile("movsg ttbr,%0" : "=r"(x)); x; })
 344
 345 /*
 346  * TPXR - TLB Probe Extend Register
 347  */
 348 #define TPXR_E                  0x00000001
 349 #define TPXR_LMAX_SHIFT         20
 350 #define TPXR_LMAX_SMASK         0xf
 351 #define TPXR_WMAX_SHIFT         24
 352 #define TPXR_WMAX_SMASK         0xf
 353 #define TPXR_WAY_SHIFT          28
 354 #define TPXR_WAY_SMASK          0xf
 355
 356 /*
 357  * DCR - Debug Control Register
 358  */
 359 #define DCR_IBCE3               0x00000001      /* break on conditional insn pointed to by IBAR3 */
 360 #define DCR_IBE3                0x00000002      /* break on insn pointed to by IBAR3 */
 361 #define DCR_IBCE1               0x00000004      /* break on conditional insn pointed to by IBAR2 */
 362 #define DCR_IBE1                0x00000008      /* break on insn pointed to by IBAR2 */
 363 #define DCR_IBCE2               0x00000010      /* break on conditional insn pointed to by IBAR1 */
 364 #define DCR_IBE2                0x00000020      /* break on insn pointed to by IBAR1 */
 365 #define DCR_IBCE0               0x00000040      /* break on conditional insn pointed to by IBAR0 */
 366 #define DCR_IBE0                0x00000080      /* break on insn pointed to by IBAR0 */
 367
 368 #define DCR_DDBE1               0x00004000      /* use DBDR1x when checking DBAR1 */
 369 #define DCR_DWBE1               0x00008000      /* break on store to address in DBAR1/DBMR1x */
 370 #define DCR_DRBE1               0x00010000      /* break on load from address in DBAR1/DBMR1x */
 371 #define DCR_DDBE0               0x00020000      /* use DBDR0x when checking DBAR0 */
 372 #define DCR_DWBE0               0x00040000      /* break on store to address in DBAR0/DBMR0x */
 373 #define DCR_DRBE0               0x00080000      /* break on load from address in DBAR0/DBMR0x */
 374
 375 #define DCR_EIM                 0x0c000000      /* external interrupt disable */
 376 #define DCR_IBM                 0x10000000      /* instruction break disable */
 377 #define DCR_SE                  0x20000000      /* single step enable */
 378 #define DCR_EBE                 0x40000000      /* exception break enable */
 379
 380 /*
 381  * BRR - Break Interrupt Request Register
 382  */
 383 #define BRR_ST                  0x00000001      /* single-step detected */
 384 #define BRR_SB                  0x00000002      /* break instruction detected */
 385 #define BRR_BB                  0x00000004      /* branch with hint detected */
 386 #define BRR_CBB                 0x00000008      /* branch to LR detected */
 387 #define BRR_IBx                 0x000000f0      /* hardware breakpoint detected */
 388 #define BRR_DBx                 0x00000f00      /* hardware watchpoint detected */
 389 #define BRR_DBNEx               0x0000f000      /* ? */
 390 #define BRR_EBTT                0x00ff0000      /* trap type of exception break */
 391 #define BRR_TB                  0x10000000      /* external break request detected */
 392 #define BRR_CB                  0x20000000      /* ICE break command detected */
 393 #define BRR_EB                  0x40000000      /* exception break detected */
 394
 395 /*
 396  * BPSR - Break PSR Save Register
 397  */
 398 #define BPSR_BET                0x00000001      /* former PSR.ET */
 399 #define BPSR_BS                 0x00001000      /* former PSR.S */
 400
 401 #endif /* _ASM_SPR_REGS_H */